arch/x86/include/asm/uv/uv_mmrs.h

   1
   2 /*
   3  * This file is subject to the terms and conditions of the GNU General Public
   4  * License.  See the file "COPYING" in the main directory of this archive
   5  * for more details.
   6  *
   7  * SGI UV MMR definitions
   8  *
   9  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
  10  */
  11
  12 #ifndef _ASM_X86_UV_UV_MMRS_H
  13 #define _ASM_X86_UV_UV_MMRS_H
  14
  15 #define UV_MMR_ENABLE           (1UL << 63)
  16
  17 /* ========================================================================= */
  18 /*                           UVH_BAU_DATA_CONFIG                             */
  19 /* ========================================================================= */
  20 #define UVH_LB_BAU_MISC_CONTROL 0x320170UL
  21 #define UV_ENABLE_INTD_SOFT_ACK_MODE_SHIFT 15
  22 #define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHIFT 16
  23 #define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD 0x000000000bUL
  24 /* 1011 timebase 7 (168millisec) * 3 ticks -> 500ms */
  25 #define UVH_BAU_DATA_CONFIG 0x61680UL
  26 #define UVH_BAU_DATA_CONFIG_32 0x0438
  27
  28 #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
  29 #define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
  30 #define UVH_BAU_DATA_CONFIG_DM_SHFT 8
  31 #define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
  32 #define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11
  33 #define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
  34 #define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12
  35 #define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
  36 #define UVH_BAU_DATA_CONFIG_P_SHFT 13
  37 #define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
  38 #define UVH_BAU_DATA_CONFIG_T_SHFT 15
  39 #define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
  40 #define UVH_BAU_DATA_CONFIG_M_SHFT 16
  41 #define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
  42 #define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32
  43 #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
  44
  45 union uvh_bau_data_config_u {
  46     unsigned long       v;
  47     struct uvh_bau_data_config_s {
  48         unsigned long   vector_  :  8;  /* RW */
  49         unsigned long   dm       :  3;  /* RW */
  50         unsigned long   destmode :  1;  /* RW */
  51         unsigned long   status   :  1;  /* RO */
  52         unsigned long   p        :  1;  /* RO */
  53         unsigned long   rsvd_14  :  1;  /*    */
  54         unsigned long   t        :  1;  /* RO */
  55         unsigned long   m        :  1;  /* RW */
  56         unsigned long   rsvd_17_31: 15;  /*    */
  57         unsigned long   apic_id  : 32;  /* RW */
  58     } s;
  59 };
  60
  61 /* ========================================================================= */
  62 /*                           UVH_EVENT_OCCURRED0                             */
  63 /* ========================================================================= */
  64 #define UVH_EVENT_OCCURRED0 0x70000UL
  65 #define UVH_EVENT_OCCURRED0_32 0x005e8
  66
  67 #define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0
  68 #define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
  69 #define UVH_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
  70 #define UVH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
  71 #define UVH_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
  72 #define UVH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
  73 #define UVH_EVENT_OCCURRED0_LH_HCERR_SHFT 3
  74 #define UVH_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
  75 #define UVH_EVENT_OCCURRED0_RH_HCERR_SHFT 4
  76 #define UVH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL
  77 #define UVH_EVENT_OCCURRED0_XN_HCERR_SHFT 5
  78 #define UVH_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL
  79 #define UVH_EVENT_OCCURRED0_SI_HCERR_SHFT 6
  80 #define UVH_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL
  81 #define UVH_EVENT_OCCURRED0_LB_AOERR0_SHFT 7
  82 #define UVH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL
  83 #define UVH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
  84 #define UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
  85 #define UVH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
  86 #define UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
  87 #define UVH_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
  88 #define UVH_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
  89 #define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
  90 #define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
  91 #define UVH_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
  92 #define UVH_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
  93 #define UVH_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
  94 #define UVH_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
  95 #define UVH_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
  96 #define UVH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
  97 #define UVH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15
  98 #define UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL
  99 #define UVH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16
 100 #define UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL
 101 #define UVH_EVENT_OCCURRED0_LH_AOERR1_SHFT 17
 102 #define UVH_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL
 103 #define UVH_EVENT_OCCURRED0_RH_AOERR1_SHFT 18
 104 #define UVH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL
 105 #define UVH_EVENT_OCCURRED0_XN_AOERR1_SHFT 19
 106 #define UVH_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL
 107 #define UVH_EVENT_OCCURRED0_SI_AOERR1_SHFT 20
 108 #define UVH_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL
 109 #define UVH_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21
 110 #define UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL
 111 #define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22
 112 #define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
 113 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23
 114 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL
 115 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24
 116 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL
 117 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25
 118 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL
 119 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26
 120 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL
 121 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27
 122 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL
 123 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28
 124 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL
 125 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29
 126 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL
 127 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30
 128 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL
 129 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31
 130 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL
 131 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32
 132 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL
 133 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33
 134 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL
 135 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34
 136 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL
 137 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35
 138 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL
 139 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36
 140 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL
 141 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37
 142 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL
 143 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38
 144 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL
 145 #define UVH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39
 146 #define UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL
 147 #define UVH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40
 148 #define UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL
 149 #define UVH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41
 150 #define UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL
 151 #define UVH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42
 152 #define UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL
 153 #define UVH_EVENT_OCCURRED0_LTC_INT_SHFT 43
 154 #define UVH_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL
 155 #define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44
 156 #define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
 157 #define UVH_EVENT_OCCURRED0_IPI_INT_SHFT 45
 158 #define UVH_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL
 159 #define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46
 160 #define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL
 161 #define UVH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47
 162 #define UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL
 163 #define UVH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48
 164 #define UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL
 165 #define UVH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49
 166 #define UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL
 167 #define UVH_EVENT_OCCURRED0_PROFILE_INT_SHFT 50
 168 #define UVH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL
 169 #define UVH_EVENT_OCCURRED0_RTC0_SHFT 51
 170 #define UVH_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL
 171 #define UVH_EVENT_OCCURRED0_RTC1_SHFT 52
 172 #define UVH_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL
 173 #define UVH_EVENT_OCCURRED0_RTC2_SHFT 53
 174 #define UVH_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL
 175 #define UVH_EVENT_OCCURRED0_RTC3_SHFT 54
 176 #define UVH_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL
 177 #define UVH_EVENT_OCCURRED0_BAU_DATA_SHFT 55
 178 #define UVH_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
 179 #define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
 180 #define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
 181 union uvh_event_occurred0_u {
 182     unsigned long       v;
 183     struct uvh_event_occurred0_s {
 184         unsigned long   lb_hcerr             :  1;  /* RW, W1C */
 185         unsigned long   gr0_hcerr            :  1;  /* RW, W1C */
 186         unsigned long   gr1_hcerr            :  1;  /* RW, W1C */
 187         unsigned long   lh_hcerr             :  1;  /* RW, W1C */
 188         unsigned long   rh_hcerr             :  1;  /* RW, W1C */
 189         unsigned long   xn_hcerr             :  1;  /* RW, W1C */
 190         unsigned long   si_hcerr             :  1;  /* RW, W1C */
 191         unsigned long   lb_aoerr0            :  1;  /* RW, W1C */
 192         unsigned long   gr0_aoerr0           :  1;  /* RW, W1C */
 193         unsigned long   gr1_aoerr0           :  1;  /* RW, W1C */
 194         unsigned long   lh_aoerr0            :  1;  /* RW, W1C */
 195         unsigned long   rh_aoerr0            :  1;  /* RW, W1C */
 196         unsigned long   xn_aoerr0            :  1;  /* RW, W1C */
 197         unsigned long   si_aoerr0            :  1;  /* RW, W1C */
 198         unsigned long   lb_aoerr1            :  1;  /* RW, W1C */
 199         unsigned long   gr0_aoerr1           :  1;  /* RW, W1C */
 200         unsigned long   gr1_aoerr1           :  1;  /* RW, W1C */
 201         unsigned long   lh_aoerr1            :  1;  /* RW, W1C */
 202         unsigned long   rh_aoerr1            :  1;  /* RW, W1C */
 203         unsigned long   xn_aoerr1            :  1;  /* RW, W1C */
 204         unsigned long   si_aoerr1            :  1;  /* RW, W1C */
 205         unsigned long   rh_vpi_int           :  1;  /* RW, W1C */
 206         unsigned long   system_shutdown_int  :  1;  /* RW, W1C */
 207         unsigned long   lb_irq_int_0         :  1;  /* RW, W1C */
 208         unsigned long   lb_irq_int_1         :  1;  /* RW, W1C */
 209         unsigned long   lb_irq_int_2         :  1;  /* RW, W1C */
 210         unsigned long   lb_irq_int_3         :  1;  /* RW, W1C */
 211         unsigned long   lb_irq_int_4         :  1;  /* RW, W1C */
 212         unsigned long   lb_irq_int_5         :  1;  /* RW, W1C */
 213         unsigned long   lb_irq_int_6         :  1;  /* RW, W1C */
 214         unsigned long   lb_irq_int_7         :  1;  /* RW, W1C */
 215         unsigned long   lb_irq_int_8         :  1;  /* RW, W1C */
 216         unsigned long   lb_irq_int_9         :  1;  /* RW, W1C */
 217         unsigned long   lb_irq_int_10        :  1;  /* RW, W1C */
 218         unsigned long   lb_irq_int_11        :  1;  /* RW, W1C */
 219         unsigned long   lb_irq_int_12        :  1;  /* RW, W1C */
 220         unsigned long   lb_irq_int_13        :  1;  /* RW, W1C */
 221         unsigned long   lb_irq_int_14        :  1;  /* RW, W1C */
 222         unsigned long   lb_irq_int_15        :  1;  /* RW, W1C */
 223         unsigned long   l1_nmi_int           :  1;  /* RW, W1C */
 224         unsigned long   stop_clock           :  1;  /* RW, W1C */
 225         unsigned long   asic_to_l1           :  1;  /* RW, W1C */
 226         unsigned long   l1_to_asic           :  1;  /* RW, W1C */
 227         unsigned long   ltc_int              :  1;  /* RW, W1C */
 228         unsigned long   la_seq_trigger       :  1;  /* RW, W1C */
 229         unsigned long   ipi_int              :  1;  /* RW, W1C */
 230         unsigned long   extio_int0           :  1;  /* RW, W1C */
 231         unsigned long   extio_int1           :  1;  /* RW, W1C */
 232         unsigned long   extio_int2           :  1;  /* RW, W1C */
 233         unsigned long   extio_int3           :  1;  /* RW, W1C */
 234         unsigned long   profile_int          :  1;  /* RW, W1C */
 235         unsigned long   rtc0                 :  1;  /* RW, W1C */
 236         unsigned long   rtc1                 :  1;  /* RW, W1C */
 237         unsigned long   rtc2                 :  1;  /* RW, W1C */
 238         unsigned long   rtc3                 :  1;  /* RW, W1C */
 239         unsigned long   bau_data             :  1;  /* RW, W1C */
 240         unsigned long   power_management_req :  1;  /* RW, W1C */
 241         unsigned long   rsvd_57_63           :  7;  /*    */
 242     } s;
 243 };
 244
 245 /* ========================================================================= */
 246 /*                        UVH_EVENT_OCCURRED0_ALIAS                          */
 247 /* ========================================================================= */
 248 #define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL
 249 #define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0
 250
 251 /* ========================================================================= */
 252 /*                         UVH_GR0_TLB_INT0_CONFIG                           */
 253 /* ========================================================================= */
 254 #define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL
 255
 256 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
 257 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
 258 #define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8
 259 #define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
 260 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
 261 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
 262 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
 263 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
 264 #define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13
 265 #define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
 266 #define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15
 267 #define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
 268 #define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16
 269 #define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
 270 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
 271 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
 272
 273 union uvh_gr0_tlb_int0_config_u {
 274     unsigned long       v;
 275     struct uvh_gr0_tlb_int0_config_s {
 276         unsigned long   vector_  :  8;  /* RW */
 277         unsigned long   dm       :  3;  /* RW */
 278         unsigned long   destmode :  1;  /* RW */
 279         unsigned long   status   :  1;  /* RO */
 280         unsigned long   p        :  1;  /* RO */
 281         unsigned long   rsvd_14  :  1;  /*    */
 282         unsigned long   t        :  1;  /* RO */
 283         unsigned long   m        :  1;  /* RW */
 284         unsigned long   rsvd_17_31: 15;  /*    */
 285         unsigned long   apic_id  : 32;  /* RW */
 286     } s;
 287 };
 288
 289 /* ========================================================================= */
 290 /*                         UVH_GR0_TLB_INT1_CONFIG                           */
 291 /* ========================================================================= */
 292 #define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL
 293
 294 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0
 295 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
 296 #define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8
 297 #define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
 298 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11
 299 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
 300 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12
 301 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
 302 #define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13
 303 #define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
 304 #define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15
 305 #define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
 306 #define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16
 307 #define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
 308 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32
 309 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
 310
 311 union uvh_gr0_tlb_int1_config_u {
 312     unsigned long       v;
 313     struct uvh_gr0_tlb_int1_config_s {
 314         unsigned long   vector_  :  8;  /* RW */
 315         unsigned long   dm       :  3;  /* RW */
 316         unsigned long   destmode :  1;  /* RW */
 317         unsigned long   status   :  1;  /* RO */
 318         unsigned long   p        :  1;  /* RO */
 319         unsigned long   rsvd_14  :  1;  /*    */
 320         unsigned long   t        :  1;  /* RO */
 321         unsigned long   m        :  1;  /* RW */
 322         unsigned long   rsvd_17_31: 15;  /*    */
 323         unsigned long   apic_id  : 32;  /* RW */
 324     } s;
 325 };
 326
 327 /* ========================================================================= */
 328 /*                         UVH_GR1_TLB_INT0_CONFIG                           */
 329 /* ========================================================================= */
 330 #define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL
 331
 332 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0
 333 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
 334 #define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8
 335 #define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
 336 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11
 337 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
 338 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12
 339 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
 340 #define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13
 341 #define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
 342 #define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15
 343 #define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
 344 #define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16
 345 #define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
 346 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32
 347 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
 348
 349 union uvh_gr1_tlb_int0_config_u {
 350     unsigned long       v;
 351     struct uvh_gr1_tlb_int0_config_s {
 352         unsigned long   vector_  :  8;  /* RW */
 353         unsigned long   dm       :  3;  /* RW */
 354         unsigned long   destmode :  1;  /* RW */
 355         unsigned long   status   :  1;  /* RO */
 356         unsigned long   p        :  1;  /* RO */
 357         unsigned long   rsvd_14  :  1;  /*    */
 358         unsigned long   t        :  1;  /* RO */
 359         unsigned long   m        :  1;  /* RW */
 360         unsigned long   rsvd_17_31: 15;  /*    */
 361         unsigned long   apic_id  : 32;  /* RW */
 362     } s;
 363 };
 364
 365 /* ========================================================================= */
 366 /*                         UVH_GR1_TLB_INT1_CONFIG                           */
 367 /* ========================================================================= */
 368 #define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL
 369
 370 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0
 371 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
 372 #define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8
 373 #define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
 374 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11
 375 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
 376 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12
 377 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
 378 #define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13
 379 #define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
 380 #define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15
 381 #define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
 382 #define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16
 383 #define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
 384 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32
 385 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
 386
 387 union uvh_gr1_tlb_int1_config_u {
 388     unsigned long       v;
 389     struct uvh_gr1_tlb_int1_config_s {
 390         unsigned long   vector_  :  8;  /* RW */
 391         unsigned long   dm       :  3;  /* RW */
 392         unsigned long   destmode :  1;  /* RW */
 393         unsigned long   status   :  1;  /* RO */
 394         unsigned long   p        :  1;  /* RO */
 395         unsigned long   rsvd_14  :  1;  /*    */
 396         unsigned long   t        :  1;  /* RO */
 397         unsigned long   m        :  1;  /* RW */
 398         unsigned long   rsvd_17_31: 15;  /*    */
 399         unsigned long   apic_id  : 32;  /* RW */
 400     } s;
 401 };
 402
 403 /* ========================================================================= */
 404 /*                               UVH_INT_CMPB                                */
 405 /* ========================================================================= */
 406 #define UVH_INT_CMPB 0x22080UL
 407
 408 #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
 409 #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
 410
 411 union uvh_int_cmpb_u {
 412     unsigned long       v;
 413     struct uvh_int_cmpb_s {
 414         unsigned long   real_time_cmpb : 56;  /* RW */
 415         unsigned long   rsvd_56_63     :  8;  /*    */
 416     } s;
 417 };
 418
 419 /* ========================================================================= */
 420 /*                               UVH_INT_CMPC                                */
 421 /* ========================================================================= */
 422 #define UVH_INT_CMPC 0x22100UL
 423
 424 #define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
 425 #define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL
 426
 427 union uvh_int_cmpc_u {
 428     unsigned long       v;
 429     struct uvh_int_cmpc_s {
 430         unsigned long   real_time_cmpc : 56;  /* RW */
 431         unsigned long   rsvd_56_63     :  8;  /*    */
 432     } s;
 433 };
 434
 435 /* ========================================================================= */
 436 /*                               UVH_INT_CMPD                                */
 437 /* ========================================================================= */
 438 #define UVH_INT_CMPD 0x22180UL
 439
 440 #define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
 441 #define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL
 442
 443 union uvh_int_cmpd_u {
 444     unsigned long       v;
 445     struct uvh_int_cmpd_s {
 446         unsigned long   real_time_cmpd : 56;  /* RW */
 447         unsigned long   rsvd_56_63     :  8;  /*    */
 448     } s;
 449 };
 450
 451 /* ========================================================================= */
 452 /*                               UVH_IPI_INT                                 */
 453 /* ========================================================================= */
 454 #define UVH_IPI_INT 0x60500UL
 455 #define UVH_IPI_INT_32 0x0348
 456
 457 #define UVH_IPI_INT_VECTOR_SHFT 0
 458 #define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL
 459 #define UVH_IPI_INT_DELIVERY_MODE_SHFT 8
 460 #define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL
 461 #define UVH_IPI_INT_DESTMODE_SHFT 11
 462 #define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL
 463 #define UVH_IPI_INT_APIC_ID_SHFT 16
 464 #define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL
 465 #define UVH_IPI_INT_SEND_SHFT 63
 466 #define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL
 467
 468 union uvh_ipi_int_u {
 469     unsigned long       v;
 470     struct uvh_ipi_int_s {
 471         unsigned long   vector_       :  8;  /* RW */
 472         unsigned long   delivery_mode :  3;  /* RW */
 473         unsigned long   destmode      :  1;  /* RW */
 474         unsigned long   rsvd_12_15    :  4;  /*    */
 475         unsigned long   apic_id       : 32;  /* RW */
 476         unsigned long   rsvd_48_62    : 15;  /*    */
 477         unsigned long   send          :  1;  /* WP */
 478     } s;
 479 };
 480
 481 /* ========================================================================= */
 482 /*                   UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST                     */
 483 /* ========================================================================= */
 484 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
 485 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x009c0
 486
 487 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
 488 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
 489 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
 490 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
 491
 492 union uvh_lb_bau_intd_payload_queue_first_u {
 493     unsigned long       v;
 494     struct uvh_lb_bau_intd_payload_queue_first_s {
 495         unsigned long   rsvd_0_3:  4;  /*    */
 496         unsigned long   address : 39;  /* RW */
 497         unsigned long   rsvd_43_48:  6;  /*    */
 498         unsigned long   node_id : 14;  /* RW */
 499         unsigned long   rsvd_63 :  1;  /*    */
 500     } s;
 501 };
 502
 503 /* ========================================================================= */
 504 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST                     */
 505 /* ========================================================================= */
 506 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
 507 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x009c8
 508
 509 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
 510 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
 511
 512 union uvh_lb_bau_intd_payload_queue_last_u {
 513     unsigned long       v;
 514     struct uvh_lb_bau_intd_payload_queue_last_s {
 515         unsigned long   rsvd_0_3:  4;  /*    */
 516         unsigned long   address : 39;  /* RW */
 517         unsigned long   rsvd_43_63: 21;  /*    */
 518     } s;
 519 };
 520
 521 /* ========================================================================= */
 522 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL                     */
 523 /* ========================================================================= */
 524 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
 525 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x009d0
 526
 527 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
 528 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
 529
 530 union uvh_lb_bau_intd_payload_queue_tail_u {
 531     unsigned long       v;
 532     struct uvh_lb_bau_intd_payload_queue_tail_s {
 533         unsigned long   rsvd_0_3:  4;  /*    */
 534         unsigned long   address : 39;  /* RW */
 535         unsigned long   rsvd_43_63: 21;  /*    */
 536     } s;
 537 };
 538
 539 /* ========================================================================= */
 540 /*                   UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE                    */
 541 /* ========================================================================= */
 542 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
 543 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x0a68
 544
 545 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
 546 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
 547 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
 548 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
 549 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
 550 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
 551 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
 552 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
 553 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
 554 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
 555 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
 556 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
 557 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
 558 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
 559 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
 560 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
 561 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
 562 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
 563 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
 564 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
 565 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
 566 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
 567 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
 568 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
 569 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
 570 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
 571 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
 572 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
 573 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
 574 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
 575 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
 576 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
 577 union uvh_lb_bau_intd_software_acknowledge_u {
 578     unsigned long       v;
 579     struct uvh_lb_bau_intd_software_acknowledge_s {
 580         unsigned long   pending_0 :  1;  /* RW, W1C */
 581         unsigned long   pending_1 :  1;  /* RW, W1C */
 582         unsigned long   pending_2 :  1;  /* RW, W1C */
 583         unsigned long   pending_3 :  1;  /* RW, W1C */
 584         unsigned long   pending_4 :  1;  /* RW, W1C */
 585         unsigned long   pending_5 :  1;  /* RW, W1C */
 586         unsigned long   pending_6 :  1;  /* RW, W1C */
 587         unsigned long   pending_7 :  1;  /* RW, W1C */
 588         unsigned long   timeout_0 :  1;  /* RW, W1C */
 589         unsigned long   timeout_1 :  1;  /* RW, W1C */
 590         unsigned long   timeout_2 :  1;  /* RW, W1C */
 591         unsigned long   timeout_3 :  1;  /* RW, W1C */
 592         unsigned long   timeout_4 :  1;  /* RW, W1C */
 593         unsigned long   timeout_5 :  1;  /* RW, W1C */
 594         unsigned long   timeout_6 :  1;  /* RW, W1C */
 595         unsigned long   timeout_7 :  1;  /* RW, W1C */
 596         unsigned long   rsvd_16_63: 48;  /*    */
 597     } s;
 598 };
 599
 600 /* ========================================================================= */
 601 /*                UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS                 */
 602 /* ========================================================================= */
 603 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL
 604 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x0a70
 605
 606 /* ========================================================================= */
 607 /*                     UVH_LB_BAU_SB_ACTIVATION_CONTROL                      */
 608 /* ========================================================================= */
 609 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
 610 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x009a8
 611
 612 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
 613 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL
 614 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62
 615 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL
 616 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63
 617 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL
 618
 619 union uvh_lb_bau_sb_activation_control_u {
 620     unsigned long       v;
 621     struct uvh_lb_bau_sb_activation_control_s {
 622         unsigned long   index :  6;  /* RW */
 623         unsigned long   rsvd_6_61: 56;  /*    */
 624         unsigned long   push  :  1;  /* WP */
 625         unsigned long   init  :  1;  /* WP */
 626     } s;
 627 };
 628
 629 /* ========================================================================= */
 630 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_0                      */
 631 /* ========================================================================= */
 632 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
 633 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x009b0
 634
 635 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
 636 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
 637
 638 union uvh_lb_bau_sb_activation_status_0_u {
 639     unsigned long       v;
 640     struct uvh_lb_bau_sb_activation_status_0_s {
 641         unsigned long   status : 64;  /* RW */
 642     } s;
 643 };
 644
 645 /* ========================================================================= */
 646 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_1                      */
 647 /* ========================================================================= */
 648 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
 649 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x009b8
 650
 651 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
 652 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
 653
 654 union uvh_lb_bau_sb_activation_status_1_u {
 655     unsigned long       v;
 656     struct uvh_lb_bau_sb_activation_status_1_s {
 657         unsigned long   status : 64;  /* RW */
 658     } s;
 659 };
 660
 661 /* ========================================================================= */
 662 /*                      UVH_LB_BAU_SB_DESCRIPTOR_BASE                        */
 663 /* ========================================================================= */
 664 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
 665 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x009a0
 666
 667 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
 668 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
 669 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49
 670 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL
 671
 672 union uvh_lb_bau_sb_descriptor_base_u {
 673     unsigned long       v;
 674     struct uvh_lb_bau_sb_descriptor_base_s {
 675         unsigned long   rsvd_0_11    : 12;  /*    */
 676         unsigned long   page_address : 31;  /* RW */
 677         unsigned long   rsvd_43_48   :  6;  /*    */
 678         unsigned long   node_id      : 14;  /* RW */
 679         unsigned long   rsvd_63      :  1;  /*    */
 680     } s;
 681 };
 682
 683 /* ========================================================================= */
 684 /*                      UVH_LB_MCAST_AOERR0_RPT_ENABLE                       */
 685 /* ========================================================================= */
 686 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE 0x50b20UL
 687
 688 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_OBESE_MSG_SHFT 0
 689 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_OBESE_MSG_MASK 0x0000000000000001UL
 690 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_DATA_SB_ERR_SHFT 1
 691 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_DATA_SB_ERR_MASK 0x0000000000000002UL
 692 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_NACK_BUFF_PARITY_SHFT 2
 693 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_NACK_BUFF_PARITY_MASK 0x0000000000000004UL
 694 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_TIMEOUT_SHFT 3
 695 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_TIMEOUT_MASK 0x0000000000000008UL
 696 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_INACTIVE_REPLY_SHFT 4
 697 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_INACTIVE_REPLY_MASK 0x0000000000000010UL
 698 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_UPGRADE_ERROR_SHFT 5
 699 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_UPGRADE_ERROR_MASK 0x0000000000000020UL
 700 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REG_COUNT_UNDERFLOW_SHFT 6
 701 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REG_COUNT_UNDERFLOW_MASK 0x0000000000000040UL
 702 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REP_OBESE_MSG_SHFT 7
 703 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REP_OBESE_MSG_MASK 0x0000000000000080UL
 704 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_RUNT_MSG_SHFT 8
 705 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_RUNT_MSG_MASK 0x0000000000000100UL
 706 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_OBESE_MSG_SHFT 9
 707 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_OBESE_MSG_MASK 0x0000000000000200UL
 708 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_DATA_SB_ERR_SHFT 10
 709 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_DATA_SB_ERR_MASK 0x0000000000000400UL
 710 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_RUNT_MSG_SHFT 11
 711 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_RUNT_MSG_MASK 0x0000000000000800UL
 712 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_OBESE_MSG_SHFT 12
 713 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_OBESE_MSG_MASK 0x0000000000001000UL
 714 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_DATA_SB_ERR_SHFT 13
 715 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_DATA_SB_ERR_MASK 0x0000000000002000UL
 716 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_COMMAND_ERR_SHFT 14
 717 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_COMMAND_ERR_MASK 0x0000000000004000UL
 718 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_PEND_TIMEOUT_SHFT 15
 719 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_PEND_TIMEOUT_MASK 0x0000000000008000UL
 720 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_RUNT_MSG_SHFT 16
 721 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_RUNT_MSG_MASK 0x0000000000010000UL
 722 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_OBESE_MSG_SHFT 17
 723 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_OBESE_MSG_MASK 0x0000000000020000UL
 724 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_DATA_SB_ERR_SHFT 18
 725 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_DATA_SB_ERR_MASK 0x0000000000040000UL
 726 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_RUNT_MSG_SHFT 19
 727 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_RUNT_MSG_MASK 0x0000000000080000UL
 728 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_SHFT 20
 729 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_MASK 0x0000000000100000UL
 730 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_SHFT 21
 731 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_MASK 0x0000000000200000UL
 732 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_AMO_TIMEOUT_SHFT 22
 733 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_AMO_TIMEOUT_MASK 0x0000000000400000UL
 734 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_PUT_TIMEOUT_SHFT 23
 735 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_PUT_TIMEOUT_MASK 0x0000000000800000UL
 736 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_SHFT 24
 737 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_MASK 0x0000000001000000UL
 738 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_SHFT 25
 739 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_MASK 0x0000000002000000UL
 740 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_SHFT 26
 741 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_MASK 0x0000000004000000UL
 742 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_SHFT 27
 743 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_MASK 0x0000000008000000UL
 744 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_SHFT 28
 745 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_MASK 0x0000000010000000UL
 746 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_SHFT 29
 747 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_MASK 0x0000000020000000UL
 748 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_SHFT 30
 749 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_MASK 0x0000000040000000UL
 750 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_SHFT 31
 751 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_MASK 0x0000000080000000UL
 752 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_SHFT 32
 753 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_MASK 0x0000000100000000UL
 754 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_SHFT 33
 755 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_MASK 0x0000000200000000UL
 756 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_SHFT 34
 757 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_MASK 0x0000000400000000UL
 758 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_SHFT 35
 759 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_MASK 0x0000000800000000UL
 760 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_SHFT 36
 761 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_MASK 0x0000001000000000UL
 762 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_SHFT 37
 763 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_MASK 0x0000002000000000UL
 764 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_SHFT 38
 765 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_MASK 0x0000004000000000UL
 766 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_SHFT 39
 767 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_MASK 0x0000008000000000UL
 768 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_SHFT 40
 769 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_MASK 0x0000010000000000UL
 770 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_SHFT 41
 771 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_MASK 0x0000020000000000UL
 772 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_SHFT 42
 773 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_MASK 0x0000040000000000UL
 774
 775 union uvh_lb_mcast_aoerr0_rpt_enable_u {
 776     unsigned long       v;
 777     struct uvh_lb_mcast_aoerr0_rpt_enable_s {
 778         unsigned long   mcast_obese_msg                         :  1;  /* RW */
 779         unsigned long   mcast_data_sb_err                       :  1;  /* RW */
 780         unsigned long   mcast_nack_buff_parity                  :  1;  /* RW */
 781         unsigned long   mcast_timeout                           :  1;  /* RW */
 782         unsigned long   mcast_inactive_reply                    :  1;  /* RW */
 783         unsigned long   mcast_upgrade_error                     :  1;  /* RW */
 784         unsigned long   mcast_reg_count_underflow               :  1;  /* RW */
 785         unsigned long   mcast_rep_obese_msg                     :  1;  /* RW */
 786         unsigned long   ucache_req_runt_msg                     :  1;  /* RW */
 787         unsigned long   ucache_req_obese_msg                    :  1;  /* RW */
 788         unsigned long   ucache_req_data_sb_err                  :  1;  /* RW */
 789         unsigned long   ucache_rep_runt_msg                     :  1;  /* RW */
 790         unsigned long   ucache_rep_obese_msg                    :  1;  /* RW */
 791         unsigned long   ucache_rep_data_sb_err                  :  1;  /* RW */
 792         unsigned long   ucache_rep_command_err                  :  1;  /* RW */
 793         unsigned long   ucache_pend_timeout                     :  1;  /* RW */
 794         unsigned long   macc_req_runt_msg                       :  1;  /* RW */
 795         unsigned long   macc_req_obese_msg                      :  1;  /* RW */
 796         unsigned long   macc_req_data_sb_err                    :  1;  /* RW */
 797         unsigned long   macc_rep_runt_msg                       :  1;  /* RW */
 798         unsigned long   macc_rep_obese_msg                      :  1;  /* RW */
 799         unsigned long   macc_rep_data_sb_err                    :  1;  /* RW */
 800         unsigned long   macc_amo_timeout                        :  1;  /* RW */
 801         unsigned long   macc_put_timeout                        :  1;  /* RW */
 802         unsigned long   macc_spurious_event                     :  1;  /* RW */
 803         unsigned long   ioh_destination_table_parity            :  1;  /* RW */
 804         unsigned long   get_had_error_reply                     :  1;  /* RW */
 805         unsigned long   get_timeout                             :  1;  /* RW */
 806         unsigned long   lock_manager_had_error_reply            :  1;  /* RW */
 807         unsigned long   put_had_error_reply                     :  1;  /* RW */
 808         unsigned long   put_timeout                             :  1;  /* RW */
 809         unsigned long   sb_activation_overrun                   :  1;  /* RW */
 810         unsigned long   completed_gb_activation_had_error_reply :  1;  /* RW */
 811         unsigned long   completed_gb_activation_timeout         :  1;  /* RW */
 812         unsigned long   descriptor_buffer_0_parity              :  1;  /* RW */
 813         unsigned long   descriptor_buffer_1_parity              :  1;  /* RW */
 814         unsigned long   socket_destination_table_parity         :  1;  /* RW */
 815         unsigned long   bau_reply_payload_corruption            :  1;  /* RW */
 816         unsigned long   io_port_destination_table_parity        :  1;  /* RW */
 817         unsigned long   intd_soft_ack_timeout                   :  1;  /* RW */
 818         unsigned long   int_rep_obese_msg                       :  1;  /* RW */
 819         unsigned long   int_rep_command_err                     :  1;  /* RW */
 820         unsigned long   int_timeout                             :  1;  /* RW */
 821         unsigned long   rsvd_43_63                              : 21;  /*    */
 822     } s;
 823 };
 824
 825 /* ========================================================================= */
 826 /*                          UVH_LOCAL_INT0_CONFIG                            */
 827 /* ========================================================================= */
 828 #define UVH_LOCAL_INT0_CONFIG 0x61000UL
 829
 830 #define UVH_LOCAL_INT0_CONFIG_VECTOR_SHFT 0
 831 #define UVH_LOCAL_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
 832 #define UVH_LOCAL_INT0_CONFIG_DM_SHFT 8
 833 #define UVH_LOCAL_INT0_CONFIG_DM_MASK 0x0000000000000700UL
 834 #define UVH_LOCAL_INT0_CONFIG_DESTMODE_SHFT 11
 835 #define UVH_LOCAL_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
 836 #define UVH_LOCAL_INT0_CONFIG_STATUS_SHFT 12
 837 #define UVH_LOCAL_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
 838 #define UVH_LOCAL_INT0_CONFIG_P_SHFT 13
 839 #define UVH_LOCAL_INT0_CONFIG_P_MASK 0x0000000000002000UL
 840 #define UVH_LOCAL_INT0_CONFIG_T_SHFT 15
 841 #define UVH_LOCAL_INT0_CONFIG_T_MASK 0x0000000000008000UL
 842 #define UVH_LOCAL_INT0_CONFIG_M_SHFT 16
 843 #define UVH_LOCAL_INT0_CONFIG_M_MASK 0x0000000000010000UL
 844 #define UVH_LOCAL_INT0_CONFIG_APIC_ID_SHFT 32
 845 #define UVH_LOCAL_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
 846
 847 union uvh_local_int0_config_u {
 848     unsigned long       v;
 849     struct uvh_local_int0_config_s {
 850         unsigned long   vector_  :  8;  /* RW */
 851         unsigned long   dm       :  3;  /* RW */
 852         unsigned long   destmode :  1;  /* RW */
 853         unsigned long   status   :  1;  /* RO */
 854         unsigned long   p        :  1;  /* RO */
 855         unsigned long   rsvd_14  :  1;  /*    */
 856         unsigned long   t        :  1;  /* RO */
 857         unsigned long   m        :  1;  /* RW */
 858         unsigned long   rsvd_17_31: 15;  /*    */
 859         unsigned long   apic_id  : 32;  /* RW */
 860     } s;
 861 };
 862
 863 /* ========================================================================= */
 864 /*                          UVH_LOCAL_INT0_ENABLE                            */
 865 /* ========================================================================= */
 866 #define UVH_LOCAL_INT0_ENABLE 0x65000UL
 867
 868 #define UVH_LOCAL_INT0_ENABLE_LB_HCERR_SHFT 0
 869 #define UVH_LOCAL_INT0_ENABLE_LB_HCERR_MASK 0x0000000000000001UL
 870 #define UVH_LOCAL_INT0_ENABLE_GR0_HCERR_SHFT 1
 871 #define UVH_LOCAL_INT0_ENABLE_GR0_HCERR_MASK 0x0000000000000002UL
 872 #define UVH_LOCAL_INT0_ENABLE_GR1_HCERR_SHFT 2
 873 #define UVH_LOCAL_INT0_ENABLE_GR1_HCERR_MASK 0x0000000000000004UL
 874 #define UVH_LOCAL_INT0_ENABLE_LH_HCERR_SHFT 3
 875 #define UVH_LOCAL_INT0_ENABLE_LH_HCERR_MASK 0x0000000000000008UL
 876 #define UVH_LOCAL_INT0_ENABLE_RH_HCERR_SHFT 4
 877 #define UVH_LOCAL_INT0_ENABLE_RH_HCERR_MASK 0x0000000000000010UL
 878 #define UVH_LOCAL_INT0_ENABLE_XN_HCERR_SHFT 5
 879 #define UVH_LOCAL_INT0_ENABLE_XN_HCERR_MASK 0x0000000000000020UL
 880 #define UVH_LOCAL_INT0_ENABLE_SI_HCERR_SHFT 6
 881 #define UVH_LOCAL_INT0_ENABLE_SI_HCERR_MASK 0x0000000000000040UL
 882 #define UVH_LOCAL_INT0_ENABLE_LB_AOERR0_SHFT 7
 883 #define UVH_LOCAL_INT0_ENABLE_LB_AOERR0_MASK 0x0000000000000080UL
 884 #define UVH_LOCAL_INT0_ENABLE_GR0_AOERR0_SHFT 8
 885 #define UVH_LOCAL_INT0_ENABLE_GR0_AOERR0_MASK 0x0000000000000100UL
 886 #define UVH_LOCAL_INT0_ENABLE_GR1_AOERR0_SHFT 9
 887 #define UVH_LOCAL_INT0_ENABLE_GR1_AOERR0_MASK 0x0000000000000200UL
 888 #define UVH_LOCAL_INT0_ENABLE_LH_AOERR0_SHFT 10
 889 #define UVH_LOCAL_INT0_ENABLE_LH_AOERR0_MASK 0x0000000000000400UL
 890 #define UVH_LOCAL_INT0_ENABLE_RH_AOERR0_SHFT 11
 891 #define UVH_LOCAL_INT0_ENABLE_RH_AOERR0_MASK 0x0000000000000800UL
 892 #define UVH_LOCAL_INT0_ENABLE_XN_AOERR0_SHFT 12
 893 #define UVH_LOCAL_INT0_ENABLE_XN_AOERR0_MASK 0x0000000000001000UL
 894 #define UVH_LOCAL_INT0_ENABLE_SI_AOERR0_SHFT 13
 895 #define UVH_LOCAL_INT0_ENABLE_SI_AOERR0_MASK 0x0000000000002000UL
 896 #define UVH_LOCAL_INT0_ENABLE_LB_AOERR1_SHFT 14
 897 #define UVH_LOCAL_INT0_ENABLE_LB_AOERR1_MASK 0x0000000000004000UL
 898 #define UVH_LOCAL_INT0_ENABLE_GR0_AOERR1_SHFT 15
 899 #define UVH_LOCAL_INT0_ENABLE_GR0_AOERR1_MASK 0x0000000000008000UL
 900 #define UVH_LOCAL_INT0_ENABLE_GR1_AOERR1_SHFT 16
 901 #define UVH_LOCAL_INT0_ENABLE_GR1_AOERR1_MASK 0x0000000000010000UL
 902 #define UVH_LOCAL_INT0_ENABLE_LH_AOERR1_SHFT 17
 903 #define UVH_LOCAL_INT0_ENABLE_LH_AOERR1_MASK 0x0000000000020000UL
 904 #define UVH_LOCAL_INT0_ENABLE_RH_AOERR1_SHFT 18
 905 #define UVH_LOCAL_INT0_ENABLE_RH_AOERR1_MASK 0x0000000000040000UL
 906 #define UVH_LOCAL_INT0_ENABLE_XN_AOERR1_SHFT 19
 907 #define UVH_LOCAL_INT0_ENABLE_XN_AOERR1_MASK 0x0000000000080000UL
 908 #define UVH_LOCAL_INT0_ENABLE_SI_AOERR1_SHFT 20
 909 #define UVH_LOCAL_INT0_ENABLE_SI_AOERR1_MASK 0x0000000000100000UL
 910 #define UVH_LOCAL_INT0_ENABLE_RH_VPI_INT_SHFT 21
 911 #define UVH_LOCAL_INT0_ENABLE_RH_VPI_INT_MASK 0x0000000000200000UL
 912 #define UVH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 22
 913 #define UVH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
 914 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_0_SHFT 23
 915 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_0_MASK 0x0000000000800000UL
 916 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_1_SHFT 24
 917 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_1_MASK 0x0000000001000000UL
 918 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_2_SHFT 25
 919 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_2_MASK 0x0000000002000000UL
 920 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_3_SHFT 26
 921 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_3_MASK 0x0000000004000000UL
 922 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_4_SHFT 27
 923 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_4_MASK 0x0000000008000000UL
 924 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_5_SHFT 28
 925 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_5_MASK 0x0000000010000000UL
 926 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_6_SHFT 29
 927 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_6_MASK 0x0000000020000000UL
 928 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_7_SHFT 30
 929 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_7_MASK 0x0000000040000000UL
 930 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_8_SHFT 31
 931 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_8_MASK 0x0000000080000000UL
 932 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_9_SHFT 32
 933 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_9_MASK 0x0000000100000000UL
 934 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_10_SHFT 33
 935 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_10_MASK 0x0000000200000000UL
 936 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_11_SHFT 34
 937 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_11_MASK 0x0000000400000000UL
 938 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_12_SHFT 35
 939 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_12_MASK 0x0000000800000000UL
 940 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_13_SHFT 36
 941 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_13_MASK 0x0000001000000000UL
 942 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_14_SHFT 37
 943 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_14_MASK 0x0000002000000000UL
 944 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_15_SHFT 38
 945 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_15_MASK 0x0000004000000000UL
 946 #define UVH_LOCAL_INT0_ENABLE_L1_NMI_INT_SHFT 39
 947 #define UVH_LOCAL_INT0_ENABLE_L1_NMI_INT_MASK 0x0000008000000000UL
 948 #define UVH_LOCAL_INT0_ENABLE_STOP_CLOCK_SHFT 40
 949 #define UVH_LOCAL_INT0_ENABLE_STOP_CLOCK_MASK 0x0000010000000000UL
 950 #define UVH_LOCAL_INT0_ENABLE_ASIC_TO_L1_SHFT 41
 951 #define UVH_LOCAL_INT0_ENABLE_ASIC_TO_L1_MASK 0x0000020000000000UL
 952 #define UVH_LOCAL_INT0_ENABLE_L1_TO_ASIC_SHFT 42
 953 #define UVH_LOCAL_INT0_ENABLE_L1_TO_ASIC_MASK 0x0000040000000000UL
 954 #define UVH_LOCAL_INT0_ENABLE_LTC_INT_SHFT 43
 955 #define UVH_LOCAL_INT0_ENABLE_LTC_INT_MASK 0x0000080000000000UL
 956 #define UVH_LOCAL_INT0_ENABLE_LA_SEQ_TRIGGER_SHFT 44
 957 #define UVH_LOCAL_INT0_ENABLE_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
 958
 959 union uvh_local_int0_enable_u {
 960     unsigned long       v;
 961     struct uvh_local_int0_enable_s {
 962         unsigned long   lb_hcerr            :  1;  /* RW */
 963         unsigned long   gr0_hcerr           :  1;  /* RW */
 964         unsigned long   gr1_hcerr           :  1;  /* RW */
 965         unsigned long   lh_hcerr            :  1;  /* RW */
 966         unsigned long   rh_hcerr            :  1;  /* RW */
 967         unsigned long   xn_hcerr            :  1;  /* RW */
 968         unsigned long   si_hcerr            :  1;  /* RW */
 969         unsigned long   lb_aoerr0           :  1;  /* RW */
 970         unsigned long   gr0_aoerr0          :  1;  /* RW */
 971         unsigned long   gr1_aoerr0          :  1;  /* RW */
 972         unsigned long   lh_aoerr0           :  1;  /* RW */
 973         unsigned long   rh_aoerr0           :  1;  /* RW */
 974         unsigned long   xn_aoerr0           :  1;  /* RW */
 975         unsigned long   si_aoerr0           :  1;  /* RW */
 976         unsigned long   lb_aoerr1           :  1;  /* RW */
 977         unsigned long   gr0_aoerr1          :  1;  /* RW */
 978         unsigned long   gr1_aoerr1          :  1;  /* RW */
 979         unsigned long   lh_aoerr1           :  1;  /* RW */
 980         unsigned long   rh_aoerr1           :  1;  /* RW */
 981         unsigned long   xn_aoerr1           :  1;  /* RW */
 982         unsigned long   si_aoerr1           :  1;  /* RW */
 983         unsigned long   rh_vpi_int          :  1;  /* RW */
 984         unsigned long   system_shutdown_int :  1;  /* RW */
 985         unsigned long   lb_irq_int_0        :  1;  /* RW */
 986         unsigned long   lb_irq_int_1        :  1;  /* RW */
 987         unsigned long   lb_irq_int_2        :  1;  /* RW */
 988         unsigned long   lb_irq_int_3        :  1;  /* RW */
 989         unsigned long   lb_irq_int_4        :  1;  /* RW */
 990         unsigned long   lb_irq_int_5        :  1;  /* RW */
 991         unsigned long   lb_irq_int_6        :  1;  /* RW */
 992         unsigned long   lb_irq_int_7        :  1;  /* RW */
 993         unsigned long   lb_irq_int_8        :  1;  /* RW */
 994         unsigned long   lb_irq_int_9        :  1;  /* RW */
 995         unsigned long   lb_irq_int_10       :  1;  /* RW */
 996         unsigned long   lb_irq_int_11       :  1;  /* RW */
 997         unsigned long   lb_irq_int_12       :  1;  /* RW */
 998         unsigned long   lb_irq_int_13       :  1;  /* RW */
 999         unsigned long   lb_irq_int_14       :  1;  /* RW */
1000         unsigned long   lb_irq_int_15       :  1;  /* RW */
1001         unsigned long   l1_nmi_int          :  1;  /* RW */
1002         unsigned long   stop_clock          :  1;  /* RW */
1003         unsigned long   asic_to_l1          :  1;  /* RW */
1004         unsigned long   l1_to_asic          :  1;  /* RW */
1005         unsigned long   ltc_int             :  1;  /* RW */
1006         unsigned long   la_seq_trigger      :  1;  /* RW */
1007         unsigned long   rsvd_45_63          : 19;  /*    */
1008     } s;
1009 };
1010
1011 /* ========================================================================= */
1012 /*                               UVH_NODE_ID                                 */
1013 /* ========================================================================= */
1014 #define UVH_NODE_ID 0x0UL
1015
1016 #define UVH_NODE_ID_FORCE1_SHFT 0
1017 #define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
1018 #define UVH_NODE_ID_MANUFACTURER_SHFT 1
1019 #define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
1020 #define UVH_NODE_ID_PART_NUMBER_SHFT 12
1021 #define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
1022 #define UVH_NODE_ID_REVISION_SHFT 28
1023 #define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
1024 #define UVH_NODE_ID_NODE_ID_SHFT 32
1025 #define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
1026 #define UVH_NODE_ID_NODES_PER_BIT_SHFT 48
1027 #define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
1028 #define UVH_NODE_ID_NI_PORT_SHFT 56
1029 #define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
1030
1031 union uvh_node_id_u {
1032     unsigned long       v;
1033     struct uvh_node_id_s {
1034         unsigned long   force1        :  1;  /* RO */
1035         unsigned long   manufacturer  : 11;  /* RO */
1036         unsigned long   part_number   : 16;  /* RO */
1037         unsigned long   revision      :  4;  /* RO */
1038         unsigned long   node_id       : 15;  /* RW */
1039         unsigned long   rsvd_47       :  1;  /*    */
1040         unsigned long   nodes_per_bit :  7;  /* RW */
1041         unsigned long   rsvd_55       :  1;  /*    */
1042         unsigned long   ni_port       :  4;  /* RO */
1043         unsigned long   rsvd_60_63    :  4;  /*    */
1044     } s;
1045 };
1046
1047 /* ========================================================================= */
1048 /*                          UVH_NODE_PRESENT_TABLE                           */
1049 /* ========================================================================= */
1050 #define UVH_NODE_PRESENT_TABLE 0x1400UL
1051 #define UVH_NODE_PRESENT_TABLE_DEPTH 16
1052
1053 #define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0
1054 #define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL
1055
1056 union uvh_node_present_table_u {
1057     unsigned long       v;
1058     struct uvh_node_present_table_s {
1059         unsigned long   nodes : 64;  /* RW */
1060     } s;
1061 };
1062
1063 /* ========================================================================= */
1064 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR                  */
1065 /* ========================================================================= */
1066 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
1067
1068 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
1069 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
1070
1071 union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
1072     unsigned long       v;
1073     struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
1074         unsigned long   rsvd_0_23 : 24;  /*    */
1075         unsigned long   dest_base : 22;  /* RW */
1076         unsigned long   rsvd_46_63: 18;  /*    */
1077     } s;
1078 };
1079
1080 /* ========================================================================= */
1081 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR                  */
1082 /* ========================================================================= */
1083 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
1084
1085 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
1086 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
1087
1088 union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
1089     unsigned long       v;
1090     struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
1091         unsigned long   rsvd_0_23 : 24;  /*    */
1092         unsigned long   dest_base : 22;  /* RW */
1093         unsigned long   rsvd_46_63: 18;  /*    */
1094     } s;
1095 };
1096
1097 /* ========================================================================= */
1098 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR                  */
1099 /* ========================================================================= */
1100 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
1101
1102 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
1103 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
1104
1105 union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
1106     unsigned long       v;
1107     struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
1108         unsigned long   rsvd_0_23 : 24;  /*    */
1109         unsigned long   dest_base : 22;  /* RW */
1110         unsigned long   rsvd_46_63: 18;  /*    */
1111     } s;
1112 };
1113
1114 /* ========================================================================= */
1115 /*                    UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR                      */
1116 /* ========================================================================= */
1117 #define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR 0x1600020UL
1118
1119 #define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT 26
1120 #define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1121 #define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1122 #define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1123
1124 union uvh_rh_gam_cfg_overlay_config_mmr_u {
1125     unsigned long       v;
1126     struct uvh_rh_gam_cfg_overlay_config_mmr_s {
1127         unsigned long   rsvd_0_25: 26;  /*    */
1128         unsigned long   base   : 20;  /* RW */
1129         unsigned long   rsvd_46_62: 17;  /*    */
1130         unsigned long   enable :  1;  /* RW */
1131     } s;
1132 };
1133
1134 /* ========================================================================= */
1135 /*                    UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR                      */
1136 /* ========================================================================= */
1137 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
1138
1139 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
1140 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
1141 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48
1142 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL
1143 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
1144 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
1145 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1146 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1147
1148 union uvh_rh_gam_gru_overlay_config_mmr_u {
1149     unsigned long       v;
1150     struct uvh_rh_gam_gru_overlay_config_mmr_s {
1151         unsigned long   rsvd_0_27: 28;  /*    */
1152         unsigned long   base   : 18;  /* RW */
1153         unsigned long   rsvd_46_47:  2;  /*    */
1154         unsigned long   gr4    :  1;  /* RW */
1155         unsigned long   rsvd_49_51:  3;  /*    */
1156         unsigned long   n_gru  :  4;  /* RW */
1157         unsigned long   rsvd_56_62:  7;  /*    */
1158         unsigned long   enable :  1;  /* RW */
1159     } s;
1160 };
1161
1162 /* ========================================================================= */
1163 /*                   UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR                     */
1164 /* ========================================================================= */
1165 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
1166
1167 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30
1168 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL
1169 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
1170 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
1171 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
1172 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
1173 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1174 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1175
1176 union uvh_rh_gam_mmioh_overlay_config_mmr_u {
1177     unsigned long       v;
1178     struct uvh_rh_gam_mmioh_overlay_config_mmr_s {
1179         unsigned long   rsvd_0_29: 30;  /*    */
1180         unsigned long   base   : 16;  /* RW */
1181         unsigned long   m_io   :  6;  /* RW */
1182         unsigned long   n_io   :  4;  /* RW */
1183         unsigned long   rsvd_56_62:  7;  /*    */
1184         unsigned long   enable :  1;  /* RW */
1185     } s;
1186 };
1187
1188 /* ========================================================================= */
1189 /*                    UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR                      */
1190 /* ========================================================================= */
1191 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
1192
1193 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
1194 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1195 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
1196 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
1197 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1198 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1199
1200 union uvh_rh_gam_mmr_overlay_config_mmr_u {
1201     unsigned long       v;
1202     struct uvh_rh_gam_mmr_overlay_config_mmr_s {
1203         unsigned long   rsvd_0_25: 26;  /*    */
1204         unsigned long   base     : 20;  /* RW */
1205         unsigned long   dual_hub :  1;  /* RW */
1206         unsigned long   rsvd_47_62: 16;  /*    */
1207         unsigned long   enable   :  1;  /* RW */
1208     } s;
1209 };
1210
1211 /* ========================================================================= */
1212 /*                                 UVH_RTC                                   */
1213 /* ========================================================================= */
1214 #define UVH_RTC 0x340000UL
1215
1216 #define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
1217 #define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
1218
1219 union uvh_rtc_u {
1220     unsigned long       v;
1221     struct uvh_rtc_s {
1222         unsigned long   real_time_clock : 56;  /* RW */
1223         unsigned long   rsvd_56_63      :  8;  /*    */
1224     } s;
1225 };
1226
1227 /* ========================================================================= */
1228 /*                           UVH_RTC1_INT_CONFIG                             */
1229 /* ========================================================================= */
1230 #define UVH_RTC1_INT_CONFIG 0x615c0UL
1231
1232 #define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0
1233 #define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1234 #define UVH_RTC1_INT_CONFIG_DM_SHFT 8
1235 #define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
1236 #define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11
1237 #define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1238 #define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12
1239 #define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
1240 #define UVH_RTC1_INT_CONFIG_P_SHFT 13
1241 #define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
1242 #define UVH_RTC1_INT_CONFIG_T_SHFT 15
1243 #define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
1244 #define UVH_RTC1_INT_CONFIG_M_SHFT 16
1245 #define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
1246 #define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32
1247 #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1248
1249 union uvh_rtc1_int_config_u {
1250     unsigned long       v;
1251     struct uvh_rtc1_int_config_s {
1252         unsigned long   vector_  :  8;  /* RW */
1253         unsigned long   dm       :  3;  /* RW */
1254         unsigned long   destmode :  1;  /* RW */
1255         unsigned long   status   :  1;  /* RO */
1256         unsigned long   p        :  1;  /* RO */
1257         unsigned long   rsvd_14  :  1;  /*    */
1258         unsigned long   t        :  1;  /* RO */
1259         unsigned long   m        :  1;  /* RW */
1260         unsigned long   rsvd_17_31: 15;  /*    */
1261         unsigned long   apic_id  : 32;  /* RW */
1262     } s;
1263 };
1264
1265 /* ========================================================================= */
1266 /*                           UVH_RTC2_INT_CONFIG                             */
1267 /* ========================================================================= */
1268 #define UVH_RTC2_INT_CONFIG 0x61600UL
1269
1270 #define UVH_RTC2_INT_CONFIG_VECTOR_SHFT 0
1271 #define UVH_RTC2_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1272 #define UVH_RTC2_INT_CONFIG_DM_SHFT 8
1273 #define UVH_RTC2_INT_CONFIG_DM_MASK 0x0000000000000700UL
1274 #define UVH_RTC2_INT_CONFIG_DESTMODE_SHFT 11
1275 #define UVH_RTC2_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1276 #define UVH_RTC2_INT_CONFIG_STATUS_SHFT 12
1277 #define UVH_RTC2_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
1278 #define UVH_RTC2_INT_CONFIG_P_SHFT 13
1279 #define UVH_RTC2_INT_CONFIG_P_MASK 0x0000000000002000UL
1280 #define UVH_RTC2_INT_CONFIG_T_SHFT 15
1281 #define UVH_RTC2_INT_CONFIG_T_MASK 0x0000000000008000UL
1282 #define UVH_RTC2_INT_CONFIG_M_SHFT 16
1283 #define UVH_RTC2_INT_CONFIG_M_MASK 0x0000000000010000UL
1284 #define UVH_RTC2_INT_CONFIG_APIC_ID_SHFT 32
1285 #define UVH_RTC2_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1286
1287 union uvh_rtc2_int_config_u {
1288     unsigned long       v;
1289     struct uvh_rtc2_int_config_s {
1290         unsigned long   vector_  :  8;  /* RW */
1291         unsigned long   dm       :  3;  /* RW */
1292         unsigned long   destmode :  1;  /* RW */
1293         unsigned long   status   :  1;  /* RO */
1294         unsigned long   p        :  1;  /* RO */
1295         unsigned long   rsvd_14  :  1;  /*    */
1296         unsigned long   t        :  1;  /* RO */
1297         unsigned long   m        :  1;  /* RW */
1298         unsigned long   rsvd_17_31: 15;  /*    */
1299         unsigned long   apic_id  : 32;  /* RW */
1300     } s;
1301 };
1302
1303 /* ========================================================================= */
1304 /*                           UVH_RTC3_INT_CONFIG                             */
1305 /* ========================================================================= */
1306 #define UVH_RTC3_INT_CONFIG 0x61640UL
1307
1308 #define UVH_RTC3_INT_CONFIG_VECTOR_SHFT 0
1309 #define UVH_RTC3_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1310 #define UVH_RTC3_INT_CONFIG_DM_SHFT 8
1311 #define UVH_RTC3_INT_CONFIG_DM_MASK 0x0000000000000700UL
1312 #define UVH_RTC3_INT_CONFIG_DESTMODE_SHFT 11
1313 #define UVH_RTC3_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1314 #define UVH_RTC3_INT_CONFIG_STATUS_SHFT 12
1315 #define UVH_RTC3_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
1316 #define UVH_RTC3_INT_CONFIG_P_SHFT 13
1317 #define UVH_RTC3_INT_CONFIG_P_MASK 0x0000000000002000UL
1318 #define UVH_RTC3_INT_CONFIG_T_SHFT 15
1319 #define UVH_RTC3_INT_CONFIG_T_MASK 0x0000000000008000UL
1320 #define UVH_RTC3_INT_CONFIG_M_SHFT 16
1321 #define UVH_RTC3_INT_CONFIG_M_MASK 0x0000000000010000UL
1322 #define UVH_RTC3_INT_CONFIG_APIC_ID_SHFT 32
1323 #define UVH_RTC3_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1324
1325 union uvh_rtc3_int_config_u {
1326     unsigned long       v;
1327     struct uvh_rtc3_int_config_s {
1328         unsigned long   vector_  :  8;  /* RW */
1329         unsigned long   dm       :  3;  /* RW */
1330         unsigned long   destmode :  1;  /* RW */
1331         unsigned long   status   :  1;  /* RO */
1332         unsigned long   p        :  1;  /* RO */
1333         unsigned long   rsvd_14  :  1;  /*    */
1334         unsigned long   t        :  1;  /* RO */
1335         unsigned long   m        :  1;  /* RW */
1336         unsigned long   rsvd_17_31: 15;  /*    */
1337         unsigned long   apic_id  : 32;  /* RW */
1338     } s;
1339 };
1340
1341 /* ========================================================================= */
1342 /*                            UVH_RTC_INC_RATIO                              */
1343 /* ========================================================================= */
1344 #define UVH_RTC_INC_RATIO 0x350000UL
1345
1346 #define UVH_RTC_INC_RATIO_FRACTION_SHFT 0
1347 #define UVH_RTC_INC_RATIO_FRACTION_MASK 0x00000000000fffffUL
1348 #define UVH_RTC_INC_RATIO_RATIO_SHFT 20
1349 #define UVH_RTC_INC_RATIO_RATIO_MASK 0x0000000000700000UL
1350
1351 union uvh_rtc_inc_ratio_u {
1352     unsigned long       v;
1353     struct uvh_rtc_inc_ratio_s {
1354         unsigned long   fraction : 20;  /* RW */
1355         unsigned long   ratio    :  3;  /* RW */
1356         unsigned long   rsvd_23_63: 41;  /*    */
1357     } s;
1358 };
1359
1360 /* ========================================================================= */
1361 /*                          UVH_SI_ADDR_MAP_CONFIG                           */
1362 /* ========================================================================= */
1363 #define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
1364
1365 #define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0
1366 #define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
1367 #define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8
1368 #define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL
1369
1370 union uvh_si_addr_map_config_u {
1371     unsigned long       v;
1372     struct uvh_si_addr_map_config_s {
1373         unsigned long   m_skt :  6;  /* RW */
1374         unsigned long   rsvd_6_7:  2;  /*    */
1375         unsigned long   n_skt :  4;  /* RW */
1376         unsigned long   rsvd_12_63: 52;  /*    */
1377     } s;
1378 };
1379
1380 /* ========================================================================= */
1381 /*                       UVH_SI_ALIAS0_OVERLAY_CONFIG                        */
1382 /* ========================================================================= */
1383 #define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL
1384
1385 #define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24
1386 #define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
1387 #define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48
1388 #define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
1389 #define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63
1390 #define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
1391
1392 union uvh_si_alias0_overlay_config_u {
1393     unsigned long       v;
1394     struct uvh_si_alias0_overlay_config_s {
1395         unsigned long   rsvd_0_23: 24;  /*    */
1396         unsigned long   base    :  8;  /* RW */
1397         unsigned long   rsvd_32_47: 16;  /*    */
1398         unsigned long   m_alias :  5;  /* RW */
1399         unsigned long   rsvd_53_62: 10;  /*    */
1400         unsigned long   enable  :  1;  /* RW */
1401     } s;
1402 };
1403
1404 /* ========================================================================= */
1405 /*                       UVH_SI_ALIAS1_OVERLAY_CONFIG                        */
1406 /* ========================================================================= */
1407 #define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL
1408
1409 #define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24
1410 #define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
1411 #define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48
1412 #define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
1413 #define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63
1414 #define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
1415
1416 union uvh_si_alias1_overlay_config_u {
1417     unsigned long       v;
1418     struct uvh_si_alias1_overlay_config_s {
1419         unsigned long   rsvd_0_23: 24;  /*    */
1420         unsigned long   base    :  8;  /* RW */
1421         unsigned long   rsvd_32_47: 16;  /*    */
1422         unsigned long   m_alias :  5;  /* RW */
1423         unsigned long   rsvd_53_62: 10;  /*    */
1424         unsigned long   enable  :  1;  /* RW */
1425     } s;
1426 };
1427
1428 /* ========================================================================= */
1429 /*                       UVH_SI_ALIAS2_OVERLAY_CONFIG                        */
1430 /* ========================================================================= */
1431 #define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL
1432
1433 #define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24
1434 #define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
1435 #define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48
1436 #define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
1437 #define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63
1438 #define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
1439
1440 union uvh_si_alias2_overlay_config_u {
1441     unsigned long       v;
1442     struct uvh_si_alias2_overlay_config_s {
1443         unsigned long   rsvd_0_23: 24;  /*    */
1444         unsigned long   base    :  8;  /* RW */
1445         unsigned long   rsvd_32_47: 16;  /*    */
1446         unsigned long   m_alias :  5;  /* RW */
1447         unsigned long   rsvd_53_62: 10;  /*    */
1448         unsigned long   enable  :  1;  /* RW */
1449     } s;
1450 };
1451
1452
1453 #endif /* _ASM_X86_UV_UV_MMRS_H */