2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV architectural definitions
8 * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
11 #ifndef _ASM_X86_UV_UV_HUB_H
12 #define _ASM_X86_UV_UV_HUB_H
15 #include <linux/numa.h>
16 #include <linux/percpu.h>
17 #include <linux/timer.h>
19 #include <asm/types.h>
20 #include <asm/percpu.h>
21 #include <asm/uv/uv_mmrs.h>
22 #include <asm/irq_vectors.h>
23 #include <asm/io_apic.h>
27 * Addressing Terminology
29 * M - The low M bits of a physical address represent the offset
30 * into the blade local memory. RAM memory on a blade is physically
31 * contiguous (although various IO spaces may punch holes in
34 * N - Number of bits in the node portion of a socket physical
37 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
38 * routers always have low bit of 1, C/MBricks have low bit
39 * equal to 0. Most addressing macros that target UV hub chips
40 * right shift the NASID by 1 to exclude the always-zero bit.
41 * NASIDs contain up to 15 bits.
43 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
46 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
47 * of the nasid for socket usage.
50 * NumaLink Global Physical Address Format:
51 * +--------------------------------+---------------------+
52 * |00..000| GNODE | NodeOffset |
53 * +--------------------------------+---------------------+
54 * |<-------53 - M bits --->|<--------M bits ----->
56 * M - number of node offset bits (35 .. 40)
59 * Memory/UV-HUB Processor Socket Address Format:
60 * +----------------+---------------+---------------------+
61 * |00..000000000000| PNODE | NodeOffset |
62 * +----------------+---------------+---------------------+
63 * <--- N bits --->|<--------M bits ----->
65 * M - number of node offset bits (35 .. 40)
66 * N - number of PNODE bits (0 .. 10)
68 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
69 * The actual values are configuration dependent and are set at
70 * boot time. M & N values are set by the hardware/BIOS at boot.
74 * NOTE!!!!!! This is the current format of the APICID. However, code
75 * should assume that this will change in the future. Use functions
76 * in this file for all APICID bit manipulations and conversion.
80 * pppppppppplc0cch Nehalem-EX
81 * ppppppppplcc0cch Westmere-EX
85 * l = socket number on board
88 * s = bits that are in the SOCKET_ID CSR
90 * Note: Processor only supports 12 bits in the APICID register. The ACPI
91 * tables hold all 16 bits. Software needs to be aware of this.
93 * Unless otherwise specified, all references to APICID refer to
94 * the FULL value contained in ACPI tables, not the subset in the
95 * processor APICID register.
100 * Maximum number of bricks in all partitions and in all coherency domains.
101 * This is the total number of bricks accessible in the numalink fabric. It
102 * includes all C & M bricks. Routers are NOT included.
104 * This value is also the value of the maximum number of non-router NASIDs
105 * in the numalink fabric.
107 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
109 #define UV_MAX_NUMALINK_BLADES 16384
112 * Maximum number of C/Mbricks within a software SSI (hardware may support
115 #define UV_MAX_SSI_BLADES 256
118 * The largest possible NASID of a C or M brick (+ 2)
120 #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2)
123 struct timer_list timer;
124 unsigned long offset;
126 unsigned long idle_on;
127 unsigned long idle_off;
129 unsigned char enabled;
133 * The following defines attributes of the HUB chip. These attributes are
134 * frequently referenced and are kept in the per-cpu data areas of each cpu.
135 * They are kept together in a struct to minimize cache misses.
137 struct uv_hub_info_s {
138 unsigned long global_mmr_base;
139 unsigned long gpa_mask;
140 unsigned int gnode_extra;
141 unsigned long gnode_upper;
142 unsigned long lowmem_remap_top;
143 unsigned long lowmem_remap_base;
144 unsigned short pnode;
145 unsigned short pnode_mask;
146 unsigned short coherency_domain_number;
147 unsigned short numa_blade_id;
148 unsigned char blade_processor_id;
151 struct uv_scir_s scir;
152 unsigned char apic_pnode_shift;
155 DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
156 #define uv_hub_info (&__get_cpu_var(__uv_hub_info))
157 #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
161 struct uvh_apicid_s {
162 unsigned long local_apic_mask : 24;
163 unsigned long local_apic_shift : 5;
164 unsigned long unused1 : 3;
165 unsigned long pnode_mask : 24;
166 unsigned long pnode_shift : 5;
167 unsigned long unused2 : 3;
172 * Local & Global MMR space macros.
173 * Note: macros are intended to be used ONLY by inline functions
174 * in this file - not by other kernel code.
175 * n - NASID (full 15-bit global nasid)
176 * g - GNODE (full 15-bit global nasid, right shifted 1)
177 * p - PNODE (local part of nsids, right shifted 1)
179 #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
180 #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra)
181 #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1)
183 #define UV_LOCAL_MMR_BASE 0xf4000000UL
184 #define UV_GLOBAL_MMR32_BASE 0xf8000000UL
185 #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
186 #define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024)
187 #define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024)
189 #define UV_GLOBAL_GRU_MMR_BASE 0x4000000
191 #define UV_GLOBAL_MMR32_PNODE_SHIFT 15
192 #define UV_GLOBAL_MMR64_PNODE_SHIFT 26
194 #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
196 #define UV_GLOBAL_MMR64_PNODE_BITS(p) \
197 (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT)
199 #define UVH_APICID 0x002D0E00L
200 #define UV_APIC_PNODE_SHIFT 6
202 /* Local Bus from cpu's perspective */
203 #define LOCAL_BUS_BASE 0x1c00000
204 #define LOCAL_BUS_SIZE (4 * 1024 * 1024)
207 * System Controller Interface Reg
209 * Note there are NO leds on a UV system. This register is only
210 * used by the system controller to monitor system-wide operation.
211 * There are 64 regs per node. With Nahelem cpus (2 cores per node,
212 * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on
215 * The window is located at top of ACPI MMR space
217 #define SCIR_WINDOW_COUNT 64
218 #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \
222 #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */
223 #define SCIR_CPU_ACTIVITY 0x02 /* not idle */
224 #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */
226 /* Loop through all installed blades */
227 #define for_each_possible_blade(bid) \
228 for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++)
231 * Macros for converting between kernel virtual addresses, socket local physical
232 * addresses, and UV global physical addresses.
233 * Note: use the standard __pa() & __va() macros for converting
234 * between socket virtual and socket physical addresses.
237 /* socket phys RAM --> UV global physical address */
238 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
240 if (paddr < uv_hub_info->lowmem_remap_top)
241 paddr |= uv_hub_info->lowmem_remap_base;
242 return paddr | uv_hub_info->gnode_upper;
246 /* socket virtual --> UV global physical address */
247 static inline unsigned long uv_gpa(void *v)
249 return uv_soc_phys_ram_to_gpa(__pa(v));
252 /* Top two bits indicate the requested address is in MMR space. */
254 uv_gpa_in_mmr_space(unsigned long gpa)
256 return (gpa >> 62) == 0x3UL;
259 /* UV global physical address --> socket phys RAM */
260 static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa)
262 unsigned long paddr = gpa & uv_hub_info->gpa_mask;
263 unsigned long remap_base = uv_hub_info->lowmem_remap_base;
264 unsigned long remap_top = uv_hub_info->lowmem_remap_top;
266 if (paddr >= remap_base && paddr < remap_base + remap_top)
273 static inline unsigned long uv_gpa_to_gnode(unsigned long gpa)
275 return gpa >> uv_hub_info->m_val;
279 static inline int uv_gpa_to_pnode(unsigned long gpa)
281 unsigned long n_mask = (1UL << uv_hub_info->n_val) - 1;
283 return uv_gpa_to_gnode(gpa) & n_mask;
286 /* pnode, offset --> socket virtual */
287 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
289 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
294 * Extract a PNODE from an APICID (full apicid, not processor subset)
296 static inline int uv_apicid_to_pnode(int apicid)
298 return (apicid >> uv_hub_info->apic_pnode_shift);
302 * Access global MMRs using the low memory MMR32 space. This region supports
303 * faster MMR access but not all MMRs are accessible in this space.
305 static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset)
307 return __va(UV_GLOBAL_MMR32_BASE |
308 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
311 static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val)
313 writeq(val, uv_global_mmr32_address(pnode, offset));
316 static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset)
318 return readq(uv_global_mmr32_address(pnode, offset));
322 * Access Global MMR space using the MMR space located at the top of physical
325 static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset)
327 return __va(UV_GLOBAL_MMR64_BASE |
328 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
331 static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val)
333 writeq(val, uv_global_mmr64_address(pnode, offset));
336 static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset)
338 return readq(uv_global_mmr64_address(pnode, offset));
342 * Global MMR space addresses when referenced by the GRU. (GRU does
343 * NOT use socket addressing).
345 static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset)
347 return UV_GLOBAL_GRU_MMR_BASE | offset |
348 ((unsigned long)pnode << uv_hub_info->m_val);
351 static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val)
353 writeb(val, uv_global_mmr64_address(pnode, offset));
356 static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset)
358 return readb(uv_global_mmr64_address(pnode, offset));
362 * Access hub local MMRs. Faster than using global space but only local MMRs
365 static inline unsigned long *uv_local_mmr_address(unsigned long offset)
367 return __va(UV_LOCAL_MMR_BASE | offset);
370 static inline unsigned long uv_read_local_mmr(unsigned long offset)
372 return readq(uv_local_mmr_address(offset));
375 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
377 writeq(val, uv_local_mmr_address(offset));
380 static inline unsigned char uv_read_local_mmr8(unsigned long offset)
382 return readb(uv_local_mmr_address(offset));
385 static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
387 writeb(val, uv_local_mmr_address(offset));
391 * Structures and definitions for converting between cpu, node, pnode, and blade
394 struct uv_blade_info {
395 unsigned short nr_possible_cpus;
396 unsigned short nr_online_cpus;
397 unsigned short pnode;
400 extern struct uv_blade_info *uv_blade_info;
401 extern short *uv_node_to_blade;
402 extern short *uv_cpu_to_blade;
403 extern short uv_possible_blades;
405 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
406 static inline int uv_blade_processor_id(void)
408 return uv_hub_info->blade_processor_id;
411 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
412 static inline int uv_numa_blade_id(void)
414 return uv_hub_info->numa_blade_id;
417 /* Convert a cpu number to the the UV blade number */
418 static inline int uv_cpu_to_blade_id(int cpu)
420 return uv_cpu_to_blade[cpu];
423 /* Convert linux node number to the UV blade number */
424 static inline int uv_node_to_blade_id(int nid)
426 return uv_node_to_blade[nid];
429 /* Convert a blade id to the PNODE of the blade */
430 static inline int uv_blade_to_pnode(int bid)
432 return uv_blade_info[bid].pnode;
435 /* Nid of memory node on blade. -1 if no blade-local memory */
436 static inline int uv_blade_to_memory_nid(int bid)
438 return uv_blade_info[bid].memory_nid;
441 /* Determine the number of possible cpus on a blade */
442 static inline int uv_blade_nr_possible_cpus(int bid)
444 return uv_blade_info[bid].nr_possible_cpus;
447 /* Determine the number of online cpus on a blade */
448 static inline int uv_blade_nr_online_cpus(int bid)
450 return uv_blade_info[bid].nr_online_cpus;
453 /* Convert a cpu id to the PNODE of the blade containing the cpu */
454 static inline int uv_cpu_to_pnode(int cpu)
456 return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
459 /* Convert a linux node number to the PNODE of the blade */
460 static inline int uv_node_to_pnode(int nid)
462 return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
465 /* Maximum possible number of blades */
466 static inline int uv_num_possible_blades(void)
468 return uv_possible_blades;
471 /* Update SCIR state */
472 static inline void uv_set_scir_bits(unsigned char value)
474 if (uv_hub_info->scir.state != value) {
475 uv_hub_info->scir.state = value;
476 uv_write_local_mmr8(uv_hub_info->scir.offset, value);
480 static inline unsigned long uv_scir_offset(int apicid)
482 return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f);
485 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
487 if (uv_cpu_hub_info(cpu)->scir.state != value) {
488 uv_write_global_mmr8(uv_cpu_to_pnode(cpu),
489 uv_cpu_hub_info(cpu)->scir.offset, value);
490 uv_cpu_hub_info(cpu)->scir.state = value;
494 static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode)
496 return (1UL << UVH_IPI_INT_SEND_SHFT) |
497 ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) |
498 (mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
499 (vector << UVH_IPI_INT_VECTOR_SHFT);
502 static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
505 unsigned long dmode = dest_Fixed;
507 if (vector == NMI_VECTOR)
510 val = uv_hub_ipi_value(apicid, vector, dmode);
511 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
515 * Get the minimum revision number of the hub chips within the partition.
516 * 1 - initial rev 1.0 silicon
517 * 2 - rev 2.0 production silicon
519 static inline int uv_get_min_hub_revision_id(void)
521 extern int uv_min_hub_revision_id;
523 return uv_min_hub_revision_id;
526 #endif /* CONFIG_X86_64 */
527 #endif /* _ASM_X86_UV_UV_HUB_H */