2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 * x86-64 work by Andi Kleen 2002
10 #ifndef _ASM_X86_I387_H
11 #define _ASM_X86_I387_H
15 #include <linux/sched.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/regset.h>
18 #include <linux/hardirq.h>
19 #include <linux/slab.h>
21 #include <asm/cpufeature.h>
22 #include <asm/processor.h>
23 #include <asm/sigcontext.h>
25 #include <asm/uaccess.h>
26 #include <asm/xsave.h>
28 extern unsigned int sig_xstate_size;
29 extern void fpu_init(void);
30 extern void mxcsr_feature_mask_init(void);
31 extern int init_fpu(struct task_struct *child);
32 extern asmlinkage void math_state_restore(void);
33 extern void __math_state_restore(void);
34 extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
36 extern user_regset_active_fn fpregs_active, xfpregs_active;
37 extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
39 extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
43 * xstateregs_active == fpregs_active. Please refer to the comment
44 * at the definition of fpregs_active.
46 #define xstateregs_active fpregs_active
48 extern struct _fpx_sw_bytes fx_sw_reserved;
49 #ifdef CONFIG_IA32_EMULATION
50 extern unsigned int sig_xstate_ia32_size;
51 extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
54 extern int save_i387_xstate_ia32(void __user *buf);
55 extern int restore_i387_xstate_ia32(void __user *buf);
58 #define X87_FSW_ES (1 << 7) /* Exception Summary */
60 static __always_inline __pure bool use_xsaveopt(void)
62 return static_cpu_has(X86_FEATURE_XSAVEOPT);
65 static __always_inline __pure bool use_xsave(void)
67 return static_cpu_has(X86_FEATURE_XSAVE);
70 extern void __sanitize_i387_state(struct task_struct *);
72 static inline void sanitize_i387_state(struct task_struct *tsk)
76 __sanitize_i387_state(tsk);
80 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
84 asm volatile("1: rex64/fxrstor (%[fx])\n\t"
86 ".section .fixup,\"ax\"\n"
87 "3: movl $-1,%[err]\n"
92 #if 0 /* See comment in fxsave() below. */
93 : [fx] "r" (fx), "m" (*fx), "0" (0));
95 : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
100 /* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
101 is pending. Clear the x87 state here by setting it to fixed
102 values. The kernel data segment can be sometimes 0 and sometimes
103 new user value. Both should be ok.
104 Use the PDA as safe address because it should be already in L1. */
105 static inline void fpu_clear(struct fpu *fpu)
107 struct xsave_struct *xstate = &fpu->state->xsave;
108 struct i387_fxsave_struct *fx = &fpu->state->fxsave;
111 * xsave header may indicate the init state of the FP.
114 !(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
117 if (unlikely(fx->swd & X87_FSW_ES))
118 asm volatile("fnclex");
119 alternative_input(ASM_NOP8 ASM_NOP2,
120 " emms\n" /* clear stack tags */
121 " fildl %%gs:0", /* load to clear state */
122 X86_FEATURE_FXSAVE_LEAK);
125 static inline void clear_fpu_state(struct task_struct *tsk)
127 fpu_clear(&tsk->thread.fpu);
130 static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
135 * Clear the bytes not touched by the fxsave and reserved
138 err = __clear_user(&fx->sw_reserved,
139 sizeof(struct _fpx_sw_bytes));
143 asm volatile("1: rex64/fxsave (%[fx])\n\t"
145 ".section .fixup,\"ax\"\n"
146 "3: movl $-1,%[err]\n"
150 : [err] "=r" (err), "=m" (*fx)
151 #if 0 /* See comment in fxsave() below. */
152 : [fx] "r" (fx), "0" (0));
154 : [fx] "cdaSDb" (fx), "0" (0));
157 __clear_user(fx, sizeof(struct i387_fxsave_struct)))
159 /* No need to clear here because the caller clears USED_MATH */
163 static inline void fpu_fxsave(struct fpu *fpu)
165 /* Using "rex64; fxsave %0" is broken because, if the memory operand
166 uses any extended registers for addressing, a second REX prefix
167 will be generated (to the assembler, rex64 followed by semicolon
168 is a separate instruction), and hence the 64-bitness is lost. */
170 /* Using "fxsaveq %0" would be the ideal choice, but is only supported
171 starting with gas 2.16. */
172 __asm__ __volatile__("fxsaveq %0"
173 : "=m" (fpu->state->fxsave));
175 /* Using, as a workaround, the properly prefixed form below isn't
176 accepted by any binutils version so far released, complaining that
177 the same type of prefix is used twice if an extended register is
178 needed for addressing (fix submitted to mainline 2005-11-21). */
179 __asm__ __volatile__("rex64/fxsave %0"
180 : "=m" (fpu->state->fxsave));
182 /* This, however, we can work around by forcing the compiler to select
183 an addressing mode that doesn't require extended registers. */
184 __asm__ __volatile__("rex64/fxsave (%1)"
185 : "=m" (fpu->state->fxsave)
186 : "cdaSDb" (&fpu->state->fxsave));
190 static inline void fpu_save_init(struct fpu *fpu)
200 #else /* CONFIG_X86_32 */
202 #ifdef CONFIG_MATH_EMULATION
203 extern void finit_soft_fpu(struct i387_soft_struct *soft);
205 static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
208 /* perform fxrstor iff the processor has extended states, otherwise frstor */
209 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
212 * The "nop" is needed to make the instructions the same
224 /* We need a safe address that is cheap to find and that is already
225 in L1 during context switch. The best choices are unfortunately
226 different for UP and SMP */
228 #define safe_address (__per_cpu_offset[0])
230 #define safe_address (kstat_cpu(0).cpustat.user)
234 * These must be called with preempt disabled
236 static inline void fpu_save_init(struct fpu *fpu)
239 struct xsave_struct *xstate = &fpu->state->xsave;
240 struct i387_fxsave_struct *fx = &fpu->state->fxsave;
245 * xsave header may indicate the init state of the FP.
247 if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
250 if (unlikely(fx->swd & X87_FSW_ES))
251 asm volatile("fnclex");
254 * we can do a simple return here or be paranoid :)
259 /* Use more nops than strictly needed in case the compiler
262 "fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
264 "bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
266 [fx] "m" (fpu->state->fxsave),
267 [fsw] "m" (fpu->state->fxsave.swd) : "memory");
269 /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
270 is pending. Clear the x87 state here by setting it to fixed
271 values. safe_address is a random variable that should be in L1 */
273 GENERIC_NOP8 GENERIC_NOP2,
274 "emms\n\t" /* clear stack tags */
275 "fildl %[addr]", /* set F?P to defined value */
276 X86_FEATURE_FXSAVE_LEAK,
277 [addr] "m" (safe_address));
282 #endif /* CONFIG_X86_64 */
284 static inline void __save_init_fpu(struct task_struct *tsk)
286 fpu_save_init(&tsk->thread.fpu);
287 task_thread_info(tsk)->status &= ~TS_USEDFPU;
290 static inline int fpu_fxrstor_checking(struct fpu *fpu)
292 return fxrstor_checking(&fpu->state->fxsave);
295 static inline int fpu_restore_checking(struct fpu *fpu)
298 return fpu_xrstor_checking(fpu);
300 return fpu_fxrstor_checking(fpu);
303 static inline int restore_fpu_checking(struct task_struct *tsk)
305 return fpu_restore_checking(&tsk->thread.fpu);
309 * Signal frame handlers...
311 extern int save_i387_xstate(void __user *buf);
312 extern int restore_i387_xstate(void __user *buf);
314 static inline void __unlazy_fpu(struct task_struct *tsk)
316 if (task_thread_info(tsk)->status & TS_USEDFPU) {
317 __save_init_fpu(tsk);
320 tsk->fpu_counter = 0;
323 static inline void __clear_fpu(struct task_struct *tsk)
325 if (task_thread_info(tsk)->status & TS_USEDFPU) {
326 /* Ignore delayed exceptions from user space */
327 asm volatile("1: fwait\n"
329 _ASM_EXTABLE(1b, 2b));
330 task_thread_info(tsk)->status &= ~TS_USEDFPU;
335 static inline void kernel_fpu_begin(void)
337 struct thread_info *me = current_thread_info();
339 if (me->status & TS_USEDFPU)
340 __save_init_fpu(me->task);
345 static inline void kernel_fpu_end(void)
351 static inline bool irq_fpu_usable(void)
353 struct pt_regs *regs;
355 return !in_interrupt() || !(regs = get_irq_regs()) || \
356 user_mode(regs) || (read_cr0() & X86_CR0_TS);
360 * Some instructions like VIA's padlock instructions generate a spurious
361 * DNA fault but don't modify SSE registers. And these instructions
362 * get used from interrupt context as well. To prevent these kernel instructions
363 * in interrupt context interacting wrongly with other user/kernel fpu usage, we
364 * should use them only in the context of irq_ts_save/restore()
366 static inline int irq_ts_save(void)
369 * If in process context and not atomic, we can take a spurious DNA fault.
370 * Otherwise, doing clts() in process context requires disabling preemption
371 * or some heavy lifting like kernel_fpu_begin()
376 if (read_cr0() & X86_CR0_TS) {
384 static inline void irq_ts_restore(int TS_state)
391 * These disable preemption on their own and are safe
393 static inline void save_init_fpu(struct task_struct *tsk)
396 __save_init_fpu(tsk);
401 static inline void unlazy_fpu(struct task_struct *tsk)
408 static inline void clear_fpu(struct task_struct *tsk)
416 * i387 state interaction
418 static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
421 return tsk->thread.fpu.state->fxsave.cwd;
423 return (unsigned short)tsk->thread.fpu.state->fsave.cwd;
427 static inline unsigned short get_fpu_swd(struct task_struct *tsk)
430 return tsk->thread.fpu.state->fxsave.swd;
432 return (unsigned short)tsk->thread.fpu.state->fsave.swd;
436 static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
439 return tsk->thread.fpu.state->fxsave.mxcsr;
441 return MXCSR_DEFAULT;
445 static bool fpu_allocated(struct fpu *fpu)
447 return fpu->state != NULL;
450 static inline int fpu_alloc(struct fpu *fpu)
452 if (fpu_allocated(fpu))
454 fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
457 WARN_ON((unsigned long)fpu->state & 15);
461 static inline void fpu_free(struct fpu *fpu)
464 kmem_cache_free(task_xstate_cachep, fpu->state);
469 static inline void fpu_copy(struct fpu *dst, struct fpu *src)
471 memcpy(dst->state, src->state, xstate_size);
474 extern void fpu_finit(struct fpu *fpu);
476 #endif /* __ASSEMBLY__ */
478 #define PSHUFB_XMM5_XMM0 .byte 0x66, 0x0f, 0x38, 0x00, 0xc5
479 #define PSHUFB_XMM5_XMM6 .byte 0x66, 0x0f, 0x38, 0x00, 0xf5
481 #endif /* _ASM_X86_I387_H */