2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 * x86-64 work by Andi Kleen 2002
10 #ifndef _ASM_X86_I387_H
11 #define _ASM_X86_I387_H
15 #include <linux/sched.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/regset.h>
18 #include <linux/hardirq.h>
20 #include <asm/processor.h>
21 #include <asm/sigcontext.h>
23 #include <asm/uaccess.h>
24 #include <asm/xsave.h>
26 extern unsigned int sig_xstate_size;
27 extern void fpu_init(void);
28 extern void mxcsr_feature_mask_init(void);
29 extern int init_fpu(struct task_struct *child);
30 extern asmlinkage void math_state_restore(void);
31 extern void __math_state_restore(void);
32 extern void init_thread_xstate(void);
33 extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
35 extern user_regset_active_fn fpregs_active, xfpregs_active;
36 extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
38 extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
42 * xstateregs_active == fpregs_active. Please refer to the comment
43 * at the definition of fpregs_active.
45 #define xstateregs_active fpregs_active
47 extern struct _fpx_sw_bytes fx_sw_reserved;
48 #ifdef CONFIG_IA32_EMULATION
49 extern unsigned int sig_xstate_ia32_size;
50 extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
53 extern int save_i387_xstate_ia32(void __user *buf);
54 extern int restore_i387_xstate_ia32(void __user *buf);
57 #define X87_FSW_ES (1 << 7) /* Exception Summary */
61 /* Ignore delayed exceptions from user space */
62 static inline void tolerant_fwait(void)
64 asm volatile("1: fwait\n"
66 _ASM_EXTABLE(1b, 2b));
69 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
73 asm volatile("1: rex64/fxrstor (%[fx])\n\t"
75 ".section .fixup,\"ax\"\n"
76 "3: movl $-1,%[err]\n"
81 #if 0 /* See comment in fxsave() below. */
82 : [fx] "r" (fx), "m" (*fx), "0" (0));
84 : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
89 /* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
90 is pending. Clear the x87 state here by setting it to fixed
91 values. The kernel data segment can be sometimes 0 and sometimes
92 new user value. Both should be ok.
93 Use the PDA as safe address because it should be already in L1. */
94 static inline void clear_fpu_state(struct task_struct *tsk)
96 struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
97 struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
100 * xsave header may indicate the init state of the FP.
102 if ((task_thread_info(tsk)->status & TS_XSAVE) &&
103 !(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
106 if (unlikely(fx->swd & X87_FSW_ES))
107 asm volatile("fnclex");
108 alternative_input(ASM_NOP8 ASM_NOP2,
109 " emms\n" /* clear stack tags */
110 " fildl %%gs:0", /* load to clear state */
111 X86_FEATURE_FXSAVE_LEAK);
114 static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
118 asm volatile("1: rex64/fxsave (%[fx])\n\t"
120 ".section .fixup,\"ax\"\n"
121 "3: movl $-1,%[err]\n"
125 : [err] "=r" (err), "=m" (*fx)
126 #if 0 /* See comment in fxsave() below. */
127 : [fx] "r" (fx), "0" (0));
129 : [fx] "cdaSDb" (fx), "0" (0));
132 __clear_user(fx, sizeof(struct i387_fxsave_struct)))
134 /* No need to clear here because the caller clears USED_MATH */
138 static inline void fxsave(struct task_struct *tsk)
140 /* Using "rex64; fxsave %0" is broken because, if the memory operand
141 uses any extended registers for addressing, a second REX prefix
142 will be generated (to the assembler, rex64 followed by semicolon
143 is a separate instruction), and hence the 64-bitness is lost. */
145 /* Using "fxsaveq %0" would be the ideal choice, but is only supported
146 starting with gas 2.16. */
147 __asm__ __volatile__("fxsaveq %0"
148 : "=m" (tsk->thread.xstate->fxsave));
150 /* Using, as a workaround, the properly prefixed form below isn't
151 accepted by any binutils version so far released, complaining that
152 the same type of prefix is used twice if an extended register is
153 needed for addressing (fix submitted to mainline 2005-11-21). */
154 __asm__ __volatile__("rex64/fxsave %0"
155 : "=m" (tsk->thread.xstate->fxsave));
157 /* This, however, we can work around by forcing the compiler to select
158 an addressing mode that doesn't require extended registers. */
159 __asm__ __volatile__("rex64/fxsave (%1)"
160 : "=m" (tsk->thread.xstate->fxsave)
161 : "cdaSDb" (&tsk->thread.xstate->fxsave));
165 static inline void __save_init_fpu(struct task_struct *tsk)
167 if (task_thread_info(tsk)->status & TS_XSAVE)
172 clear_fpu_state(tsk);
173 task_thread_info(tsk)->status &= ~TS_USEDFPU;
176 #else /* CONFIG_X86_32 */
178 #ifdef CONFIG_MATH_EMULATION
179 extern void finit_task(struct task_struct *tsk);
181 static inline void finit_task(struct task_struct *tsk)
186 static inline void tolerant_fwait(void)
188 asm volatile("fnclex ; fwait");
191 /* perform fxrstor iff the processor has extended states, otherwise frstor */
192 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
195 * The "nop" is needed to make the instructions the same
207 /* We need a safe address that is cheap to find and that is already
208 in L1 during context switch. The best choices are unfortunately
209 different for UP and SMP */
211 #define safe_address (__per_cpu_offset[0])
213 #define safe_address (kstat_cpu(0).cpustat.user)
217 * These must be called with preempt disabled
219 static inline void __save_init_fpu(struct task_struct *tsk)
221 if (task_thread_info(tsk)->status & TS_XSAVE) {
222 struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
223 struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
228 * xsave header may indicate the init state of the FP.
230 if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
233 if (unlikely(fx->swd & X87_FSW_ES))
234 asm volatile("fnclex");
237 * we can do a simple return here or be paranoid :)
242 /* Use more nops than strictly needed in case the compiler
245 "fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
247 "bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
249 [fx] "m" (tsk->thread.xstate->fxsave),
250 [fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
252 /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
253 is pending. Clear the x87 state here by setting it to fixed
254 values. safe_address is a random variable that should be in L1 */
256 GENERIC_NOP8 GENERIC_NOP2,
257 "emms\n\t" /* clear stack tags */
258 "fildl %[addr]", /* set F?P to defined value */
259 X86_FEATURE_FXSAVE_LEAK,
260 [addr] "m" (safe_address));
262 task_thread_info(tsk)->status &= ~TS_USEDFPU;
265 #endif /* CONFIG_X86_64 */
267 static inline int restore_fpu_checking(struct task_struct *tsk)
269 if (task_thread_info(tsk)->status & TS_XSAVE)
270 return xrstor_checking(&tsk->thread.xstate->xsave);
272 return fxrstor_checking(&tsk->thread.xstate->fxsave);
276 * Signal frame handlers...
278 extern int save_i387_xstate(void __user *buf);
279 extern int restore_i387_xstate(void __user *buf);
281 static inline void __unlazy_fpu(struct task_struct *tsk)
283 if (task_thread_info(tsk)->status & TS_USEDFPU) {
284 __save_init_fpu(tsk);
287 tsk->fpu_counter = 0;
290 static inline void __clear_fpu(struct task_struct *tsk)
292 if (task_thread_info(tsk)->status & TS_USEDFPU) {
294 task_thread_info(tsk)->status &= ~TS_USEDFPU;
299 static inline void kernel_fpu_begin(void)
301 struct thread_info *me = current_thread_info();
303 if (me->status & TS_USEDFPU)
304 __save_init_fpu(me->task);
309 static inline void kernel_fpu_end(void)
315 static inline bool irq_fpu_usable(void)
317 struct pt_regs *regs;
319 return !in_interrupt() || !(regs = get_irq_regs()) || \
320 user_mode(regs) || (read_cr0() & X86_CR0_TS);
324 * Some instructions like VIA's padlock instructions generate a spurious
325 * DNA fault but don't modify SSE registers. And these instructions
326 * get used from interrupt context as well. To prevent these kernel instructions
327 * in interrupt context interacting wrongly with other user/kernel fpu usage, we
328 * should use them only in the context of irq_ts_save/restore()
330 static inline int irq_ts_save(void)
333 * If in process context and not atomic, we can take a spurious DNA fault.
334 * Otherwise, doing clts() in process context requires disabling preemption
335 * or some heavy lifting like kernel_fpu_begin()
340 if (read_cr0() & X86_CR0_TS) {
348 static inline void irq_ts_restore(int TS_state)
356 static inline void save_init_fpu(struct task_struct *tsk)
358 __save_init_fpu(tsk);
362 #define unlazy_fpu __unlazy_fpu
363 #define clear_fpu __clear_fpu
365 #else /* CONFIG_X86_32 */
368 * These disable preemption on their own and are safe
370 static inline void save_init_fpu(struct task_struct *tsk)
373 __save_init_fpu(tsk);
378 static inline void unlazy_fpu(struct task_struct *tsk)
385 static inline void clear_fpu(struct task_struct *tsk)
392 #endif /* CONFIG_X86_64 */
395 * i387 state interaction
397 static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
400 return tsk->thread.xstate->fxsave.cwd;
402 return (unsigned short)tsk->thread.xstate->fsave.cwd;
406 static inline unsigned short get_fpu_swd(struct task_struct *tsk)
409 return tsk->thread.xstate->fxsave.swd;
411 return (unsigned short)tsk->thread.xstate->fsave.swd;
415 static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
418 return tsk->thread.xstate->fxsave.mxcsr;
420 return MXCSR_DEFAULT;
424 #endif /* __ASSEMBLY__ */
426 #define PSHUFB_XMM5_XMM0 .byte 0x66, 0x0f, 0x38, 0x00, 0xc5
427 #define PSHUFB_XMM5_XMM6 .byte 0x66, 0x0f, 0x38, 0x00, 0xf5
429 #endif /* _ASM_X86_I387_H */