1 #ifndef _ASM_X86_KVM_HYPERV_H
2 #define _ASM_X86_KVM_HYPERV_H
4 #include <linux/types.h>
7 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
8 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
10 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000
11 #define HYPERV_CPUID_INTERFACE 0x40000001
12 #define HYPERV_CPUID_VERSION 0x40000002
13 #define HYPERV_CPUID_FEATURES 0x40000003
14 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004
15 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005
17 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000
18 #define HYPERV_CPUID_MIN 0x40000005
21 * Feature identification. EAX indicates which features are available
22 * to the partition based upon the current partition privileges.
25 /* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
26 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE (1 << 0)
27 /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
28 #define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE (1 << 1)
30 * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
31 * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
33 #define HV_X64_MSR_SYNIC_AVAILABLE (1 << 2)
35 * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
36 * HV_X64_MSR_STIMER3_COUNT) available
38 #define HV_X64_MSR_SYNTIMER_AVAILABLE (1 << 3)
40 * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
43 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE (1 << 4)
44 /* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
45 #define HV_X64_MSR_HYPERCALL_AVAILABLE (1 << 5)
46 /* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
47 #define HV_X64_MSR_VP_INDEX_AVAILABLE (1 << 6)
48 /* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
49 #define HV_X64_MSR_RESET_AVAILABLE (1 << 7)
51 * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
52 * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
53 * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
55 #define HV_X64_MSR_STAT_PAGES_AVAILABLE (1 << 8)
58 * Feature identification: EBX indicates which flags were specified at
59 * partition creation. The format is the same as the partition creation
60 * flag structure defined in section Partition Creation Flags.
62 #define HV_X64_CREATE_PARTITIONS (1 << 0)
63 #define HV_X64_ACCESS_PARTITION_ID (1 << 1)
64 #define HV_X64_ACCESS_MEMORY_POOL (1 << 2)
65 #define HV_X64_ADJUST_MESSAGE_BUFFERS (1 << 3)
66 #define HV_X64_POST_MESSAGES (1 << 4)
67 #define HV_X64_SIGNAL_EVENTS (1 << 5)
68 #define HV_X64_CREATE_PORT (1 << 6)
69 #define HV_X64_CONNECT_PORT (1 << 7)
70 #define HV_X64_ACCESS_STATS (1 << 8)
71 #define HV_X64_DEBUGGING (1 << 11)
72 #define HV_X64_CPU_POWER_MANAGEMENT (1 << 12)
73 #define HV_X64_CONFIGURE_PROFILER (1 << 13)
76 * Feature identification. EDX indicates which miscellaneous features
77 * are available to the partition.
79 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */
80 #define HV_X64_MWAIT_AVAILABLE (1 << 0)
81 /* Guest debugging support is available */
82 #define HV_X64_GUEST_DEBUGGING_AVAILABLE (1 << 1)
83 /* Performance Monitor support is available*/
84 #define HV_X64_PERF_MONITOR_AVAILABLE (1 << 2)
85 /* Support for physical CPU dynamic partitioning events is available*/
86 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1 << 3)
88 * Support for passing hypercall input parameter block via XMM
89 * registers is available
91 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE (1 << 4)
92 /* Support for a virtual guest idle state is available */
93 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE (1 << 5)
96 * Implementation recommendations. Indicates which behaviors the hypervisor
97 * recommends the OS implement for optimal performance.
100 * Recommend using hypercall for address space switches rather
101 * than MOV to CR3 instruction
103 #define HV_X64_MWAIT_RECOMMENDED (1 << 0)
104 /* Recommend using hypercall for local TLB flushes rather
105 * than INVLPG or MOV to CR3 instructions */
106 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED (1 << 1)
108 * Recommend using hypercall for remote TLB flushes rather
109 * than inter-processor interrupts
111 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED (1 << 2)
113 * Recommend using MSRs for accessing APIC registers
114 * EOI, ICR and TPR rather than their memory-mapped counterparts
116 #define HV_X64_APIC_ACCESS_RECOMMENDED (1 << 3)
117 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */
118 #define HV_X64_SYSTEM_RESET_RECOMMENDED (1 << 4)
120 * Recommend using relaxed timing for this partition. If used,
121 * the VM should disable any watchdog timeouts that rely on the
122 * timely delivery of external interrupts
124 #define HV_X64_RELAXED_TIMING_RECOMMENDED (1 << 5)
126 /* MSR used to identify the guest OS. */
127 #define HV_X64_MSR_GUEST_OS_ID 0x40000000
129 /* MSR used to setup pages used to communicate with the hypervisor. */
130 #define HV_X64_MSR_HYPERCALL 0x40000001
132 /* MSR used to provide vcpu index */
133 #define HV_X64_MSR_VP_INDEX 0x40000002
135 /* MSR used to read the per-partition time reference counter */
136 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020
138 /* Define the virtual APIC registers */
139 #define HV_X64_MSR_EOI 0x40000070
140 #define HV_X64_MSR_ICR 0x40000071
141 #define HV_X64_MSR_TPR 0x40000072
142 #define HV_X64_MSR_APIC_ASSIST_PAGE 0x40000073
144 /* Define synthetic interrupt controller model specific registers. */
145 #define HV_X64_MSR_SCONTROL 0x40000080
146 #define HV_X64_MSR_SVERSION 0x40000081
147 #define HV_X64_MSR_SIEFP 0x40000082
148 #define HV_X64_MSR_SIMP 0x40000083
149 #define HV_X64_MSR_EOM 0x40000084
150 #define HV_X64_MSR_SINT0 0x40000090
151 #define HV_X64_MSR_SINT1 0x40000091
152 #define HV_X64_MSR_SINT2 0x40000092
153 #define HV_X64_MSR_SINT3 0x40000093
154 #define HV_X64_MSR_SINT4 0x40000094
155 #define HV_X64_MSR_SINT5 0x40000095
156 #define HV_X64_MSR_SINT6 0x40000096
157 #define HV_X64_MSR_SINT7 0x40000097
158 #define HV_X64_MSR_SINT8 0x40000098
159 #define HV_X64_MSR_SINT9 0x40000099
160 #define HV_X64_MSR_SINT10 0x4000009A
161 #define HV_X64_MSR_SINT11 0x4000009B
162 #define HV_X64_MSR_SINT12 0x4000009C
163 #define HV_X64_MSR_SINT13 0x4000009D
164 #define HV_X64_MSR_SINT14 0x4000009E
165 #define HV_X64_MSR_SINT15 0x4000009F
168 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001
169 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
170 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \
171 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
173 /* Declare the various hypercall operations. */
174 #define HV_X64_HV_NOTIFY_LONG_SPIN_WAIT 0x0008
176 #define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE 0x00000001
177 #define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT 12
178 #define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK \
179 (~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
181 #define HV_PROCESSOR_POWER_STATE_C0 0
182 #define HV_PROCESSOR_POWER_STATE_C1 1
183 #define HV_PROCESSOR_POWER_STATE_C2 2
184 #define HV_PROCESSOR_POWER_STATE_C3 3
186 /* hypercall status code */
187 #define HV_STATUS_SUCCESS 0
188 #define HV_STATUS_INVALID_HYPERCALL_CODE 2
189 #define HV_STATUS_INVALID_HYPERCALL_INPUT 3
190 #define HV_STATUS_INVALID_ALIGNMENT 4