arch/sparc64/kernel/smp.c

   1 /* smp.c: Sparc64 SMP support.
   2  *
   3  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/kernel.h>
   8 #include <linux/sched.h>
   9 #include <linux/mm.h>
  10 #include <linux/pagemap.h>
  11 #include <linux/threads.h>
  12 #include <linux/smp.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/delay.h>
  16 #include <linux/init.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/fs.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/cache.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/profile.h>
  23 #include <linux/bootmem.h>
  24
  25 #include <asm/head.h>
  26 #include <asm/ptrace.h>
  27 #include <asm/atomic.h>
  28 #include <asm/tlbflush.h>
  29 #include <asm/mmu_context.h>
  30 #include <asm/cpudata.h>
  31
  32 #include <asm/irq.h>
  33 #include <asm/irq_regs.h>
  34 #include <asm/page.h>
  35 #include <asm/pgtable.h>
  36 #include <asm/oplib.h>
  37 #include <asm/uaccess.h>
  38 #include <asm/timer.h>
  39 #include <asm/starfire.h>
  40 #include <asm/tlb.h>
  41 #include <asm/sections.h>
  42 #include <asm/prom.h>
  43 #include <asm/mdesc.h>
  44 #include <asm/ldc.h>
  45
  46 extern void calibrate_delay(void);
  47
  48 int sparc64_multi_core __read_mostly;
  49
  50 /* Please don't make this stuff initdata!!!  --DaveM */
  51 unsigned char boot_cpu_id;
  52
  53 cpumask_t cpu_possible_map __read_mostly = CPU_MASK_NONE;
  54 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
  55 cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly =
  56         { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
  57 cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
  58         { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
  59
  60 EXPORT_SYMBOL(cpu_possible_map);
  61 EXPORT_SYMBOL(cpu_online_map);
  62 EXPORT_SYMBOL(cpu_sibling_map);
  63 EXPORT_SYMBOL(cpu_core_map);
  64
  65 static cpumask_t smp_commenced_mask;
  66 static cpumask_t cpu_callout_map;
  67
  68 void smp_info(struct seq_file *m)
  69 {
  70         int i;
  71
  72         seq_printf(m, "State:\n");
  73         for_each_online_cpu(i)
  74                 seq_printf(m, "CPU%d:\t\tonline\n", i);
  75 }
  76
  77 void smp_bogo(struct seq_file *m)
  78 {
  79         int i;
  80
  81         for_each_online_cpu(i)
  82                 seq_printf(m,
  83                            "Cpu%dBogo\t: %lu.%02lu\n"
  84                            "Cpu%dClkTck\t: %016lx\n",
  85                            i, cpu_data(i).udelay_val / (500000/HZ),
  86                            (cpu_data(i).udelay_val / (5000/HZ)) % 100,
  87                            i, cpu_data(i).clock_tick);
  88 }
  89
  90 extern void setup_sparc64_timer(void);
  91
  92 static volatile unsigned long callin_flag = 0;
  93
  94 void __devinit smp_callin(void)
  95 {
  96         int cpuid = hard_smp_processor_id();
  97         struct trap_per_cpu *tb = &trap_block[cpuid];;
  98
  99         __local_per_cpu_offset = __per_cpu_offset(cpuid);
 100
 101         if (tlb_type == hypervisor)
 102                 sun4v_ktsb_register();
 103
 104         __flush_tlb_all();
 105
 106         setup_sparc64_timer();
 107
 108         if (cheetah_pcache_forced_on)
 109                 cheetah_enable_pcache();
 110
 111         local_irq_enable();
 112
 113         calibrate_delay();
 114         cpu_data(cpuid).udelay_val = loops_per_jiffy;
 115         callin_flag = 1;
 116         __asm__ __volatile__("membar #Sync\n\t"
 117                              "flush  %%g6" : : : "memory");
 118
 119         /* Clear this or we will die instantly when we
 120          * schedule back to this idler...
 121          */
 122         current_thread_info()->new_child = 0;
 123
 124         /* Attach to the address space of init_task. */
 125         atomic_inc(&init_mm.mm_count);
 126         current->active_mm = &init_mm;
 127
 128         if (tb->hdesc) {
 129                 kfree(tb->hdesc);
 130                 tb->hdesc = NULL;
 131         }
 132
 133         while (!cpu_isset(cpuid, smp_commenced_mask))
 134                 rmb();
 135
 136         cpu_set(cpuid, cpu_online_map);
 137
 138         /* idle thread is expected to have preempt disabled */
 139         preempt_disable();
 140 }
 141
 142 void cpu_panic(void)
 143 {
 144         printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
 145         panic("SMP bolixed\n");
 146 }
 147
 148 /* This tick register synchronization scheme is taken entirely from
 149  * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
 150  *
 151  * The only change I've made is to rework it so that the master
 152  * initiates the synchonization instead of the slave. -DaveM
 153  */
 154
 155 #define MASTER  0
 156 #define SLAVE   (SMP_CACHE_BYTES/sizeof(unsigned long))
 157
 158 #define NUM_ROUNDS      64      /* magic value */
 159 #define NUM_ITERS       5       /* likewise */
 160
 161 static DEFINE_SPINLOCK(itc_sync_lock);
 162 static unsigned long go[SLAVE + 1];
 163
 164 #define DEBUG_TICK_SYNC 0
 165
 166 static inline long get_delta (long *rt, long *master)
 167 {
 168         unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
 169         unsigned long tcenter, t0, t1, tm;
 170         unsigned long i;
 171
 172         for (i = 0; i < NUM_ITERS; i++) {
 173                 t0 = tick_ops->get_tick();
 174                 go[MASTER] = 1;
 175                 membar_storeload();
 176                 while (!(tm = go[SLAVE]))
 177                         rmb();
 178                 go[SLAVE] = 0;
 179                 wmb();
 180                 t1 = tick_ops->get_tick();
 181
 182                 if (t1 - t0 < best_t1 - best_t0)
 183                         best_t0 = t0, best_t1 = t1, best_tm = tm;
 184         }
 185
 186         *rt = best_t1 - best_t0;
 187         *master = best_tm - best_t0;
 188
 189         /* average best_t0 and best_t1 without overflow: */
 190         tcenter = (best_t0/2 + best_t1/2);
 191         if (best_t0 % 2 + best_t1 % 2 == 2)
 192                 tcenter++;
 193         return tcenter - best_tm;
 194 }
 195
 196 void smp_synchronize_tick_client(void)
 197 {
 198         long i, delta, adj, adjust_latency = 0, done = 0;
 199         unsigned long flags, rt, master_time_stamp, bound;
 200 #if DEBUG_TICK_SYNC
 201         struct {
 202                 long rt;        /* roundtrip time */
 203                 long master;    /* master's timestamp */
 204                 long diff;      /* difference between midpoint and master's timestamp */
 205                 long lat;       /* estimate of itc adjustment latency */
 206         } t[NUM_ROUNDS];
 207 #endif
 208
 209         go[MASTER] = 1;
 210
 211         while (go[MASTER])
 212                 rmb();
 213
 214         local_irq_save(flags);
 215         {
 216                 for (i = 0; i < NUM_ROUNDS; i++) {
 217                         delta = get_delta(&rt, &master_time_stamp);
 218                         if (delta == 0) {
 219                                 done = 1;       /* let's lock on to this... */
 220                                 bound = rt;
 221                         }
 222
 223                         if (!done) {
 224                                 if (i > 0) {
 225                                         adjust_latency += -delta;
 226                                         adj = -delta + adjust_latency/4;
 227                                 } else
 228                                         adj = -delta;
 229
 230                                 tick_ops->add_tick(adj);
 231                         }
 232 #if DEBUG_TICK_SYNC
 233                         t[i].rt = rt;
 234                         t[i].master = master_time_stamp;
 235                         t[i].diff = delta;
 236                         t[i].lat = adjust_latency/4;
 237 #endif
 238                 }
 239         }
 240         local_irq_restore(flags);
 241
 242 #if DEBUG_TICK_SYNC
 243         for (i = 0; i < NUM_ROUNDS; i++)
 244                 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
 245                        t[i].rt, t[i].master, t[i].diff, t[i].lat);
 246 #endif
 247
 248         printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
 249                "maxerr %lu cycles)\n", smp_processor_id(), delta, rt);
 250 }
 251
 252 static void smp_start_sync_tick_client(int cpu);
 253
 254 static void smp_synchronize_one_tick(int cpu)
 255 {
 256         unsigned long flags, i;
 257
 258         go[MASTER] = 0;
 259
 260         smp_start_sync_tick_client(cpu);
 261
 262         /* wait for client to be ready */
 263         while (!go[MASTER])
 264                 rmb();
 265
 266         /* now let the client proceed into his loop */
 267         go[MASTER] = 0;
 268         membar_storeload();
 269
 270         spin_lock_irqsave(&itc_sync_lock, flags);
 271         {
 272                 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
 273                         while (!go[MASTER])
 274                                 rmb();
 275                         go[MASTER] = 0;
 276                         wmb();
 277                         go[SLAVE] = tick_ops->get_tick();
 278                         membar_storeload();
 279                 }
 280         }
 281         spin_unlock_irqrestore(&itc_sync_lock, flags);
 282 }
 283
 284 extern void sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load);
 285
 286 extern unsigned long sparc64_cpu_startup;
 287
 288 /* The OBP cpu startup callback truncates the 3rd arg cookie to
 289  * 32-bits (I think) so to be safe we have it read the pointer
 290  * contained here so we work on >4GB machines. -DaveM
 291  */
 292 static struct thread_info *cpu_new_thread = NULL;
 293
 294 static int __devinit smp_boot_one_cpu(unsigned int cpu)
 295 {
 296         unsigned long entry =
 297                 (unsigned long)(&sparc64_cpu_startup);
 298         unsigned long cookie =
 299                 (unsigned long)(&cpu_new_thread);
 300         struct task_struct *p;
 301         int timeout, ret;
 302
 303         p = fork_idle(cpu);
 304         callin_flag = 0;
 305         cpu_new_thread = task_thread_info(p);
 306         cpu_set(cpu, cpu_callout_map);
 307
 308         if (tlb_type == hypervisor) {
 309                 /* Alloc the mondo queues, cpu will load them.  */
 310                 sun4v_init_mondo_queues(0, cpu, 1, 0);
 311
 312 #ifdef CONFIG_SUN_LDOMS
 313                 if (ldom_domaining_enabled)
 314                         ldom_startcpu_cpuid(cpu,
 315                                             (unsigned long) cpu_new_thread);
 316                 else
 317 #endif
 318                         prom_startcpu_cpuid(cpu, entry, cookie);
 319         } else {
 320                 struct device_node *dp = of_find_node_by_cpuid(cpu);
 321
 322                 prom_startcpu(dp->node, entry, cookie);
 323         }
 324
 325         for (timeout = 0; timeout < 50000; timeout++) {
 326                 if (callin_flag)
 327                         break;
 328                 udelay(100);
 329         }
 330
 331         if (callin_flag) {
 332                 ret = 0;
 333         } else {
 334                 printk("Processor %d is stuck.\n", cpu);
 335                 cpu_clear(cpu, cpu_callout_map);
 336                 ret = -ENODEV;
 337         }
 338         cpu_new_thread = NULL;
 339
 340         return ret;
 341 }
 342
 343 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
 344 {
 345         u64 result, target;
 346         int stuck, tmp;
 347
 348         if (this_is_starfire) {
 349                 /* map to real upaid */
 350                 cpu = (((cpu & 0x3c) << 1) |
 351                         ((cpu & 0x40) >> 4) |
 352                         (cpu & 0x3));
 353         }
 354
 355         target = (cpu << 14) | 0x70;
 356 again:
 357         /* Ok, this is the real Spitfire Errata #54.
 358          * One must read back from a UDB internal register
 359          * after writes to the UDB interrupt dispatch, but
 360          * before the membar Sync for that write.
 361          * So we use the high UDB control register (ASI 0x7f,
 362          * ADDR 0x20) for the dummy read. -DaveM
 363          */
 364         tmp = 0x40;
 365         __asm__ __volatile__(
 366         "wrpr   %1, %2, %%pstate\n\t"
 367         "stxa   %4, [%0] %3\n\t"
 368         "stxa   %5, [%0+%8] %3\n\t"
 369         "add    %0, %8, %0\n\t"
 370         "stxa   %6, [%0+%8] %3\n\t"
 371         "membar #Sync\n\t"
 372         "stxa   %%g0, [%7] %3\n\t"
 373         "membar #Sync\n\t"
 374         "mov    0x20, %%g1\n\t"
 375         "ldxa   [%%g1] 0x7f, %%g0\n\t"
 376         "membar #Sync"
 377         : "=r" (tmp)
 378         : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
 379           "r" (data0), "r" (data1), "r" (data2), "r" (target),
 380           "r" (0x10), "0" (tmp)
 381         : "g1");
 382
 383         /* NOTE: PSTATE_IE is still clear. */
 384         stuck = 100000;
 385         do {
 386                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 387                         : "=r" (result)
 388                         : "i" (ASI_INTR_DISPATCH_STAT));
 389                 if (result == 0) {
 390                         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 391                                              : : "r" (pstate));
 392                         return;
 393                 }
 394                 stuck -= 1;
 395                 if (stuck == 0)
 396                         break;
 397         } while (result & 0x1);
 398         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 399                              : : "r" (pstate));
 400         if (stuck == 0) {
 401                 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
 402                        smp_processor_id(), result);
 403         } else {
 404                 udelay(2);
 405                 goto again;
 406         }
 407 }
 408
 409 static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
 410 {
 411         u64 pstate;
 412         int i;
 413
 414         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 415         for_each_cpu_mask(i, mask)
 416                 spitfire_xcall_helper(data0, data1, data2, pstate, i);
 417 }
 418
 419 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
 420  * packet, but we have no use for that.  However we do take advantage of
 421  * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
 422  */
 423 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
 424 {
 425         u64 pstate, ver;
 426         int nack_busy_id, is_jbus, need_more;
 427
 428         if (cpus_empty(mask))
 429                 return;
 430
 431         /* Unfortunately, someone at Sun had the brilliant idea to make the
 432          * busy/nack fields hard-coded by ITID number for this Ultra-III
 433          * derivative processor.
 434          */
 435         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 436         is_jbus = ((ver >> 32) == __JALAPENO_ID ||
 437                    (ver >> 32) == __SERRANO_ID);
 438
 439         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 440
 441 retry:
 442         need_more = 0;
 443         __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
 444                              : : "r" (pstate), "i" (PSTATE_IE));
 445
 446         /* Setup the dispatch data registers. */
 447         __asm__ __volatile__("stxa      %0, [%3] %6\n\t"
 448                              "stxa      %1, [%4] %6\n\t"
 449                              "stxa      %2, [%5] %6\n\t"
 450                              "membar    #Sync\n\t"
 451                              : /* no outputs */
 452                              : "r" (data0), "r" (data1), "r" (data2),
 453                                "r" (0x40), "r" (0x50), "r" (0x60),
 454                                "i" (ASI_INTR_W));
 455
 456         nack_busy_id = 0;
 457         {
 458                 int i;
 459
 460                 for_each_cpu_mask(i, mask) {
 461                         u64 target = (i << 14) | 0x70;
 462
 463                         if (!is_jbus)
 464                                 target |= (nack_busy_id << 24);
 465                         __asm__ __volatile__(
 466                                 "stxa   %%g0, [%0] %1\n\t"
 467                                 "membar #Sync\n\t"
 468                                 : /* no outputs */
 469                                 : "r" (target), "i" (ASI_INTR_W));
 470                         nack_busy_id++;
 471                         if (nack_busy_id == 32) {
 472                                 need_more = 1;
 473                                 break;
 474                         }
 475                 }
 476         }
 477
 478         /* Now, poll for completion. */
 479         {
 480                 u64 dispatch_stat;
 481                 long stuck;
 482
 483                 stuck = 100000 * nack_busy_id;
 484                 do {
 485                         __asm__ __volatile__("ldxa      [%%g0] %1, %0"
 486                                              : "=r" (dispatch_stat)
 487                                              : "i" (ASI_INTR_DISPATCH_STAT));
 488                         if (dispatch_stat == 0UL) {
 489                                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 490                                                      : : "r" (pstate));
 491                                 if (unlikely(need_more)) {
 492                                         int i, cnt = 0;
 493                                         for_each_cpu_mask(i, mask) {
 494                                                 cpu_clear(i, mask);
 495                                                 cnt++;
 496                                                 if (cnt == 32)
 497                                                         break;
 498                                         }
 499                                         goto retry;
 500                                 }
 501                                 return;
 502                         }
 503                         if (!--stuck)
 504                                 break;
 505                 } while (dispatch_stat & 0x5555555555555555UL);
 506
 507                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 508                                      : : "r" (pstate));
 509
 510                 if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) {
 511                         /* Busy bits will not clear, continue instead
 512                          * of freezing up on this cpu.
 513                          */
 514                         printk("CPU[%d]: mondo stuckage result[%016lx]\n",
 515                                smp_processor_id(), dispatch_stat);
 516                 } else {
 517                         int i, this_busy_nack = 0;
 518
 519                         /* Delay some random time with interrupts enabled
 520                          * to prevent deadlock.
 521                          */
 522                         udelay(2 * nack_busy_id);
 523
 524                         /* Clear out the mask bits for cpus which did not
 525                          * NACK us.
 526                          */
 527                         for_each_cpu_mask(i, mask) {
 528                                 u64 check_mask;
 529
 530                                 if (is_jbus)
 531                                         check_mask = (0x2UL << (2*i));
 532                                 else
 533                                         check_mask = (0x2UL <<
 534                                                       this_busy_nack);
 535                                 if ((dispatch_stat & check_mask) == 0)
 536                                         cpu_clear(i, mask);
 537                                 this_busy_nack += 2;
 538                                 if (this_busy_nack == 64)
 539                                         break;
 540                         }
 541
 542                         goto retry;
 543                 }
 544         }
 545 }
 546
 547 /* Multi-cpu list version.  */
 548 static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
 549 {
 550         struct trap_per_cpu *tb;
 551         u16 *cpu_list;
 552         u64 *mondo;
 553         cpumask_t error_mask;
 554         unsigned long flags, status;
 555         int cnt, retries, this_cpu, prev_sent, i;
 556
 557         if (cpus_empty(mask))
 558                 return;
 559
 560         /* We have to do this whole thing with interrupts fully disabled.
 561          * Otherwise if we send an xcall from interrupt context it will
 562          * corrupt both our mondo block and cpu list state.
 563          *
 564          * One consequence of this is that we cannot use timeout mechanisms
 565          * that depend upon interrupts being delivered locally.  So, for
 566          * example, we cannot sample jiffies and expect it to advance.
 567          *
 568          * Fortunately, udelay() uses %stick/%tick so we can use that.
 569          */
 570         local_irq_save(flags);
 571
 572         this_cpu = smp_processor_id();
 573         tb = &trap_block[this_cpu];
 574
 575         mondo = __va(tb->cpu_mondo_block_pa);
 576         mondo[0] = data0;
 577         mondo[1] = data1;
 578         mondo[2] = data2;
 579         wmb();
 580
 581         cpu_list = __va(tb->cpu_list_pa);
 582
 583         /* Setup the initial cpu list.  */
 584         cnt = 0;
 585         for_each_cpu_mask(i, mask)
 586                 cpu_list[cnt++] = i;
 587
 588         cpus_clear(error_mask);
 589         retries = 0;
 590         prev_sent = 0;
 591         do {
 592                 int forward_progress, n_sent;
 593
 594                 status = sun4v_cpu_mondo_send(cnt,
 595                                               tb->cpu_list_pa,
 596                                               tb->cpu_mondo_block_pa);
 597
 598                 /* HV_EOK means all cpus received the xcall, we're done.  */
 599                 if (likely(status == HV_EOK))
 600                         break;
 601
 602                 /* First, see if we made any forward progress.
 603                  *
 604                  * The hypervisor indicates successful sends by setting
 605                  * cpu list entries to the value 0xffff.
 606                  */
 607                 n_sent = 0;
 608                 for (i = 0; i < cnt; i++) {
 609                         if (likely(cpu_list[i] == 0xffff))
 610                                 n_sent++;
 611                 }
 612
 613                 forward_progress = 0;
 614                 if (n_sent > prev_sent)
 615                         forward_progress = 1;
 616
 617                 prev_sent = n_sent;
 618
 619                 /* If we get a HV_ECPUERROR, then one or more of the cpus
 620                  * in the list are in error state.  Use the cpu_state()
 621                  * hypervisor call to find out which cpus are in error state.
 622                  */
 623                 if (unlikely(status == HV_ECPUERROR)) {
 624                         for (i = 0; i < cnt; i++) {
 625                                 long err;
 626                                 u16 cpu;
 627
 628                                 cpu = cpu_list[i];
 629                                 if (cpu == 0xffff)
 630                                         continue;
 631
 632                                 err = sun4v_cpu_state(cpu);
 633                                 if (err >= 0 &&
 634                                     err == HV_CPU_STATE_ERROR) {
 635                                         cpu_list[i] = 0xffff;
 636                                         cpu_set(cpu, error_mask);
 637                                 }
 638                         }
 639                 } else if (unlikely(status != HV_EWOULDBLOCK))
 640                         goto fatal_mondo_error;
 641
 642                 /* Don't bother rewriting the CPU list, just leave the
 643                  * 0xffff and non-0xffff entries in there and the
 644                  * hypervisor will do the right thing.
 645                  *
 646                  * Only advance timeout state if we didn't make any
 647                  * forward progress.
 648                  */
 649                 if (unlikely(!forward_progress)) {
 650                         if (unlikely(++retries > 10000))
 651                                 goto fatal_mondo_timeout;
 652
 653                         /* Delay a little bit to let other cpus catch up
 654                          * on their cpu mondo queue work.
 655                          */
 656                         udelay(2 * cnt);
 657                 }
 658         } while (1);
 659
 660         local_irq_restore(flags);
 661
 662         if (unlikely(!cpus_empty(error_mask)))
 663                 goto fatal_mondo_cpu_error;
 664
 665         return;
 666
 667 fatal_mondo_cpu_error:
 668         printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
 669                "were in error state\n",
 670                this_cpu);
 671         printk(KERN_CRIT "CPU[%d]: Error mask [ ", this_cpu);
 672         for_each_cpu_mask(i, error_mask)
 673                 printk("%d ", i);
 674         printk("]\n");
 675         return;
 676
 677 fatal_mondo_timeout:
 678         local_irq_restore(flags);
 679         printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
 680                " progress after %d retries.\n",
 681                this_cpu, retries);
 682         goto dump_cpu_list_and_out;
 683
 684 fatal_mondo_error:
 685         local_irq_restore(flags);
 686         printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
 687                this_cpu, status);
 688         printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
 689                "mondo_block_pa(%lx)\n",
 690                this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
 691
 692 dump_cpu_list_and_out:
 693         printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
 694         for (i = 0; i < cnt; i++)
 695                 printk("%u ", cpu_list[i]);
 696         printk("]\n");
 697 }
 698
 699 /* Send cross call to all processors mentioned in MASK
 700  * except self.
 701  */
 702 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
 703 {
 704         u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
 705         int this_cpu = get_cpu();
 706
 707         cpus_and(mask, mask, cpu_online_map);
 708         cpu_clear(this_cpu, mask);
 709
 710         if (tlb_type == spitfire)
 711                 spitfire_xcall_deliver(data0, data1, data2, mask);
 712         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 713                 cheetah_xcall_deliver(data0, data1, data2, mask);
 714         else
 715                 hypervisor_xcall_deliver(data0, data1, data2, mask);
 716         /* NOTE: Caller runs local copy on master. */
 717
 718         put_cpu();
 719 }
 720
 721 extern unsigned long xcall_sync_tick;
 722
 723 static void smp_start_sync_tick_client(int cpu)
 724 {
 725         cpumask_t mask = cpumask_of_cpu(cpu);
 726
 727         smp_cross_call_masked(&xcall_sync_tick,
 728                               0, 0, 0, mask);
 729 }
 730
 731 /* Send cross call to all processors except self. */
 732 #define smp_cross_call(func, ctx, data1, data2) \
 733         smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
 734
 735 struct call_data_struct {
 736         void (*func) (void *info);
 737         void *info;
 738         atomic_t finished;
 739         int wait;
 740 };
 741
 742 static __cacheline_aligned_in_smp DEFINE_SPINLOCK(call_lock);
 743 static struct call_data_struct *call_data;
 744
 745 extern unsigned long xcall_call_function;
 746
 747 /**
 748  * smp_call_function(): Run a function on all other CPUs.
 749  * @func: The function to run. This must be fast and non-blocking.
 750  * @info: An arbitrary pointer to pass to the function.
 751  * @nonatomic: currently unused.
 752  * @wait: If true, wait (atomically) until function has completed on other CPUs.
 753  *
 754  * Returns 0 on success, else a negative status code. Does not return until
 755  * remote CPUs are nearly ready to execute <<func>> or are or have executed.
 756  *
 757  * You must not call this function with disabled interrupts or from a
 758  * hardware interrupt handler or from a bottom half handler.
 759  */
 760 static int smp_call_function_mask(void (*func)(void *info), void *info,
 761                                   int nonatomic, int wait, cpumask_t mask)
 762 {
 763         struct call_data_struct data;
 764         int cpus;
 765
 766         /* Can deadlock when called with interrupts disabled */
 767         WARN_ON(irqs_disabled());
 768
 769         data.func = func;
 770         data.info = info;
 771         atomic_set(&data.finished, 0);
 772         data.wait = wait;
 773
 774         spin_lock(&call_lock);
 775
 776         cpu_clear(smp_processor_id(), mask);
 777         cpus = cpus_weight(mask);
 778         if (!cpus)
 779                 goto out_unlock;
 780
 781         call_data = &data;
 782         mb();
 783
 784         smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask);
 785
 786         /* Wait for response */
 787         while (atomic_read(&data.finished) != cpus)
 788                 cpu_relax();
 789
 790 out_unlock:
 791         spin_unlock(&call_lock);
 792
 793         return 0;
 794 }
 795
 796 int smp_call_function(void (*func)(void *info), void *info,
 797                       int nonatomic, int wait)
 798 {
 799         return smp_call_function_mask(func, info, nonatomic, wait,
 800                                       cpu_online_map);
 801 }
 802
 803 void smp_call_function_client(int irq, struct pt_regs *regs)
 804 {
 805         void (*func) (void *info) = call_data->func;
 806         void *info = call_data->info;
 807
 808         clear_softint(1 << irq);
 809         if (call_data->wait) {
 810                 /* let initiator proceed only after completion */
 811                 func(info);
 812                 atomic_inc(&call_data->finished);
 813         } else {
 814                 /* let initiator proceed after getting data */
 815                 atomic_inc(&call_data->finished);
 816                 func(info);
 817         }
 818 }
 819
 820 static void tsb_sync(void *info)
 821 {
 822         struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
 823         struct mm_struct *mm = info;
 824
 825         /* It is not valid to test "currrent->active_mm == mm" here.
 826          *
 827          * The value of "current" is not changed atomically with
 828          * switch_mm().  But that's OK, we just need to check the
 829          * current cpu's trap block PGD physical address.
 830          */
 831         if (tp->pgd_paddr == __pa(mm->pgd))
 832                 tsb_context_switch(mm);
 833 }
 834
 835 void smp_tsb_sync(struct mm_struct *mm)
 836 {
 837         smp_call_function_mask(tsb_sync, mm, 0, 1, mm->cpu_vm_mask);
 838 }
 839
 840 extern unsigned long xcall_flush_tlb_mm;
 841 extern unsigned long xcall_flush_tlb_pending;
 842 extern unsigned long xcall_flush_tlb_kernel_range;
 843 extern unsigned long xcall_report_regs;
 844 extern unsigned long xcall_receive_signal;
 845 extern unsigned long xcall_new_mmu_context_version;
 846
 847 #ifdef DCACHE_ALIASING_POSSIBLE
 848 extern unsigned long xcall_flush_dcache_page_cheetah;
 849 #endif
 850 extern unsigned long xcall_flush_dcache_page_spitfire;
 851
 852 #ifdef CONFIG_DEBUG_DCFLUSH
 853 extern atomic_t dcpage_flushes;
 854 extern atomic_t dcpage_flushes_xcall;
 855 #endif
 856
 857 static __inline__ void __local_flush_dcache_page(struct page *page)
 858 {
 859 #ifdef DCACHE_ALIASING_POSSIBLE
 860         __flush_dcache_page(page_address(page),
 861                             ((tlb_type == spitfire) &&
 862                              page_mapping(page) != NULL));
 863 #else
 864         if (page_mapping(page) != NULL &&
 865             tlb_type == spitfire)
 866                 __flush_icache_page(__pa(page_address(page)));
 867 #endif
 868 }
 869
 870 void smp_flush_dcache_page_impl(struct page *page, int cpu)
 871 {
 872         cpumask_t mask = cpumask_of_cpu(cpu);
 873         int this_cpu;
 874
 875         if (tlb_type == hypervisor)
 876                 return;
 877
 878 #ifdef CONFIG_DEBUG_DCFLUSH
 879         atomic_inc(&dcpage_flushes);
 880 #endif
 881
 882         this_cpu = get_cpu();
 883
 884         if (cpu == this_cpu) {
 885                 __local_flush_dcache_page(page);
 886         } else if (cpu_online(cpu)) {
 887                 void *pg_addr = page_address(page);
 888                 u64 data0;
 889
 890                 if (tlb_type == spitfire) {
 891                         data0 =
 892                                 ((u64)&xcall_flush_dcache_page_spitfire);
 893                         if (page_mapping(page) != NULL)
 894                                 data0 |= ((u64)1 << 32);
 895                         spitfire_xcall_deliver(data0,
 896                                                __pa(pg_addr),
 897                                                (u64) pg_addr,
 898                                                mask);
 899                 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 900 #ifdef DCACHE_ALIASING_POSSIBLE
 901                         data0 =
 902                                 ((u64)&xcall_flush_dcache_page_cheetah);
 903                         cheetah_xcall_deliver(data0,
 904                                               __pa(pg_addr),
 905                                               0, mask);
 906 #endif
 907                 }
 908 #ifdef CONFIG_DEBUG_DCFLUSH
 909                 atomic_inc(&dcpage_flushes_xcall);
 910 #endif
 911         }
 912
 913         put_cpu();
 914 }
 915
 916 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
 917 {
 918         void *pg_addr = page_address(page);
 919         cpumask_t mask = cpu_online_map;
 920         u64 data0;
 921         int this_cpu;
 922
 923         if (tlb_type == hypervisor)
 924                 return;
 925
 926         this_cpu = get_cpu();
 927
 928         cpu_clear(this_cpu, mask);
 929
 930 #ifdef CONFIG_DEBUG_DCFLUSH
 931         atomic_inc(&dcpage_flushes);
 932 #endif
 933         if (cpus_empty(mask))
 934                 goto flush_self;
 935         if (tlb_type == spitfire) {
 936                 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
 937                 if (page_mapping(page) != NULL)
 938                         data0 |= ((u64)1 << 32);
 939                 spitfire_xcall_deliver(data0,
 940                                        __pa(pg_addr),
 941                                        (u64) pg_addr,
 942                                        mask);
 943         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 944 #ifdef DCACHE_ALIASING_POSSIBLE
 945                 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
 946                 cheetah_xcall_deliver(data0,
 947                                       __pa(pg_addr),
 948                                       0, mask);
 949 #endif
 950         }
 951 #ifdef CONFIG_DEBUG_DCFLUSH
 952         atomic_inc(&dcpage_flushes_xcall);
 953 #endif
 954  flush_self:
 955         __local_flush_dcache_page(page);
 956
 957         put_cpu();
 958 }
 959
 960 static void __smp_receive_signal_mask(cpumask_t mask)
 961 {
 962         smp_cross_call_masked(&xcall_receive_signal, 0, 0, 0, mask);
 963 }
 964
 965 void smp_receive_signal(int cpu)
 966 {
 967         cpumask_t mask = cpumask_of_cpu(cpu);
 968
 969         if (cpu_online(cpu))
 970                 __smp_receive_signal_mask(mask);
 971 }
 972
 973 void smp_receive_signal_client(int irq, struct pt_regs *regs)
 974 {
 975         clear_softint(1 << irq);
 976 }
 977
 978 void smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
 979 {
 980         struct mm_struct *mm;
 981         unsigned long flags;
 982
 983         clear_softint(1 << irq);
 984
 985         /* See if we need to allocate a new TLB context because
 986          * the version of the one we are using is now out of date.
 987          */
 988         mm = current->active_mm;
 989         if (unlikely(!mm || (mm == &init_mm)))
 990                 return;
 991
 992         spin_lock_irqsave(&mm->context.lock, flags);
 993
 994         if (unlikely(!CTX_VALID(mm->context)))
 995                 get_new_mmu_context(mm);
 996
 997         spin_unlock_irqrestore(&mm->context.lock, flags);
 998
 999         load_secondary_context(mm);
1000         __flush_tlb_mm(CTX_HWBITS(mm->context),
1001                        SECONDARY_CONTEXT);
1002 }
1003
1004 void smp_new_mmu_context_version(void)
1005 {
1006         smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
1007 }
1008
1009 void smp_report_regs(void)
1010 {
1011         smp_cross_call(&xcall_report_regs, 0, 0, 0);
1012 }
1013
1014 /* We know that the window frames of the user have been flushed
1015  * to the stack before we get here because all callers of us
1016  * are flush_tlb_*() routines, and these run after flush_cache_*()
1017  * which performs the flushw.
1018  *
1019  * The SMP TLB coherency scheme we use works as follows:
1020  *
1021  * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1022  *    space has (potentially) executed on, this is the heuristic
1023  *    we use to avoid doing cross calls.
1024  *
1025  *    Also, for flushing from kswapd and also for clones, we
1026  *    use cpu_vm_mask as the list of cpus to make run the TLB.
1027  *
1028  * 2) TLB context numbers are shared globally across all processors
1029  *    in the system, this allows us to play several games to avoid
1030  *    cross calls.
1031  *
1032  *    One invariant is that when a cpu switches to a process, and
1033  *    that processes tsk->active_mm->cpu_vm_mask does not have the
1034  *    current cpu's bit set, that tlb context is flushed locally.
1035  *
1036  *    If the address space is non-shared (ie. mm->count == 1) we avoid
1037  *    cross calls when we want to flush the currently running process's
1038  *    tlb state.  This is done by clearing all cpu bits except the current
1039  *    processor's in current->active_mm->cpu_vm_mask and performing the
1040  *    flush locally only.  This will force any subsequent cpus which run
1041  *    this task to flush the context from the local tlb if the process
1042  *    migrates to another cpu (again).
1043  *
1044  * 3) For shared address spaces (threads) and swapping we bite the
1045  *    bullet for most cases and perform the cross call (but only to
1046  *    the cpus listed in cpu_vm_mask).
1047  *
1048  *    The performance gain from "optimizing" away the cross call for threads is
1049  *    questionable (in theory the big win for threads is the massive sharing of
1050  *    address space state across processors).
1051  */
1052
1053 /* This currently is only used by the hugetlb arch pre-fault
1054  * hook on UltraSPARC-III+ and later when changing the pagesize
1055  * bits of the context register for an address space.
1056  */
1057 void smp_flush_tlb_mm(struct mm_struct *mm)
1058 {
1059         u32 ctx = CTX_HWBITS(mm->context);
1060         int cpu = get_cpu();
1061
1062         if (atomic_read(&mm->mm_users) == 1) {
1063                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1064                 goto local_flush_and_out;
1065         }
1066
1067         smp_cross_call_masked(&xcall_flush_tlb_mm,
1068                               ctx, 0, 0,
1069                               mm->cpu_vm_mask);
1070
1071 local_flush_and_out:
1072         __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1073
1074         put_cpu();
1075 }
1076
1077 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1078 {
1079         u32 ctx = CTX_HWBITS(mm->context);
1080         int cpu = get_cpu();
1081
1082         if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
1083                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1084         else
1085                 smp_cross_call_masked(&xcall_flush_tlb_pending,
1086                                       ctx, nr, (unsigned long) vaddrs,
1087                                       mm->cpu_vm_mask);
1088
1089         __flush_tlb_pending(ctx, nr, vaddrs);
1090
1091         put_cpu();
1092 }
1093
1094 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1095 {
1096         start &= PAGE_MASK;
1097         end    = PAGE_ALIGN(end);
1098         if (start != end) {
1099                 smp_cross_call(&xcall_flush_tlb_kernel_range,
1100                                0, start, end);
1101
1102                 __flush_tlb_kernel_range(start, end);
1103         }
1104 }
1105
1106 /* CPU capture. */
1107 /* #define CAPTURE_DEBUG */
1108 extern unsigned long xcall_capture;
1109
1110 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1111 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1112 static unsigned long penguins_are_doing_time;
1113
1114 void smp_capture(void)
1115 {
1116         int result = atomic_add_ret(1, &smp_capture_depth);
1117
1118         if (result == 1) {
1119                 int ncpus = num_online_cpus();
1120
1121 #ifdef CAPTURE_DEBUG
1122                 printk("CPU[%d]: Sending penguins to jail...",
1123                        smp_processor_id());
1124 #endif
1125                 penguins_are_doing_time = 1;
1126                 membar_storestore_loadstore();
1127                 atomic_inc(&smp_capture_registry);
1128                 smp_cross_call(&xcall_capture, 0, 0, 0);
1129                 while (atomic_read(&smp_capture_registry) != ncpus)
1130                         rmb();
1131 #ifdef CAPTURE_DEBUG
1132                 printk("done\n");
1133 #endif
1134         }
1135 }
1136
1137 void smp_release(void)
1138 {
1139         if (atomic_dec_and_test(&smp_capture_depth)) {
1140 #ifdef CAPTURE_DEBUG
1141                 printk("CPU[%d]: Giving pardon to "
1142                        "imprisoned penguins\n",
1143                        smp_processor_id());
1144 #endif
1145                 penguins_are_doing_time = 0;
1146                 membar_storeload_storestore();
1147                 atomic_dec(&smp_capture_registry);
1148         }
1149 }
1150
1151 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
1152  * can service tlb flush xcalls...
1153  */
1154 extern void prom_world(int);
1155
1156 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
1157 {
1158         clear_softint(1 << irq);
1159
1160         preempt_disable();
1161
1162         __asm__ __volatile__("flushw");
1163         prom_world(1);
1164         atomic_inc(&smp_capture_registry);
1165         membar_storeload_storestore();
1166         while (penguins_are_doing_time)
1167                 rmb();
1168         atomic_dec(&smp_capture_registry);
1169         prom_world(0);
1170
1171         preempt_enable();
1172 }
1173
1174 void __init smp_tick_init(void)
1175 {
1176         boot_cpu_id = hard_smp_processor_id();
1177 }
1178
1179 /* /proc/profile writes can call this, don't __init it please. */
1180 int setup_profiling_timer(unsigned int multiplier)
1181 {
1182         return -EINVAL;
1183 }
1184
1185 void __init smp_prepare_cpus(unsigned int max_cpus)
1186 {
1187         cpu_data(boot_cpu_id).udelay_val = loops_per_jiffy;
1188 }
1189
1190 void __devinit smp_prepare_boot_cpu(void)
1191 {
1192 }
1193
1194 void __devinit smp_fill_in_sib_core_maps(void)
1195 {
1196         unsigned int i;
1197
1198         for_each_possible_cpu(i) {
1199                 unsigned int j;
1200
1201                 if (cpu_data(i).core_id == 0) {
1202                         cpu_set(i, cpu_core_map[i]);
1203                         continue;
1204                 }
1205
1206                 for_each_possible_cpu(j) {
1207                         if (cpu_data(i).core_id ==
1208                             cpu_data(j).core_id)
1209                                 cpu_set(j, cpu_core_map[i]);
1210                 }
1211         }
1212
1213         for_each_possible_cpu(i) {
1214                 unsigned int j;
1215
1216                 if (cpu_data(i).proc_id == -1) {
1217                         cpu_set(i, cpu_sibling_map[i]);
1218                         continue;
1219                 }
1220
1221                 for_each_possible_cpu(j) {
1222                         if (cpu_data(i).proc_id ==
1223                             cpu_data(j).proc_id)
1224                                 cpu_set(j, cpu_sibling_map[i]);
1225                 }
1226         }
1227 }
1228
1229 int __cpuinit __cpu_up(unsigned int cpu)
1230 {
1231         int ret = smp_boot_one_cpu(cpu);
1232
1233         if (!ret) {
1234                 cpu_set(cpu, smp_commenced_mask);
1235                 while (!cpu_isset(cpu, cpu_online_map))
1236                         mb();
1237                 if (!cpu_isset(cpu, cpu_online_map)) {
1238                         ret = -ENODEV;
1239                 } else {
1240                         /* On SUN4V, writes to %tick and %stick are
1241                          * not allowed.
1242                          */
1243                         if (tlb_type != hypervisor)
1244                                 smp_synchronize_one_tick(cpu);
1245                 }
1246         }
1247         return ret;
1248 }
1249
1250 #ifdef CONFIG_HOTPLUG_CPU
1251 int __cpu_disable(void)
1252 {
1253         printk(KERN_ERR "SMP: __cpu_disable() on cpu %d\n",
1254                smp_processor_id());
1255         return -ENODEV;
1256 }
1257
1258 void __cpu_die(unsigned int cpu)
1259 {
1260         printk(KERN_ERR "SMP: __cpu_die(%u)\n", cpu);
1261 }
1262 #endif
1263
1264 void __init smp_cpus_done(unsigned int max_cpus)
1265 {
1266         unsigned long bogosum = 0;
1267         int i;
1268
1269         for_each_online_cpu(i)
1270                 bogosum += cpu_data(i).udelay_val;
1271         printk("Total of %ld processors activated "
1272                "(%lu.%02lu BogoMIPS).\n",
1273                (long) num_online_cpus(),
1274                bogosum/(500000/HZ),
1275                (bogosum/(5000/HZ))%100);
1276 }
1277
1278 void smp_send_reschedule(int cpu)
1279 {
1280         smp_receive_signal(cpu);
1281 }
1282
1283 /* This is a nop because we capture all other cpus
1284  * anyways when making the PROM active.
1285  */
1286 void smp_send_stop(void)
1287 {
1288 }
1289
1290 unsigned long __per_cpu_base __read_mostly;
1291 unsigned long __per_cpu_shift __read_mostly;
1292
1293 EXPORT_SYMBOL(__per_cpu_base);
1294 EXPORT_SYMBOL(__per_cpu_shift);
1295
1296 void __init real_setup_per_cpu_areas(void)
1297 {
1298         unsigned long goal, size, i;
1299         char *ptr;
1300
1301         /* Copy section for each CPU (we discard the original) */
1302         goal = PERCPU_ENOUGH_ROOM;
1303
1304         __per_cpu_shift = PAGE_SHIFT;
1305         for (size = PAGE_SIZE; size < goal; size <<= 1UL)
1306                 __per_cpu_shift++;
1307
1308         ptr = alloc_bootmem_pages(size * NR_CPUS);
1309
1310         __per_cpu_base = ptr - __per_cpu_start;
1311
1312         for (i = 0; i < NR_CPUS; i++, ptr += size)
1313                 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
1314
1315         /* Setup %g5 for the boot cpu.  */
1316         __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());
1317 }