arch/sparc64/kernel/irq.c

   1 /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
   2  * irq.c: UltraSparc IRQ handling/init/registry.
   3  *
   4  * Copyright (C) 1997  David S. Miller  (davem@caip.rutgers.edu)
   5  * Copyright (C) 1998  Eddie C. Dost    (ecd@skynet.be)
   6  * Copyright (C) 1998  Jakub Jelinek    (jj@ultra.linux.cz)
   7  */
   8
   9 #include <linux/config.h>
  10 #include <linux/module.h>
  11 #include <linux/sched.h>
  12 #include <linux/ptrace.h>
  13 #include <linux/errno.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/signal.h>
  16 #include <linux/mm.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/slab.h>
  19 #include <linux/random.h>
  20 #include <linux/init.h>
  21 #include <linux/delay.h>
  22 #include <linux/proc_fs.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/bootmem.h>
  25
  26 #include <asm/ptrace.h>
  27 #include <asm/processor.h>
  28 #include <asm/atomic.h>
  29 #include <asm/system.h>
  30 #include <asm/irq.h>
  31 #include <asm/io.h>
  32 #include <asm/sbus.h>
  33 #include <asm/iommu.h>
  34 #include <asm/upa.h>
  35 #include <asm/oplib.h>
  36 #include <asm/timer.h>
  37 #include <asm/smp.h>
  38 #include <asm/starfire.h>
  39 #include <asm/uaccess.h>
  40 #include <asm/cache.h>
  41 #include <asm/cpudata.h>
  42 #include <asm/auxio.h>
  43 #include <asm/head.h>
  44
  45 #ifdef CONFIG_SMP
  46 static void distribute_irqs(void);
  47 #endif
  48
  49 /* UPA nodes send interrupt packet to UltraSparc with first data reg
  50  * value low 5 (7 on Starfire) bits holding the IRQ identifier being
  51  * delivered.  We must translate this into a non-vector IRQ so we can
  52  * set the softint on this cpu.
  53  *
  54  * To make processing these packets efficient and race free we use
  55  * an array of irq buckets below.  The interrupt vector handler in
  56  * entry.S feeds incoming packets into per-cpu pil-indexed lists.
  57  * The IVEC handler does not need to act atomically, the PIL dispatch
  58  * code uses CAS to get an atomic snapshot of the list and clear it
  59  * at the same time.
  60  */
  61
  62 struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
  63
  64 /* This has to be in the main kernel image, it cannot be
  65  * turned into per-cpu data.  The reason is that the main
  66  * kernel image is locked into the TLB and this structure
  67  * is accessed from the vectored interrupt trap handler.  If
  68  * access to this structure takes a TLB miss it could cause
  69  * the 5-level sparc v9 trap stack to overflow.
  70  */
  71 struct irq_work_struct {
  72         unsigned int    irq_worklists[16];
  73 };
  74 struct irq_work_struct __irq_work[NR_CPUS];
  75 #define irq_work(__cpu, __pil)  &(__irq_work[(__cpu)].irq_worklists[(__pil)])
  76
  77 static struct irqaction *irq_action[NR_IRQS+1];
  78
  79 /* This only synchronizes entities which modify IRQ handler
  80  * state and some selected user-level spots that want to
  81  * read things in the table.  IRQ handler processing orders
  82  * its' accesses such that no locking is needed.
  83  */
  84 static DEFINE_SPINLOCK(irq_action_lock);
  85
  86 static void register_irq_proc (unsigned int irq);
  87
  88 /*
  89  * Upper 2b of irqaction->flags holds the ino.
  90  * irqaction->mask holds the smp affinity information.
  91  */
  92 #define put_ino_in_irqaction(action, irq) \
  93         action->flags &= 0xffffffffffffUL; \
  94         if (__bucket(irq) == &pil0_dummy_bucket) \
  95                 action->flags |= 0xdeadUL << 48;  \
  96         else \
  97                 action->flags |= __irq_ino(irq) << 48;
  98 #define get_ino_in_irqaction(action)    (action->flags >> 48)
  99
 100 #define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff)
 101 #define get_smpaff_in_irqaction(action)         ((action)->mask)
 102
 103 int show_interrupts(struct seq_file *p, void *v)
 104 {
 105         unsigned long flags;
 106         int i = *(loff_t *) v;
 107         struct irqaction *action;
 108 #ifdef CONFIG_SMP
 109         int j;
 110 #endif
 111
 112         spin_lock_irqsave(&irq_action_lock, flags);
 113         if (i <= NR_IRQS) {
 114                 if (!(action = *(i + irq_action)))
 115                         goto out_unlock;
 116                 seq_printf(p, "%3d: ", i);
 117 #ifndef CONFIG_SMP
 118                 seq_printf(p, "%10u ", kstat_irqs(i));
 119 #else
 120                 for (j = 0; j < NR_CPUS; j++) {
 121                         if (!cpu_online(j))
 122                                 continue;
 123                         seq_printf(p, "%10u ",
 124                                    kstat_cpu(j).irqs[i]);
 125                 }
 126 #endif
 127                 seq_printf(p, " %s:%lx", action->name,
 128                            get_ino_in_irqaction(action));
 129                 for (action = action->next; action; action = action->next) {
 130                         seq_printf(p, ", %s:%lx", action->name,
 131                                    get_ino_in_irqaction(action));
 132                 }
 133                 seq_putc(p, '\n');
 134         }
 135 out_unlock:
 136         spin_unlock_irqrestore(&irq_action_lock, flags);
 137
 138         return 0;
 139 }
 140
 141 extern unsigned long real_hard_smp_processor_id(void);
 142
 143 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
 144 {
 145         unsigned int tid;
 146
 147         if (this_is_starfire) {
 148                 tid = starfire_translate(imap, cpuid);
 149                 tid <<= IMAP_TID_SHIFT;
 150                 tid &= IMAP_TID_UPA;
 151         } else {
 152                 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 153                         unsigned long ver;
 154
 155                         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 156                         if ((ver >> 32UL) == __JALAPENO_ID ||
 157                             (ver >> 32UL) == __SERRANO_ID) {
 158                                 tid = cpuid << IMAP_TID_SHIFT;
 159                                 tid &= IMAP_TID_JBUS;
 160                         } else {
 161                                 unsigned int a = cpuid & 0x1f;
 162                                 unsigned int n = (cpuid >> 5) & 0x1f;
 163
 164                                 tid = ((a << IMAP_AID_SHIFT) |
 165                                        (n << IMAP_NID_SHIFT));
 166                                 tid &= (IMAP_AID_SAFARI |
 167                                         IMAP_NID_SAFARI);;
 168                         }
 169                 } else {
 170                         tid = cpuid << IMAP_TID_SHIFT;
 171                         tid &= IMAP_TID_UPA;
 172                 }
 173         }
 174
 175         return tid;
 176 }
 177
 178 /* Now these are always passed a true fully specified sun4u INO. */
 179 void enable_irq(unsigned int irq)
 180 {
 181         struct ino_bucket *bucket = __bucket(irq);
 182         unsigned long imap, cpuid;
 183
 184         imap = bucket->imap;
 185         if (imap == 0UL)
 186                 return;
 187
 188         preempt_disable();
 189
 190         /* This gets the physical processor ID, even on uniprocessor,
 191          * so we can always program the interrupt target correctly.
 192          */
 193         cpuid = real_hard_smp_processor_id();
 194
 195         if (tlb_type == hypervisor) {
 196                 unsigned int ino = __irq_ino(irq);
 197                 int err;
 198
 199                 err = sun4v_intr_settarget(ino, cpuid);
 200                 if (err != HV_EOK)
 201                         printk("sun4v_intr_settarget(%x,%lu): err(%d)\n",
 202                                ino, cpuid, err);
 203                 err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
 204                 if (err != HV_EOK)
 205                         printk("sun4v_intr_setenabled(%x): err(%d)\n",
 206                                ino, err);
 207         } else {
 208                 unsigned int tid = sun4u_compute_tid(imap, cpuid);
 209
 210                 /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product
 211                  * of this SYSIO's preconfigured IGN in the SYSIO Control
 212                  * Register, the hardware just mirrors that value here.
 213                  * However for Graphics and UPA Slave devices the full
 214                  * IMAP_INR field can be set by the programmer here.
 215                  *
 216                  * Things like FFB can now be handled via the new IRQ
 217                  * mechanism.
 218                  */
 219                 upa_writel(tid | IMAP_VALID, imap);
 220         }
 221
 222         preempt_enable();
 223 }
 224
 225 /* This now gets passed true ino's as well. */
 226 void disable_irq(unsigned int irq)
 227 {
 228         struct ino_bucket *bucket = __bucket(irq);
 229         unsigned long imap;
 230
 231         imap = bucket->imap;
 232         if (imap != 0UL) {
 233                 if (tlb_type == hypervisor) {
 234                         unsigned int ino = __irq_ino(irq);
 235                         int err;
 236
 237                         err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
 238                         if (err != HV_EOK)
 239                                 printk("sun4v_intr_setenabled(%x): "
 240                                        "err(%d)\n", ino, err);
 241                 } else {
 242                         u32 tmp;
 243
 244                         /* NOTE: We do not want to futz with the IRQ clear registers
 245                          *       and move the state to IDLE, the SCSI code does call
 246                          *       disable_irq() to assure atomicity in the queue cmd
 247                          *       SCSI adapter driver code.  Thus we'd lose interrupts.
 248                          */
 249                         tmp = upa_readl(imap);
 250                         tmp &= ~IMAP_VALID;
 251                         upa_writel(tmp, imap);
 252                 }
 253         }
 254 }
 255
 256 /* The timer is the one "weird" interrupt which is generated by
 257  * the CPU %tick register and not by some normal vectored interrupt
 258  * source.  To handle this special case, we use this dummy INO bucket.
 259  */
 260 static struct irq_desc pil0_dummy_desc;
 261 static struct ino_bucket pil0_dummy_bucket = {
 262         .irq_info       =       &pil0_dummy_desc,
 263 };
 264
 265 static void build_irq_error(const char *msg, unsigned int ino, int pil, int inofixup,
 266                             unsigned long iclr, unsigned long imap,
 267                             struct ino_bucket *bucket)
 268 {
 269         prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> "
 270                     "(%d:%d:%016lx:%016lx), halting...\n",
 271                     ino, bucket->pil, bucket->iclr, bucket->imap,
 272                     pil, inofixup, iclr, imap);
 273         prom_halt();
 274 }
 275
 276 unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap)
 277 {
 278         struct ino_bucket *bucket;
 279         int ino;
 280
 281         if (pil == 0) {
 282                 if (iclr != 0UL || imap != 0UL) {
 283                         prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n",
 284                                     iclr, imap);
 285                         prom_halt();
 286                 }
 287                 return __irq(&pil0_dummy_bucket);
 288         }
 289
 290         BUG_ON(tlb_type == hypervisor);
 291
 292         /* RULE: Both must be specified in all other cases. */
 293         if (iclr == 0UL || imap == 0UL) {
 294                 prom_printf("Invalid build_irq %d %d %016lx %016lx\n",
 295                             pil, inofixup, iclr, imap);
 296                 prom_halt();
 297         }
 298
 299         ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
 300         if (ino > NUM_IVECS) {
 301                 prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n",
 302                             ino, pil, inofixup, iclr, imap);
 303                 prom_halt();
 304         }
 305
 306         bucket = &ivector_table[ino];
 307         if (bucket->flags & IBF_ACTIVE)
 308                 build_irq_error("IRQ: Trying to build active INO bucket.\n",
 309                                 ino, pil, inofixup, iclr, imap, bucket);
 310
 311         if (bucket->irq_info) {
 312                 if (bucket->imap != imap || bucket->iclr != iclr)
 313                         build_irq_error("IRQ: Trying to reinit INO bucket.\n",
 314                                         ino, pil, inofixup, iclr, imap, bucket);
 315
 316                 goto out;
 317         }
 318
 319         bucket->irq_info = kzalloc(sizeof(struct irq_desc), GFP_ATOMIC);
 320         if (!bucket->irq_info) {
 321                 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
 322                 prom_halt();
 323         }
 324
 325         /* Ok, looks good, set it up.  Don't touch the irq_chain or
 326          * the pending flag.
 327          */
 328         bucket->imap  = imap;
 329         bucket->iclr  = iclr;
 330         bucket->pil   = pil;
 331         bucket->flags = 0;
 332
 333 out:
 334         return __irq(bucket);
 335 }
 336
 337 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, int pil, unsigned char flags)
 338 {
 339         struct ino_bucket *bucket;
 340         unsigned long sysino;
 341
 342         sysino = sun4v_devino_to_sysino(devhandle, devino);
 343
 344         bucket = &ivector_table[sysino];
 345
 346         /* Catch accidental accesses to these things.  IMAP/ICLR handling
 347          * is done by hypervisor calls on sun4v platforms, not by direct
 348          * register accesses.
 349          *
 350          * But we need to make them look unique for the disable_irq() logic
 351          * in free_irq().
 352          */
 353         bucket->imap = ~0UL - sysino;
 354         bucket->iclr = ~0UL - sysino;
 355
 356         bucket->pil = pil;
 357         bucket->flags = flags;
 358
 359         bucket->irq_info = kzalloc(sizeof(struct irq_desc), GFP_ATOMIC);
 360         if (!bucket->irq_info) {
 361                 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
 362                 prom_halt();
 363         }
 364
 365         return __irq(bucket);
 366 }
 367
 368 static void atomic_bucket_insert(struct ino_bucket *bucket)
 369 {
 370         unsigned long pstate;
 371         unsigned int *ent;
 372
 373         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 374         __asm__ __volatile__("wrpr %0, %1, %%pstate"
 375                              : : "r" (pstate), "i" (PSTATE_IE));
 376         ent = irq_work(smp_processor_id(), bucket->pil);
 377         bucket->irq_chain = *ent;
 378         *ent = __irq(bucket);
 379         __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
 380 }
 381
 382 static int check_irq_sharing(int pil, unsigned long irqflags)
 383 {
 384         struct irqaction *action, *tmp;
 385
 386         action = *(irq_action + pil);
 387         if (action) {
 388                 if ((action->flags & SA_SHIRQ) && (irqflags & SA_SHIRQ)) {
 389                         for (tmp = action; tmp->next; tmp = tmp->next)
 390                                 ;
 391                 } else {
 392                         return -EBUSY;
 393                 }
 394         }
 395         return 0;
 396 }
 397
 398 static void append_irq_action(int pil, struct irqaction *action)
 399 {
 400         struct irqaction **pp = irq_action + pil;
 401
 402         while (*pp)
 403                 pp = &((*pp)->next);
 404         *pp = action;
 405 }
 406
 407 static struct irqaction *get_action_slot(struct ino_bucket *bucket)
 408 {
 409         struct irq_desc *desc = bucket->irq_info;
 410         int max_irq, i;
 411
 412         max_irq = 1;
 413         if (bucket->flags & IBF_PCI)
 414                 max_irq = MAX_IRQ_DESC_ACTION;
 415         for (i = 0; i < max_irq; i++) {
 416                 struct irqaction *p = &desc->action[i];
 417                 u32 mask = (1 << i);
 418
 419                 if (desc->action_active_mask & mask)
 420                         continue;
 421
 422                 desc->action_active_mask |= mask;
 423                 return p;
 424         }
 425         return NULL;
 426 }
 427
 428 int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *),
 429                 unsigned long irqflags, const char *name, void *dev_id)
 430 {
 431         struct irqaction *action;
 432         struct ino_bucket *bucket = __bucket(irq);
 433         unsigned long flags;
 434         int pending = 0;
 435
 436         if (unlikely(!handler))
 437                 return -EINVAL;
 438
 439         if (unlikely(!bucket->irq_info))
 440                 return -ENODEV;
 441
 442         if ((bucket != &pil0_dummy_bucket) && (irqflags & SA_SAMPLE_RANDOM)) {
 443                 /*
 444                  * This function might sleep, we want to call it first,
 445                  * outside of the atomic block. In SA_STATIC_ALLOC case,
 446                  * random driver's kmalloc will fail, but it is safe.
 447                  * If already initialized, random driver will not reinit.
 448                  * Yes, this might clear the entropy pool if the wrong
 449                  * driver is attempted to be loaded, without actually
 450                  * installing a new handler, but is this really a problem,
 451                  * only the sysadmin is able to do this.
 452                  */
 453                 rand_initialize_irq(irq);
 454         }
 455
 456         spin_lock_irqsave(&irq_action_lock, flags);
 457
 458         if (check_irq_sharing(bucket->pil, irqflags)) {
 459                 spin_unlock_irqrestore(&irq_action_lock, flags);
 460                 return -EBUSY;
 461         }
 462
 463         action = get_action_slot(bucket);
 464         if (!action) {
 465                 spin_unlock_irqrestore(&irq_action_lock, flags);
 466                 return -ENOMEM;
 467         }
 468
 469         bucket->flags |= IBF_ACTIVE;
 470         pending = 0;
 471         if (bucket != &pil0_dummy_bucket) {
 472                 pending = bucket->pending;
 473                 if (pending)
 474                         bucket->pending = 0;
 475         }
 476
 477         action->handler = handler;
 478         action->flags = irqflags;
 479         action->name = name;
 480         action->next = NULL;
 481         action->dev_id = dev_id;
 482         put_ino_in_irqaction(action, irq);
 483         put_smpaff_in_irqaction(action, CPU_MASK_NONE);
 484
 485         append_irq_action(bucket->pil, action);
 486
 487         enable_irq(irq);
 488
 489         /* We ate the IVEC already, this makes sure it does not get lost. */
 490         if (pending) {
 491                 atomic_bucket_insert(bucket);
 492                 set_softint(1 << bucket->pil);
 493         }
 494
 495         spin_unlock_irqrestore(&irq_action_lock, flags);
 496
 497         if (bucket != &pil0_dummy_bucket)
 498                 register_irq_proc(__irq_ino(irq));
 499
 500 #ifdef CONFIG_SMP
 501         distribute_irqs();
 502 #endif
 503         return 0;
 504 }
 505
 506 EXPORT_SYMBOL(request_irq);
 507
 508 static struct irqaction *unlink_irq_action(unsigned int irq, void *dev_id)
 509 {
 510         struct ino_bucket *bucket = __bucket(irq);
 511         struct irqaction *action, **pp;
 512
 513         pp = irq_action + bucket->pil;
 514         action = *pp;
 515         if (unlikely(!action))
 516                 return NULL;
 517
 518         if (unlikely(!action->handler)) {
 519                 printk("Freeing free IRQ %d\n", bucket->pil);
 520                 return NULL;
 521         }
 522
 523         while (action && action->dev_id != dev_id) {
 524                 pp = &action->next;
 525                 action = *pp;
 526         }
 527
 528         if (likely(action))
 529                 *pp = action->next;
 530
 531         return action;
 532 }
 533
 534 void free_irq(unsigned int irq, void *dev_id)
 535 {
 536         struct irqaction *action;
 537         struct ino_bucket *bucket;
 538         unsigned long flags;
 539
 540         spin_lock_irqsave(&irq_action_lock, flags);
 541
 542         action = unlink_irq_action(irq, dev_id);
 543
 544         spin_unlock_irqrestore(&irq_action_lock, flags);
 545
 546         if (unlikely(!action))
 547                 return;
 548
 549         synchronize_irq(irq);
 550
 551         spin_lock_irqsave(&irq_action_lock, flags);
 552
 553         bucket = __bucket(irq);
 554         if (bucket != &pil0_dummy_bucket) {
 555                 struct irq_desc *desc = bucket->irq_info;
 556                 int ent, i;
 557
 558                 for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
 559                         struct irqaction *p = &desc->action[i];
 560
 561                         if (p == action) {
 562                                 desc->action_active_mask &= ~(1 << i);
 563                                 break;
 564                         }
 565                 }
 566
 567                 if (!desc->action_active_mask) {
 568                         unsigned long imap = bucket->imap;
 569
 570                         /* This unique interrupt source is now inactive. */
 571                         bucket->flags &= ~IBF_ACTIVE;
 572
 573                         /* See if any other buckets share this bucket's IMAP
 574                          * and are still active.
 575                          */
 576                         for (ent = 0; ent < NUM_IVECS; ent++) {
 577                                 struct ino_bucket *bp = &ivector_table[ent];
 578                                 if (bp != bucket        &&
 579                                     bp->imap == imap    &&
 580                                     (bp->flags & IBF_ACTIVE) != 0)
 581                                         break;
 582                         }
 583
 584                         /* Only disable when no other sub-irq levels of
 585                          * the same IMAP are active.
 586                          */
 587                         if (ent == NUM_IVECS)
 588                                 disable_irq(irq);
 589                 }
 590         }
 591
 592         spin_unlock_irqrestore(&irq_action_lock, flags);
 593 }
 594
 595 EXPORT_SYMBOL(free_irq);
 596
 597 #ifdef CONFIG_SMP
 598 void synchronize_irq(unsigned int irq)
 599 {
 600         struct ino_bucket *bucket = __bucket(irq);
 601
 602 #if 0
 603         /* The following is how I wish I could implement this.
 604          * Unfortunately the ICLR registers are read-only, you can
 605          * only write ICLR_foo values to them.  To get the current
 606          * IRQ status you would need to get at the IRQ diag registers
 607          * in the PCI/SBUS controller and the layout of those vary
 608          * from one controller to the next, sigh... -DaveM
 609          */
 610         unsigned long iclr = bucket->iclr;
 611
 612         while (1) {
 613                 u32 tmp = upa_readl(iclr);
 614
 615                 if (tmp == ICLR_TRANSMIT ||
 616                     tmp == ICLR_PENDING) {
 617                         cpu_relax();
 618                         continue;
 619                 }
 620                 break;
 621         }
 622 #else
 623         /* So we have to do this with a INPROGRESS bit just like x86.  */
 624         while (bucket->flags & IBF_INPROGRESS)
 625                 cpu_relax();
 626 #endif
 627 }
 628 #endif /* CONFIG_SMP */
 629
 630 static void process_bucket(int irq, struct ino_bucket *bp, struct pt_regs *regs)
 631 {
 632         struct irq_desc *desc = bp->irq_info;
 633         unsigned char flags = bp->flags;
 634         u32 action_mask, i;
 635         int random;
 636
 637         bp->flags |= IBF_INPROGRESS;
 638
 639         if (unlikely(!(flags & IBF_ACTIVE))) {
 640                 bp->pending = 1;
 641                 goto out;
 642         }
 643
 644         if (desc->pre_handler)
 645                 desc->pre_handler(bp,
 646                                   desc->pre_handler_arg1,
 647                                   desc->pre_handler_arg2);
 648
 649         action_mask = desc->action_active_mask;
 650         random = 0;
 651         for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
 652                 struct irqaction *p = &desc->action[i];
 653                 u32 mask = (1 << i);
 654
 655                 if (!(action_mask & mask))
 656                         continue;
 657
 658                 action_mask &= ~mask;
 659
 660                 if (p->handler(__irq(bp), p->dev_id, regs) == IRQ_HANDLED)
 661                         random |= p->flags;
 662
 663                 if (!action_mask)
 664                         break;
 665         }
 666         if (bp->pil != 0) {
 667                 if (tlb_type == hypervisor) {
 668                         unsigned int ino = __irq_ino(bp);
 669                         int err;
 670
 671                         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 672                         if (err != HV_EOK)
 673                                 printk("sun4v_intr_setstate(%x): "
 674                                        "err(%d)\n", ino, err);
 675                 } else {
 676                         upa_writel(ICLR_IDLE, bp->iclr);
 677                 }
 678
 679                 /* Test and add entropy */
 680                 if (random & SA_SAMPLE_RANDOM)
 681                         add_interrupt_randomness(irq);
 682         }
 683 out:
 684         bp->flags &= ~IBF_INPROGRESS;
 685 }
 686
 687 void handler_irq(int irq, struct pt_regs *regs)
 688 {
 689         struct ino_bucket *bp;
 690         int cpu = smp_processor_id();
 691
 692 #ifndef CONFIG_SMP
 693         /*
 694          * Check for TICK_INT on level 14 softint.
 695          */
 696         {
 697                 unsigned long clr_mask = 1 << irq;
 698                 unsigned long tick_mask = tick_ops->softint_mask;
 699
 700                 if ((irq == 14) && (get_softint() & tick_mask)) {
 701                         irq = 0;
 702                         clr_mask = tick_mask;
 703                 }
 704                 clear_softint(clr_mask);
 705         }
 706 #else
 707         clear_softint(1 << irq);
 708 #endif
 709
 710         irq_enter();
 711         kstat_this_cpu.irqs[irq]++;
 712
 713         /* Sliiiick... */
 714 #ifndef CONFIG_SMP
 715         bp = ((irq != 0) ?
 716               __bucket(xchg32(irq_work(cpu, irq), 0)) :
 717               &pil0_dummy_bucket);
 718 #else
 719         bp = __bucket(xchg32(irq_work(cpu, irq), 0));
 720 #endif
 721         while (bp) {
 722                 struct ino_bucket *nbp = __bucket(bp->irq_chain);
 723
 724                 bp->irq_chain = 0;
 725                 process_bucket(irq, bp, regs);
 726                 bp = nbp;
 727         }
 728         irq_exit();
 729 }
 730
 731 #ifdef CONFIG_BLK_DEV_FD
 732 extern irqreturn_t floppy_interrupt(int, void *, struct pt_regs *);;
 733
 734 /* XXX No easy way to include asm/floppy.h XXX */
 735 extern unsigned char *pdma_vaddr;
 736 extern unsigned long pdma_size;
 737 extern volatile int doing_pdma;
 738 extern unsigned long fdc_status;
 739
 740 irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie, struct pt_regs *regs)
 741 {
 742         if (likely(doing_pdma)) {
 743                 void __iomem *stat = (void __iomem *) fdc_status;
 744                 unsigned char *vaddr = pdma_vaddr;
 745                 unsigned long size = pdma_size;
 746                 u8 val;
 747
 748                 while (size) {
 749                         val = readb(stat);
 750                         if (unlikely(!(val & 0x80))) {
 751                                 pdma_vaddr = vaddr;
 752                                 pdma_size = size;
 753                                 return IRQ_HANDLED;
 754                         }
 755                         if (unlikely(!(val & 0x20))) {
 756                                 pdma_vaddr = vaddr;
 757                                 pdma_size = size;
 758                                 doing_pdma = 0;
 759                                 goto main_interrupt;
 760                         }
 761                         if (val & 0x40) {
 762                                 /* read */
 763                                 *vaddr++ = readb(stat + 1);
 764                         } else {
 765                                 unsigned char data = *vaddr++;
 766
 767                                 /* write */
 768                                 writeb(data, stat + 1);
 769                         }
 770                         size--;
 771                 }
 772
 773                 pdma_vaddr = vaddr;
 774                 pdma_size = size;
 775
 776                 /* Send Terminal Count pulse to floppy controller. */
 777                 val = readb(auxio_register);
 778                 val |= AUXIO_AUX1_FTCNT;
 779                 writeb(val, auxio_register);
 780                 val &= ~AUXIO_AUX1_FTCNT;
 781                 writeb(val, auxio_register);
 782
 783                 doing_pdma = 0;
 784         }
 785
 786 main_interrupt:
 787         return floppy_interrupt(irq, dev_cookie, regs);
 788 }
 789 EXPORT_SYMBOL(sparc_floppy_irq);
 790 #endif
 791
 792 /* We really don't need these at all on the Sparc.  We only have
 793  * stubs here because they are exported to modules.
 794  */
 795 unsigned long probe_irq_on(void)
 796 {
 797         return 0;
 798 }
 799
 800 EXPORT_SYMBOL(probe_irq_on);
 801
 802 int probe_irq_off(unsigned long mask)
 803 {
 804         return 0;
 805 }
 806
 807 EXPORT_SYMBOL(probe_irq_off);
 808
 809 #ifdef CONFIG_SMP
 810 static int retarget_one_irq(struct irqaction *p, int goal_cpu)
 811 {
 812         struct ino_bucket *bucket = get_ino_in_irqaction(p) + ivector_table;
 813
 814         while (!cpu_online(goal_cpu)) {
 815                 if (++goal_cpu >= NR_CPUS)
 816                         goal_cpu = 0;
 817         }
 818
 819         if (tlb_type == hypervisor) {
 820                 unsigned int ino = __irq_ino(bucket);
 821
 822                 sun4v_intr_settarget(ino, goal_cpu);
 823                 sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
 824         } else {
 825                 unsigned long imap = bucket->imap;
 826                 unsigned int tid = sun4u_compute_tid(imap, goal_cpu);
 827
 828                 upa_writel(tid | IMAP_VALID, imap);
 829         }
 830
 831         do {
 832                 if (++goal_cpu >= NR_CPUS)
 833                         goal_cpu = 0;
 834         } while (!cpu_online(goal_cpu));
 835
 836         return goal_cpu;
 837 }
 838
 839 /* Called from request_irq. */
 840 static void distribute_irqs(void)
 841 {
 842         unsigned long flags;
 843         int cpu, level;
 844
 845         spin_lock_irqsave(&irq_action_lock, flags);
 846         cpu = 0;
 847
 848         /*
 849          * Skip the timer at [0], and very rare error/power intrs at [15].
 850          * Also level [12], it causes problems on Ex000 systems.
 851          */
 852         for (level = 1; level < NR_IRQS; level++) {
 853                 struct irqaction *p = irq_action[level];
 854
 855                 if (level == 12)
 856                         continue;
 857
 858                 while(p) {
 859                         cpu = retarget_one_irq(p, cpu);
 860                         p = p->next;
 861                 }
 862         }
 863         spin_unlock_irqrestore(&irq_action_lock, flags);
 864 }
 865 #endif
 866
 867 struct sun5_timer {
 868         u64     count0;
 869         u64     limit0;
 870         u64     count1;
 871         u64     limit1;
 872 };
 873
 874 static struct sun5_timer *prom_timers;
 875 static u64 prom_limit0, prom_limit1;
 876
 877 static void map_prom_timers(void)
 878 {
 879         unsigned int addr[3];
 880         int tnode, err;
 881
 882         /* PROM timer node hangs out in the top level of device siblings... */
 883         tnode = prom_finddevice("/counter-timer");
 884
 885         /* Assume if node is not present, PROM uses different tick mechanism
 886          * which we should not care about.
 887          */
 888         if (tnode == 0 || tnode == -1) {
 889                 prom_timers = (struct sun5_timer *) 0;
 890                 return;
 891         }
 892
 893         /* If PROM is really using this, it must be mapped by him. */
 894         err = prom_getproperty(tnode, "address", (char *)addr, sizeof(addr));
 895         if (err == -1) {
 896                 prom_printf("PROM does not have timer mapped, trying to continue.\n");
 897                 prom_timers = (struct sun5_timer *) 0;
 898                 return;
 899         }
 900         prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
 901 }
 902
 903 static void kill_prom_timer(void)
 904 {
 905         if (!prom_timers)
 906                 return;
 907
 908         /* Save them away for later. */
 909         prom_limit0 = prom_timers->limit0;
 910         prom_limit1 = prom_timers->limit1;
 911
 912         /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
 913          * We turn both off here just to be paranoid.
 914          */
 915         prom_timers->limit0 = 0;
 916         prom_timers->limit1 = 0;
 917
 918         /* Wheee, eat the interrupt packet too... */
 919         __asm__ __volatile__(
 920 "       mov     0x40, %%g2\n"
 921 "       ldxa    [%%g0] %0, %%g1\n"
 922 "       ldxa    [%%g2] %1, %%g1\n"
 923 "       stxa    %%g0, [%%g0] %0\n"
 924 "       membar  #Sync\n"
 925         : /* no outputs */
 926         : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
 927         : "g1", "g2");
 928 }
 929
 930 void init_irqwork_curcpu(void)
 931 {
 932         int cpu = hard_smp_processor_id();
 933
 934         memset(__irq_work + cpu, 0, sizeof(struct irq_work_struct));
 935 }
 936
 937 static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type)
 938 {
 939         unsigned long num_entries = 128;
 940         unsigned long status;
 941
 942         status = sun4v_cpu_qconf(type, paddr, num_entries);
 943         if (status != HV_EOK) {
 944                 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
 945                             "err %lu\n", type, paddr, num_entries, status);
 946                 prom_halt();
 947         }
 948 }
 949
 950 static void __cpuinit sun4v_register_mondo_queues(int this_cpu)
 951 {
 952         struct trap_per_cpu *tb = &trap_block[this_cpu];
 953
 954         register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO);
 955         register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO);
 956         register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR);
 957         register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR);
 958 }
 959
 960 static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, int use_bootmem)
 961 {
 962         void *page;
 963
 964         if (use_bootmem)
 965                 page = alloc_bootmem_low_pages(PAGE_SIZE);
 966         else
 967                 page = (void *) get_zeroed_page(GFP_ATOMIC);
 968
 969         if (!page) {
 970                 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
 971                 prom_halt();
 972         }
 973
 974         *pa_ptr = __pa(page);
 975 }
 976
 977 static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, int use_bootmem)
 978 {
 979         void *page;
 980
 981         if (use_bootmem)
 982                 page = alloc_bootmem_low_pages(PAGE_SIZE);
 983         else
 984                 page = (void *) get_zeroed_page(GFP_ATOMIC);
 985
 986         if (!page) {
 987                 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
 988                 prom_halt();
 989         }
 990
 991         *pa_ptr = __pa(page);
 992 }
 993
 994 static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem)
 995 {
 996 #ifdef CONFIG_SMP
 997         void *page;
 998
 999         BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
1000
1001         if (use_bootmem)
1002                 page = alloc_bootmem_low_pages(PAGE_SIZE);
1003         else
1004                 page = (void *) get_zeroed_page(GFP_ATOMIC);
1005
1006         if (!page) {
1007                 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
1008                 prom_halt();
1009         }
1010
1011         tb->cpu_mondo_block_pa = __pa(page);
1012         tb->cpu_list_pa = __pa(page + 64);
1013 #endif
1014 }
1015
1016 /* Allocate and register the mondo and error queues for this cpu.  */
1017 void __cpuinit sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load)
1018 {
1019         struct trap_per_cpu *tb = &trap_block[cpu];
1020
1021         if (alloc) {
1022                 alloc_one_mondo(&tb->cpu_mondo_pa, use_bootmem);
1023                 alloc_one_mondo(&tb->dev_mondo_pa, use_bootmem);
1024                 alloc_one_mondo(&tb->resum_mondo_pa, use_bootmem);
1025                 alloc_one_kbuf(&tb->resum_kernel_buf_pa, use_bootmem);
1026                 alloc_one_mondo(&tb->nonresum_mondo_pa, use_bootmem);
1027                 alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, use_bootmem);
1028
1029                 init_cpu_send_mondo_info(tb, use_bootmem);
1030         }
1031
1032         if (load) {
1033                 if (cpu != hard_smp_processor_id()) {
1034                         prom_printf("SUN4V: init mondo on cpu %d not %d\n",
1035                                     cpu, hard_smp_processor_id());
1036                         prom_halt();
1037                 }
1038                 sun4v_register_mondo_queues(cpu);
1039         }
1040 }
1041
1042 /* Only invoked on boot processor. */
1043 void __init init_IRQ(void)
1044 {
1045         map_prom_timers();
1046         kill_prom_timer();
1047         memset(&ivector_table[0], 0, sizeof(ivector_table));
1048
1049         if (tlb_type == hypervisor)
1050                 sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1);
1051
1052         /* We need to clear any IRQ's pending in the soft interrupt
1053          * registers, a spurious one could be left around from the
1054          * PROM timer which we just disabled.
1055          */
1056         clear_softint(get_softint());
1057
1058         /* Now that ivector table is initialized, it is safe
1059          * to receive IRQ vector traps.  We will normally take
1060          * one or two right now, in case some device PROM used
1061          * to boot us wants to speak to us.  We just ignore them.
1062          */
1063         __asm__ __volatile__("rdpr      %%pstate, %%g1\n\t"
1064                              "or        %%g1, %0, %%g1\n\t"
1065                              "wrpr      %%g1, 0x0, %%pstate"
1066                              : /* No outputs */
1067                              : "i" (PSTATE_IE)
1068                              : "g1");
1069 }
1070
1071 static struct proc_dir_entry * root_irq_dir;
1072 static struct proc_dir_entry * irq_dir [NUM_IVECS];
1073
1074 #ifdef CONFIG_SMP
1075
1076 static int irq_affinity_read_proc (char *page, char **start, off_t off,
1077                         int count, int *eof, void *data)
1078 {
1079         struct ino_bucket *bp = ivector_table + (long)data;
1080         struct irq_desc *desc = bp->irq_info;
1081         struct irqaction *ap = desc->action;
1082         cpumask_t mask;
1083         int len;
1084
1085         mask = get_smpaff_in_irqaction(ap);
1086         if (cpus_empty(mask))
1087                 mask = cpu_online_map;
1088
1089         len = cpumask_scnprintf(page, count, mask);
1090         if (count - len < 2)
1091                 return -EINVAL;
1092         len += sprintf(page + len, "\n");
1093         return len;
1094 }
1095
1096 static inline void set_intr_affinity(int irq, cpumask_t hw_aff)
1097 {
1098         struct ino_bucket *bp = ivector_table + irq;
1099         struct irq_desc *desc = bp->irq_info;
1100         struct irqaction *ap = desc->action;
1101
1102         /* Users specify affinity in terms of hw cpu ids.
1103          * As soon as we do this, handler_irq() might see and take action.
1104          */
1105         put_smpaff_in_irqaction(ap, hw_aff);
1106
1107         /* Migration is simply done by the next cpu to service this
1108          * interrupt.
1109          */
1110 }
1111
1112 static int irq_affinity_write_proc (struct file *file, const char __user *buffer,
1113                                         unsigned long count, void *data)
1114 {
1115         int irq = (long) data, full_count = count, err;
1116         cpumask_t new_value;
1117
1118         err = cpumask_parse(buffer, count, new_value);
1119
1120         /*
1121          * Do not allow disabling IRQs completely - it's a too easy
1122          * way to make the system unusable accidentally :-) At least
1123          * one online CPU still has to be targeted.
1124          */
1125         cpus_and(new_value, new_value, cpu_online_map);
1126         if (cpus_empty(new_value))
1127                 return -EINVAL;
1128
1129         set_intr_affinity(irq, new_value);
1130
1131         return full_count;
1132 }
1133
1134 #endif
1135
1136 #define MAX_NAMELEN 10
1137
1138 static void register_irq_proc (unsigned int irq)
1139 {
1140         char name [MAX_NAMELEN];
1141
1142         if (!root_irq_dir || irq_dir[irq])
1143                 return;
1144
1145         memset(name, 0, MAX_NAMELEN);
1146         sprintf(name, "%x", irq);
1147
1148         /* create /proc/irq/1234 */
1149         irq_dir[irq] = proc_mkdir(name, root_irq_dir);
1150
1151 #ifdef CONFIG_SMP
1152         /* XXX SMP affinity not supported on starfire yet. */
1153         if (this_is_starfire == 0) {
1154                 struct proc_dir_entry *entry;
1155
1156                 /* create /proc/irq/1234/smp_affinity */
1157                 entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]);
1158
1159                 if (entry) {
1160                         entry->nlink = 1;
1161                         entry->data = (void *)(long)irq;
1162                         entry->read_proc = irq_affinity_read_proc;
1163                         entry->write_proc = irq_affinity_write_proc;
1164                 }
1165         }
1166 #endif
1167 }
1168
1169 void init_irq_proc (void)
1170 {
1171         /* create /proc/irq */
1172         root_irq_dir = proc_mkdir("irq", NULL);
1173 }
1174