2 * SS1000/SC2000 interrupt handling.
4 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
5 * Heavily based on arch/sparc/kernel/irq.c.
8 #include <linux/kernel_stat.h>
9 #include <linux/seq_file.h>
11 #include <asm/timer.h>
12 #include <asm/traps.h>
16 #include <asm/cacheflush.h>
17 #include <asm/setup.h>
22 /* Sun4d interrupts fall roughly into two categories. SBUS and
23 * cpu local. CPU local interrupts cover the timer interrupts
24 * and whatnot, and we encode those as normal PILs between
26 * SBUS interrupts are encodes as a combination of board, level and slot.
29 struct sun4d_handler_data {
30 unsigned int cpuid; /* target cpu */
31 unsigned int real_irq; /* interrupt level */
35 static unsigned int sun4d_encode_irq(int board, int lvl, int slot)
37 return (board + 1) << 5 | (lvl << 2) | slot;
40 struct sun4d_timer_regs {
43 u32 l10_limit_noclear;
48 static struct sun4d_timer_regs __iomem *sun4d_timers;
50 #define SUN4D_TIMER_IRQ 10
52 /* Specify which cpu handle interrupts from which board.
53 * Index is board - value is cpu.
55 static unsigned char board_to_cpu[32];
57 static int pil_to_sbus[] = {
76 /* Exported for sun4d_smp.c */
77 DEFINE_SPINLOCK(sun4d_imsk_lock);
79 /* SBUS interrupts are encoded integers including the board number
80 * (plus one), the SBUS level, and the SBUS slot number. Sun4D
81 * IRQ dispatch is done by:
83 * 1) Reading the BW local interrupt table in order to get the bus
86 * This table is indexed by SBUS interrupt level which can be
87 * derived from the PIL we got interrupted on.
89 * 2) For each bus showing interrupt pending from #1, read the
90 * SBI interrupt state register. This will indicate which slots
91 * have interrupts pending for that SBUS interrupt level.
93 * 3) Call the genreric IRQ support.
95 static void sun4d_sbus_handler_irq(int sbusl)
97 unsigned int bus_mask;
98 unsigned int sbino, slot;
101 bus_mask = bw_get_intr_mask(sbusl) & 0x3ffff;
102 bw_clear_intr_mask(sbusl, bus_mask);
105 /* Loop for each pending SBI */
106 for (sbino = 0; bus_mask; sbino++, bus_mask >>= 1) {
107 unsigned int idx, mask;
111 /* XXX This seems to ACK the irq twice. acquire_sbi()
112 * XXX uses swap, therefore this writes 0xf << sbil,
113 * XXX then later release_sbi() will write the individual
114 * XXX bits which were set again.
116 mask = acquire_sbi(SBI2DEVID(sbino), 0xf << sbil);
117 mask &= (0xf << sbil);
119 /* Loop for each pending SBI slot */
121 for (idx = 0; mask != 0; idx++, slot <<= 1) {
123 struct irq_bucket *p;
129 pil = sun4d_encode_irq(sbino, sbusl, idx);
133 struct irq_bucket *next;
136 generic_handle_irq(p->irq);
139 release_sbi(SBI2DEVID(sbino), slot);
144 void sun4d_handler_irq(int pil, struct pt_regs *regs)
146 struct pt_regs *old_regs;
147 /* SBUS IRQ level (1 - 7) */
148 int sbusl = pil_to_sbus[pil];
150 /* FIXME: Is this necessary?? */
153 cc_set_iclr(1 << pil);
157 * Check IPI data structures after IRQ has been cleared. Hard and Soft
158 * IRQ can happen at the same time, so both cases are always handled.
160 if (pil == SUN4D_IPI_IRQ)
161 sun4d_ipi_interrupt();
164 old_regs = set_irq_regs(regs);
168 struct irq_bucket *p;
172 struct irq_bucket *next;
175 generic_handle_irq(p->irq);
180 sun4d_sbus_handler_irq(sbusl);
183 set_irq_regs(old_regs);
187 static void sun4d_mask_irq(struct irq_data *data)
189 struct sun4d_handler_data *handler_data = data->handler_data;
190 unsigned int real_irq;
192 int cpuid = handler_data->cpuid;
195 real_irq = handler_data->real_irq;
197 spin_lock_irqsave(&sun4d_imsk_lock, flags);
198 cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) | (1 << real_irq));
199 spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
201 cc_set_imsk(cc_get_imsk() | (1 << real_irq));
205 static void sun4d_unmask_irq(struct irq_data *data)
207 struct sun4d_handler_data *handler_data = data->handler_data;
208 unsigned int real_irq;
210 int cpuid = handler_data->cpuid;
213 real_irq = handler_data->real_irq;
216 spin_lock_irqsave(&sun4d_imsk_lock, flags);
217 cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) & ~(1 << real_irq));
218 spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
220 cc_set_imsk(cc_get_imsk() & ~(1 << real_irq));
224 static unsigned int sun4d_startup_irq(struct irq_data *data)
227 sun4d_unmask_irq(data);
231 static void sun4d_shutdown_irq(struct irq_data *data)
233 sun4d_mask_irq(data);
234 irq_unlink(data->irq);
237 struct irq_chip sun4d_irq = {
239 .irq_startup = sun4d_startup_irq,
240 .irq_shutdown = sun4d_shutdown_irq,
241 .irq_unmask = sun4d_unmask_irq,
242 .irq_mask = sun4d_mask_irq,
246 static void sun4d_set_cpu_int(int cpu, int level)
248 sun4d_send_ipi(cpu, level);
251 static void sun4d_clear_ipi(int cpu, int level)
255 static void sun4d_set_udt(int cpu)
259 /* Setup IRQ distribution scheme. */
260 void __init sun4d_distribute_irqs(void)
262 struct device_node *dp;
264 int cpuid = cpu_logical_map(1);
267 cpuid = cpu_logical_map(0);
268 for_each_node_by_name(dp, "sbi") {
269 int devid = of_getintprop_default(dp, "device-id", 0);
270 int board = of_getintprop_default(dp, "board#", 0);
271 board_to_cpu[board] = cpuid;
272 set_sbi_tid(devid, cpuid << 3);
274 printk(KERN_ERR "All sbus IRQs directed to CPU%d\n", cpuid);
278 static void sun4d_clear_clock_irq(void)
280 sbus_readl(&sun4d_timers->l10_timer_limit);
283 static void sun4d_load_profile_irq(int cpu, unsigned int limit)
285 bw_set_prof_limit(cpu, limit);
288 static void __init sun4d_load_profile_irqs(void)
292 while (!cpu_find_by_instance(cpu, NULL, &mid)) {
293 sun4d_load_profile_irq(mid >> 3, 0);
298 unsigned int _sun4d_build_device_irq(unsigned int real_irq,
302 struct sun4d_handler_data *handler_data;
305 irq = irq_alloc(real_irq, pil);
307 prom_printf("IRQ: allocate for %d %d %d failed\n",
308 real_irq, pil, board);
312 handler_data = irq_get_handler_data(irq);
313 if (unlikely(handler_data))
316 handler_data = kzalloc(sizeof(struct sun4d_handler_data), GFP_ATOMIC);
317 if (unlikely(!handler_data)) {
318 prom_printf("IRQ: kzalloc(sun4d_handler_data) failed.\n");
321 handler_data->cpuid = board_to_cpu[board];
322 handler_data->real_irq = real_irq;
323 irq_set_chip_and_handler_name(irq, &sun4d_irq,
324 handle_level_irq, "level");
325 irq_set_handler_data(irq, handler_data);
333 unsigned int sun4d_build_device_irq(struct platform_device *op,
334 unsigned int real_irq)
336 struct device_node *dp = op->dev.of_node;
337 struct device_node *io_unit, *sbi = dp->parent;
338 const struct linux_prom_registers *regs;
346 if (!strcmp(sbi->name, "sbi"))
354 regs = of_get_property(dp, "reg", NULL);
358 slot = regs->which_io;
361 * If SBI's parent is not io-unit or the io-unit lacks
362 * a "board#" property, something is very wrong.
364 if (!sbi->parent || strcmp(sbi->parent->name, "io-unit")) {
365 printk("%s: Error, parent is not io-unit.\n", sbi->full_name);
368 io_unit = sbi->parent;
369 board = of_getintprop_default(io_unit, "board#", -1);
371 printk("%s: Error, lacks board# property.\n", io_unit->full_name);
375 sbusl = pil_to_sbus[real_irq];
377 pil = sun4d_encode_irq(board, sbusl, slot);
381 irq = _sun4d_build_device_irq(real_irq, pil, board);
386 unsigned int sun4d_build_timer_irq(unsigned int board, unsigned int real_irq)
388 return _sun4d_build_device_irq(real_irq, real_irq, board);
392 static void __init sun4d_fixup_trap_table(void)
396 struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
398 /* Adjust so that we jump directly to smp4d_ticker */
399 lvl14_save[2] += smp4d_ticker - real_irq_entry;
401 /* For SMP we use the level 14 ticker, however the bootup code
402 * has copied the firmware's level 14 vector into the boot cpu's
403 * trap table, we must fix this now or we get squashed.
405 local_irq_save(flags);
406 patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */
407 trap_table->inst_one = lvl14_save[0];
408 trap_table->inst_two = lvl14_save[1];
409 trap_table->inst_three = lvl14_save[2];
410 trap_table->inst_four = lvl14_save[3];
411 local_flush_cache_all();
412 local_irq_restore(flags);
416 static void __init sun4d_init_timers(irq_handler_t counter_fn)
418 struct device_node *dp;
425 dp = of_find_node_by_name(NULL, "cpu-unit");
427 prom_printf("sun4d_init_timers: Unable to find cpu-unit\n");
431 /* Which cpu-unit we use is arbitrary, we can view the bootbus timer
432 * registers via any cpu's mapping. The first 'reg' property is the
435 reg = of_get_property(dp, "reg", NULL);
437 prom_printf("sun4d_init_timers: No reg property\n");
441 board = of_getintprop_default(dp, "board#", -1);
443 prom_printf("sun4d_init_timers: No board# property on cpu-unit\n");
450 res.end = reg[2] - 1;
451 res.flags = reg[0] & 0xff;
452 sun4d_timers = of_ioremap(&res, BW_TIMER_LIMIT,
453 sizeof(struct sun4d_timer_regs), "user timer");
455 prom_printf("sun4d_init_timers: Can't map timer regs\n");
459 sbus_writel((((1000000/HZ) + 1) << 10), &sun4d_timers->l10_timer_limit);
461 master_l10_counter = &sun4d_timers->l10_cur_count;
463 irq = sun4d_build_timer_irq(board, SUN4D_TIMER_IRQ);
464 err = request_irq(irq, counter_fn, IRQF_TIMER, "timer", NULL);
466 prom_printf("sun4d_init_timers: request_irq() failed with %d\n",
470 sun4d_load_profile_irqs();
471 sun4d_fixup_trap_table();
474 void __init sun4d_init_sbi_irq(void)
476 struct device_node *dp;
479 target_cpu = boot_cpu_id;
480 for_each_node_by_name(dp, "sbi") {
481 int devid = of_getintprop_default(dp, "device-id", 0);
482 int board = of_getintprop_default(dp, "board#", 0);
485 set_sbi_tid(devid, target_cpu << 3);
486 board_to_cpu[board] = target_cpu;
488 /* Get rid of pending irqs from PROM */
489 mask = acquire_sbi(devid, 0xffffffff);
491 printk(KERN_ERR "Clearing pending IRQs %08x on SBI %d\n",
493 release_sbi(devid, mask);
498 void __init sun4d_init_IRQ(void)
502 BTFIXUPSET_CALL(clear_clock_irq, sun4d_clear_clock_irq, BTFIXUPCALL_NORM);
503 BTFIXUPSET_CALL(load_profile_irq, sun4d_load_profile_irq, BTFIXUPCALL_NORM);
505 sparc_irq_config.init_timers = sun4d_init_timers;
506 sparc_irq_config.build_device_irq = sun4d_build_device_irq;
509 BTFIXUPSET_CALL(set_cpu_int, sun4d_set_cpu_int, BTFIXUPCALL_NORM);
510 BTFIXUPSET_CALL(clear_cpu_int, sun4d_clear_ipi, BTFIXUPCALL_NOP);
511 BTFIXUPSET_CALL(set_irq_udt, sun4d_set_udt, BTFIXUPCALL_NOP);
513 /* Cannot enable interrupts until OBP ticker is disabled. */