arch/sparc/kernel/irq_64.c

   1 /* irq.c: UltraSparc IRQ handling/init/registry.
   2  *
   3  * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  * Copyright (C) 1998  Eddie C. Dost    (ecd@skynet.be)
   5  * Copyright (C) 1998  Jakub Jelinek    (jj@ultra.linux.cz)
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/sched.h>
  10 #include <linux/linkage.h>
  11 #include <linux/ptrace.h>
  12 #include <linux/errno.h>
  13 #include <linux/kernel_stat.h>
  14 #include <linux/signal.h>
  15 #include <linux/mm.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/slab.h>
  18 #include <linux/random.h>
  19 #include <linux/init.h>
  20 #include <linux/delay.h>
  21 #include <linux/proc_fs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/ftrace.h>
  24 #include <linux/irq.h>
  25 #include <linux/kmemleak.h>
  26
  27 #include <asm/ptrace.h>
  28 #include <asm/processor.h>
  29 #include <asm/atomic.h>
  30 #include <asm/system.h>
  31 #include <asm/irq.h>
  32 #include <asm/io.h>
  33 #include <asm/iommu.h>
  34 #include <asm/upa.h>
  35 #include <asm/oplib.h>
  36 #include <asm/prom.h>
  37 #include <asm/timer.h>
  38 #include <asm/smp.h>
  39 #include <asm/starfire.h>
  40 #include <asm/uaccess.h>
  41 #include <asm/cache.h>
  42 #include <asm/cpudata.h>
  43 #include <asm/auxio.h>
  44 #include <asm/head.h>
  45 #include <asm/hypervisor.h>
  46 #include <asm/cacheflush.h>
  47
  48 #include "entry.h"
  49 #include "cpumap.h"
  50 #include "kstack.h"
  51
  52 #define NUM_IVECS       (IMAP_INR + 1)
  53
  54 struct ino_bucket *ivector_table;
  55 unsigned long ivector_table_pa;
  56
  57 /* On several sun4u processors, it is illegal to mix bypass and
  58  * non-bypass accesses.  Therefore we access all INO buckets
  59  * using bypass accesses only.
  60  */
  61 static unsigned long bucket_get_chain_pa(unsigned long bucket_pa)
  62 {
  63         unsigned long ret;
  64
  65         __asm__ __volatile__("ldxa      [%1] %2, %0"
  66                              : "=&r" (ret)
  67                              : "r" (bucket_pa +
  68                                     offsetof(struct ino_bucket,
  69                                              __irq_chain_pa)),
  70                                "i" (ASI_PHYS_USE_EC));
  71
  72         return ret;
  73 }
  74
  75 static void bucket_clear_chain_pa(unsigned long bucket_pa)
  76 {
  77         __asm__ __volatile__("stxa      %%g0, [%0] %1"
  78                              : /* no outputs */
  79                              : "r" (bucket_pa +
  80                                     offsetof(struct ino_bucket,
  81                                              __irq_chain_pa)),
  82                                "i" (ASI_PHYS_USE_EC));
  83 }
  84
  85 static unsigned int bucket_get_irq(unsigned long bucket_pa)
  86 {
  87         unsigned int ret;
  88
  89         __asm__ __volatile__("lduwa     [%1] %2, %0"
  90                              : "=&r" (ret)
  91                              : "r" (bucket_pa +
  92                                     offsetof(struct ino_bucket,
  93                                              __irq)),
  94                                "i" (ASI_PHYS_USE_EC));
  95
  96         return ret;
  97 }
  98
  99 static void bucket_set_irq(unsigned long bucket_pa, unsigned int irq)
 100 {
 101         __asm__ __volatile__("stwa      %0, [%1] %2"
 102                              : /* no outputs */
 103                              : "r" (irq),
 104                                "r" (bucket_pa +
 105                                     offsetof(struct ino_bucket,
 106                                              __irq)),
 107                                "i" (ASI_PHYS_USE_EC));
 108 }
 109
 110 #define irq_work_pa(__cpu)      &(trap_block[(__cpu)].irq_worklist_pa)
 111
 112 static struct {
 113         unsigned int dev_handle;
 114         unsigned int dev_ino;
 115         unsigned int in_use;
 116 } irq_table[NR_IRQS];
 117 static DEFINE_SPINLOCK(irq_alloc_lock);
 118
 119 unsigned char irq_alloc(unsigned int dev_handle, unsigned int dev_ino)
 120 {
 121         unsigned long flags;
 122         unsigned char ent;
 123
 124         BUILD_BUG_ON(NR_IRQS >= 256);
 125
 126         spin_lock_irqsave(&irq_alloc_lock, flags);
 127
 128         for (ent = 1; ent < NR_IRQS; ent++) {
 129                 if (!irq_table[ent].in_use)
 130                         break;
 131         }
 132         if (ent >= NR_IRQS) {
 133                 printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
 134                 ent = 0;
 135         } else {
 136                 irq_table[ent].dev_handle = dev_handle;
 137                 irq_table[ent].dev_ino = dev_ino;
 138                 irq_table[ent].in_use = 1;
 139         }
 140
 141         spin_unlock_irqrestore(&irq_alloc_lock, flags);
 142
 143         return ent;
 144 }
 145
 146 #ifdef CONFIG_PCI_MSI
 147 void irq_free(unsigned int irq)
 148 {
 149         unsigned long flags;
 150
 151         if (irq >= NR_IRQS)
 152                 return;
 153
 154         spin_lock_irqsave(&irq_alloc_lock, flags);
 155
 156         irq_table[irq].in_use = 0;
 157
 158         spin_unlock_irqrestore(&irq_alloc_lock, flags);
 159 }
 160 #endif
 161
 162 /*
 163  * /proc/interrupts printing:
 164  */
 165
 166 int show_interrupts(struct seq_file *p, void *v)
 167 {
 168         int i = *(loff_t *) v, j;
 169         struct irqaction * action;
 170         unsigned long flags;
 171
 172         if (i == 0) {
 173                 seq_printf(p, "           ");
 174                 for_each_online_cpu(j)
 175                         seq_printf(p, "CPU%d       ",j);
 176                 seq_putc(p, '\n');
 177         }
 178
 179         if (i < NR_IRQS) {
 180                 raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
 181                 action = irq_desc[i].action;
 182                 if (!action)
 183                         goto skip;
 184                 seq_printf(p, "%3d: ",i);
 185 #ifndef CONFIG_SMP
 186                 seq_printf(p, "%10u ", kstat_irqs(i));
 187 #else
 188                 for_each_online_cpu(j)
 189                         seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
 190 #endif
 191                 seq_printf(p, " %9s", irq_desc[i].irq_data.chip->name);
 192                 seq_printf(p, "  %s", action->name);
 193
 194                 for (action=action->next; action; action = action->next)
 195                         seq_printf(p, ", %s", action->name);
 196
 197                 seq_putc(p, '\n');
 198 skip:
 199                 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
 200         } else if (i == NR_IRQS) {
 201                 seq_printf(p, "NMI: ");
 202                 for_each_online_cpu(j)
 203                         seq_printf(p, "%10u ", cpu_data(j).__nmi_count);
 204                 seq_printf(p, "     Non-maskable interrupts\n");
 205         }
 206         return 0;
 207 }
 208
 209 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
 210 {
 211         unsigned int tid;
 212
 213         if (this_is_starfire) {
 214                 tid = starfire_translate(imap, cpuid);
 215                 tid <<= IMAP_TID_SHIFT;
 216                 tid &= IMAP_TID_UPA;
 217         } else {
 218                 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 219                         unsigned long ver;
 220
 221                         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 222                         if ((ver >> 32UL) == __JALAPENO_ID ||
 223                             (ver >> 32UL) == __SERRANO_ID) {
 224                                 tid = cpuid << IMAP_TID_SHIFT;
 225                                 tid &= IMAP_TID_JBUS;
 226                         } else {
 227                                 unsigned int a = cpuid & 0x1f;
 228                                 unsigned int n = (cpuid >> 5) & 0x1f;
 229
 230                                 tid = ((a << IMAP_AID_SHIFT) |
 231                                        (n << IMAP_NID_SHIFT));
 232                                 tid &= (IMAP_AID_SAFARI |
 233                                         IMAP_NID_SAFARI);
 234                         }
 235                 } else {
 236                         tid = cpuid << IMAP_TID_SHIFT;
 237                         tid &= IMAP_TID_UPA;
 238                 }
 239         }
 240
 241         return tid;
 242 }
 243
 244 struct irq_handler_data {
 245         unsigned long   iclr;
 246         unsigned long   imap;
 247
 248         void            (*pre_handler)(unsigned int, void *, void *);
 249         void            *arg1;
 250         void            *arg2;
 251 };
 252
 253 #ifdef CONFIG_SMP
 254 static int irq_choose_cpu(unsigned int irq, const struct cpumask *affinity)
 255 {
 256         cpumask_t mask;
 257         int cpuid;
 258
 259         cpumask_copy(&mask, affinity);
 260         if (cpus_equal(mask, cpu_online_map)) {
 261                 cpuid = map_to_cpu(irq);
 262         } else {
 263                 cpumask_t tmp;
 264
 265                 cpus_and(tmp, cpu_online_map, mask);
 266                 cpuid = cpus_empty(tmp) ? map_to_cpu(irq) : first_cpu(tmp);
 267         }
 268
 269         return cpuid;
 270 }
 271 #else
 272 #define irq_choose_cpu(irq, affinity)   \
 273         real_hard_smp_processor_id()
 274 #endif
 275
 276 static void sun4u_irq_enable(struct irq_data *data)
 277 {
 278         struct irq_handler_data *handler_data = data->handler_data;
 279
 280         if (likely(handler_data)) {
 281                 unsigned long cpuid, imap, val;
 282                 unsigned int tid;
 283
 284                 cpuid = irq_choose_cpu(data->irq, data->affinity);
 285                 imap = handler_data->imap;
 286
 287                 tid = sun4u_compute_tid(imap, cpuid);
 288
 289                 val = upa_readq(imap);
 290                 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
 291                          IMAP_AID_SAFARI | IMAP_NID_SAFARI);
 292                 val |= tid | IMAP_VALID;
 293                 upa_writeq(val, imap);
 294                 upa_writeq(ICLR_IDLE, handler_data->iclr);
 295         }
 296 }
 297
 298 static int sun4u_set_affinity(struct irq_data *data,
 299                                const struct cpumask *mask, bool force)
 300 {
 301         struct irq_handler_data *handler_data = data->handler_data;
 302
 303         if (likely(handler_data)) {
 304                 unsigned long cpuid, imap, val;
 305                 unsigned int tid;
 306
 307                 cpuid = irq_choose_cpu(data->irq, mask);
 308                 imap = handler_data->imap;
 309
 310                 tid = sun4u_compute_tid(imap, cpuid);
 311
 312                 val = upa_readq(imap);
 313                 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
 314                          IMAP_AID_SAFARI | IMAP_NID_SAFARI);
 315                 val |= tid | IMAP_VALID;
 316                 upa_writeq(val, imap);
 317                 upa_writeq(ICLR_IDLE, handler_data->iclr);
 318         }
 319
 320         return 0;
 321 }
 322
 323 /* Don't do anything.  The desc->status check for IRQ_DISABLED in
 324  * handler_irq() will skip the handler call and that will leave the
 325  * interrupt in the sent state.  The next ->enable() call will hit the
 326  * ICLR register to reset the state machine.
 327  *
 328  * This scheme is necessary, instead of clearing the Valid bit in the
 329  * IMAP register, to handle the case of IMAP registers being shared by
 330  * multiple INOs (and thus ICLR registers).  Since we use a different
 331  * virtual IRQ for each shared IMAP instance, the generic code thinks
 332  * there is only one user so it prematurely calls ->disable() on
 333  * free_irq().
 334  *
 335  * We have to provide an explicit ->disable() method instead of using
 336  * NULL to get the default.  The reason is that if the generic code
 337  * sees that, it also hooks up a default ->shutdown method which
 338  * invokes ->mask() which we do not want.  See irq_chip_set_defaults().
 339  */
 340 static void sun4u_irq_disable(struct irq_data *data)
 341 {
 342 }
 343
 344 static void sun4u_irq_eoi(struct irq_data *data)
 345 {
 346         struct irq_handler_data *handler_data = data->handler_data;
 347         struct irq_desc *desc = irq_desc + data->irq;
 348
 349         if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 350                 return;
 351
 352         if (likely(handler_data))
 353                 upa_writeq(ICLR_IDLE, handler_data->iclr);
 354 }
 355
 356 static void sun4v_irq_enable(struct irq_data *data)
 357 {
 358         unsigned int ino = irq_table[data->irq].dev_ino;
 359         unsigned long cpuid = irq_choose_cpu(data->irq, data->affinity);
 360         int err;
 361
 362         err = sun4v_intr_settarget(ino, cpuid);
 363         if (err != HV_EOK)
 364                 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
 365                        "err(%d)\n", ino, cpuid, err);
 366         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 367         if (err != HV_EOK)
 368                 printk(KERN_ERR "sun4v_intr_setstate(%x): "
 369                        "err(%d)\n", ino, err);
 370         err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
 371         if (err != HV_EOK)
 372                 printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n",
 373                        ino, err);
 374 }
 375
 376 static int sun4v_set_affinity(struct irq_data *data,
 377                                const struct cpumask *mask, bool force)
 378 {
 379         unsigned int ino = irq_table[data->irq].dev_ino;
 380         unsigned long cpuid = irq_choose_cpu(data->irq, mask);
 381         int err;
 382
 383         err = sun4v_intr_settarget(ino, cpuid);
 384         if (err != HV_EOK)
 385                 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
 386                        "err(%d)\n", ino, cpuid, err);
 387
 388         return 0;
 389 }
 390
 391 static void sun4v_irq_disable(struct irq_data *data)
 392 {
 393         unsigned int ino = irq_table[data->irq].dev_ino;
 394         int err;
 395
 396         err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
 397         if (err != HV_EOK)
 398                 printk(KERN_ERR "sun4v_intr_setenabled(%x): "
 399                        "err(%d)\n", ino, err);
 400 }
 401
 402 static void sun4v_irq_eoi(struct irq_data *data)
 403 {
 404         unsigned int ino = irq_table[data->irq].dev_ino;
 405         struct irq_desc *desc = irq_desc + data->irq;
 406         int err;
 407
 408         if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 409                 return;
 410
 411         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 412         if (err != HV_EOK)
 413                 printk(KERN_ERR "sun4v_intr_setstate(%x): "
 414                        "err(%d)\n", ino, err);
 415 }
 416
 417 static void sun4v_virq_enable(struct irq_data *data)
 418 {
 419         unsigned long cpuid, dev_handle, dev_ino;
 420         int err;
 421
 422         cpuid = irq_choose_cpu(data->irq, data->affinity);
 423
 424         dev_handle = irq_table[data->irq].dev_handle;
 425         dev_ino = irq_table[data->irq].dev_ino;
 426
 427         err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
 428         if (err != HV_EOK)
 429                 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
 430                        "err(%d)\n",
 431                        dev_handle, dev_ino, cpuid, err);
 432         err = sun4v_vintr_set_state(dev_handle, dev_ino,
 433                                     HV_INTR_STATE_IDLE);
 434         if (err != HV_EOK)
 435                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 436                        "HV_INTR_STATE_IDLE): err(%d)\n",
 437                        dev_handle, dev_ino, err);
 438         err = sun4v_vintr_set_valid(dev_handle, dev_ino,
 439                                     HV_INTR_ENABLED);
 440         if (err != HV_EOK)
 441                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 442                        "HV_INTR_ENABLED): err(%d)\n",
 443                        dev_handle, dev_ino, err);
 444 }
 445
 446 static int sun4v_virt_set_affinity(struct irq_data *data,
 447                                     const struct cpumask *mask, bool force)
 448 {
 449         unsigned long cpuid, dev_handle, dev_ino;
 450         int err;
 451
 452         cpuid = irq_choose_cpu(data->irq, mask);
 453
 454         dev_handle = irq_table[data->irq].dev_handle;
 455         dev_ino = irq_table[data->irq].dev_ino;
 456
 457         err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
 458         if (err != HV_EOK)
 459                 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
 460                        "err(%d)\n",
 461                        dev_handle, dev_ino, cpuid, err);
 462
 463         return 0;
 464 }
 465
 466 static void sun4v_virq_disable(struct irq_data *data)
 467 {
 468         unsigned long dev_handle, dev_ino;
 469         int err;
 470
 471         dev_handle = irq_table[data->irq].dev_handle;
 472         dev_ino = irq_table[data->irq].dev_ino;
 473
 474         err = sun4v_vintr_set_valid(dev_handle, dev_ino,
 475                                     HV_INTR_DISABLED);
 476         if (err != HV_EOK)
 477                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 478                        "HV_INTR_DISABLED): err(%d)\n",
 479                        dev_handle, dev_ino, err);
 480 }
 481
 482 static void sun4v_virq_eoi(struct irq_data *data)
 483 {
 484         struct irq_desc *desc = irq_desc + data->irq;
 485         unsigned long dev_handle, dev_ino;
 486         int err;
 487
 488         if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 489                 return;
 490
 491         dev_handle = irq_table[data->irq].dev_handle;
 492         dev_ino = irq_table[data->irq].dev_ino;
 493
 494         err = sun4v_vintr_set_state(dev_handle, dev_ino,
 495                                     HV_INTR_STATE_IDLE);
 496         if (err != HV_EOK)
 497                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 498                        "HV_INTR_STATE_IDLE): err(%d)\n",
 499                        dev_handle, dev_ino, err);
 500 }
 501
 502 static struct irq_chip sun4u_irq = {
 503         .name                   = "sun4u",
 504         .irq_enable             = sun4u_irq_enable,
 505         .irq_disable            = sun4u_irq_disable,
 506         .irq_eoi                = sun4u_irq_eoi,
 507         .irq_set_affinity       = sun4u_set_affinity,
 508 };
 509
 510 static struct irq_chip sun4v_irq = {
 511         .name                   = "sun4v",
 512         .irq_enable             = sun4v_irq_enable,
 513         .irq_disable            = sun4v_irq_disable,
 514         .irq_eoi                = sun4v_irq_eoi,
 515         .irq_set_affinity       = sun4v_set_affinity,
 516 };
 517
 518 static struct irq_chip sun4v_virq = {
 519         .name                   = "vsun4v",
 520         .irq_enable             = sun4v_virq_enable,
 521         .irq_disable            = sun4v_virq_disable,
 522         .irq_eoi                = sun4v_virq_eoi,
 523         .irq_set_affinity       = sun4v_virt_set_affinity,
 524 };
 525
 526 static void pre_flow_handler(unsigned int irq, struct irq_desc *desc)
 527 {
 528         struct irq_handler_data *handler_data = get_irq_data(irq);
 529         unsigned int ino = irq_table[irq].dev_ino;
 530
 531         handler_data->pre_handler(ino, handler_data->arg1, handler_data->arg2);
 532
 533         handle_fasteoi_irq(irq, desc);
 534 }
 535
 536 void irq_install_pre_handler(int irq,
 537                              void (*func)(unsigned int, void *, void *),
 538                              void *arg1, void *arg2)
 539 {
 540         struct irq_handler_data *handler_data = get_irq_data(irq);
 541         struct irq_desc *desc = irq_desc + irq;
 542
 543         handler_data->pre_handler = func;
 544         handler_data->arg1 = arg1;
 545         handler_data->arg2 = arg2;
 546
 547         desc->handle_irq = pre_flow_handler;
 548 }
 549
 550 unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
 551 {
 552         struct ino_bucket *bucket;
 553         struct irq_handler_data *handler_data;
 554         unsigned int irq;
 555         int ino;
 556
 557         BUG_ON(tlb_type == hypervisor);
 558
 559         ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
 560         bucket = &ivector_table[ino];
 561         irq = bucket_get_irq(__pa(bucket));
 562         if (!irq) {
 563                 irq = irq_alloc(0, ino);
 564                 bucket_set_irq(__pa(bucket), irq);
 565                 set_irq_chip_and_handler_name(irq,
 566                                               &sun4u_irq,
 567                                               handle_fasteoi_irq,
 568                                               "IVEC");
 569         }
 570
 571         handler_data = get_irq_data(irq);
 572         if (unlikely(handler_data))
 573                 goto out;
 574
 575         handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 576         if (unlikely(!handler_data)) {
 577                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
 578                 prom_halt();
 579         }
 580         set_irq_data(irq, handler_data);
 581
 582         handler_data->imap  = imap;
 583         handler_data->iclr  = iclr;
 584
 585 out:
 586         return irq;
 587 }
 588
 589 static unsigned int sun4v_build_common(unsigned long sysino,
 590                                        struct irq_chip *chip)
 591 {
 592         struct ino_bucket *bucket;
 593         struct irq_handler_data *handler_data;
 594         unsigned int irq;
 595
 596         BUG_ON(tlb_type != hypervisor);
 597
 598         bucket = &ivector_table[sysino];
 599         irq = bucket_get_irq(__pa(bucket));
 600         if (!irq) {
 601                 irq = irq_alloc(0, sysino);
 602                 bucket_set_irq(__pa(bucket), irq);
 603                 set_irq_chip_and_handler_name(irq, chip,
 604                                               handle_fasteoi_irq,
 605                                               "IVEC");
 606         }
 607
 608         handler_data = get_irq_data(irq);
 609         if (unlikely(handler_data))
 610                 goto out;
 611
 612         handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 613         if (unlikely(!handler_data)) {
 614                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
 615                 prom_halt();
 616         }
 617         set_irq_data(irq, handler_data);
 618
 619         /* Catch accidental accesses to these things.  IMAP/ICLR handling
 620          * is done by hypervisor calls on sun4v platforms, not by direct
 621          * register accesses.
 622          */
 623         handler_data->imap = ~0UL;
 624         handler_data->iclr = ~0UL;
 625
 626 out:
 627         return irq;
 628 }
 629
 630 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
 631 {
 632         unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino);
 633
 634         return sun4v_build_common(sysino, &sun4v_irq);
 635 }
 636
 637 unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
 638 {
 639         struct irq_handler_data *handler_data;
 640         unsigned long hv_err, cookie;
 641         struct ino_bucket *bucket;
 642         struct irq_desc *desc;
 643         unsigned int irq;
 644
 645         bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC);
 646         if (unlikely(!bucket))
 647                 return 0;
 648
 649         /* The only reference we store to the IRQ bucket is
 650          * by physical address which kmemleak can't see, tell
 651          * it that this object explicitly is not a leak and
 652          * should be scanned.
 653          */
 654         kmemleak_not_leak(bucket);
 655
 656         __flush_dcache_range((unsigned long) bucket,
 657                              ((unsigned long) bucket +
 658                               sizeof(struct ino_bucket)));
 659
 660         irq = irq_alloc(devhandle, devino);
 661         bucket_set_irq(__pa(bucket), irq);
 662
 663         set_irq_chip_and_handler_name(irq, &sun4v_virq,
 664                                       handle_fasteoi_irq,
 665                                       "IVEC");
 666
 667         handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 668         if (unlikely(!handler_data))
 669                 return 0;
 670
 671         /* In order to make the LDC channel startup sequence easier,
 672          * especially wrt. locking, we do not let request_irq() enable
 673          * the interrupt.
 674          */
 675         desc = irq_desc + irq;
 676         desc->status |= IRQ_NOAUTOEN;
 677
 678         set_irq_data(irq, handler_data);
 679
 680         /* Catch accidental accesses to these things.  IMAP/ICLR handling
 681          * is done by hypervisor calls on sun4v platforms, not by direct
 682          * register accesses.
 683          */
 684         handler_data->imap = ~0UL;
 685         handler_data->iclr = ~0UL;
 686
 687         cookie = ~__pa(bucket);
 688         hv_err = sun4v_vintr_set_cookie(devhandle, devino, cookie);
 689         if (hv_err) {
 690                 prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] "
 691                             "err=%lu\n", devhandle, devino, hv_err);
 692                 prom_halt();
 693         }
 694
 695         return irq;
 696 }
 697
 698 void ack_bad_irq(unsigned int irq)
 699 {
 700         unsigned int ino = irq_table[irq].dev_ino;
 701
 702         if (!ino)
 703                 ino = 0xdeadbeef;
 704
 705         printk(KERN_CRIT "Unexpected IRQ from ino[%x] irq[%u]\n",
 706                ino, irq);
 707 }
 708
 709 void *hardirq_stack[NR_CPUS];
 710 void *softirq_stack[NR_CPUS];
 711
 712 void __irq_entry handler_irq(int pil, struct pt_regs *regs)
 713 {
 714         unsigned long pstate, bucket_pa;
 715         struct pt_regs *old_regs;
 716         void *orig_sp;
 717
 718         clear_softint(1 << pil);
 719
 720         old_regs = set_irq_regs(regs);
 721         irq_enter();
 722
 723         /* Grab an atomic snapshot of the pending IVECs.  */
 724         __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
 725                              "wrpr      %0, %3, %%pstate\n\t"
 726                              "ldx       [%2], %1\n\t"
 727                              "stx       %%g0, [%2]\n\t"
 728                              "wrpr      %0, 0x0, %%pstate\n\t"
 729                              : "=&r" (pstate), "=&r" (bucket_pa)
 730                              : "r" (irq_work_pa(smp_processor_id())),
 731                                "i" (PSTATE_IE)
 732                              : "memory");
 733
 734         orig_sp = set_hardirq_stack();
 735
 736         while (bucket_pa) {
 737                 struct irq_desc *desc;
 738                 unsigned long next_pa;
 739                 unsigned int irq;
 740
 741                 next_pa = bucket_get_chain_pa(bucket_pa);
 742                 irq = bucket_get_irq(bucket_pa);
 743                 bucket_clear_chain_pa(bucket_pa);
 744
 745                 desc = irq_desc + irq;
 746
 747                 if (!(desc->status & IRQ_DISABLED))
 748                         desc->handle_irq(irq, desc);
 749
 750                 bucket_pa = next_pa;
 751         }
 752
 753         restore_hardirq_stack(orig_sp);
 754
 755         irq_exit();
 756         set_irq_regs(old_regs);
 757 }
 758
 759 void do_softirq(void)
 760 {
 761         unsigned long flags;
 762
 763         if (in_interrupt())
 764                 return;
 765
 766         local_irq_save(flags);
 767
 768         if (local_softirq_pending()) {
 769                 void *orig_sp, *sp = softirq_stack[smp_processor_id()];
 770
 771                 sp += THREAD_SIZE - 192 - STACK_BIAS;
 772
 773                 __asm__ __volatile__("mov %%sp, %0\n\t"
 774                                      "mov %1, %%sp"
 775                                      : "=&r" (orig_sp)
 776                                      : "r" (sp));
 777                 __do_softirq();
 778                 __asm__ __volatile__("mov %0, %%sp"
 779                                      : : "r" (orig_sp));
 780         }
 781
 782         local_irq_restore(flags);
 783 }
 784
 785 #ifdef CONFIG_HOTPLUG_CPU
 786 void fixup_irqs(void)
 787 {
 788         unsigned int irq;
 789
 790         for (irq = 0; irq < NR_IRQS; irq++) {
 791                 unsigned long flags;
 792
 793                 raw_spin_lock_irqsave(&irq_desc[irq].lock, flags);
 794                 if (irq_desc[irq].action &&
 795                     !(irq_desc[irq].status & IRQ_PER_CPU)) {
 796                         struct irq_data *data = irq_get_irq_data(irq);
 797
 798                         if (data->chip->irq_set_affinity)
 799                                 data->chip->irq_set_affinity(data,
 800                                                              data->affinity,
 801                                                              false);
 802                 }
 803                 raw_spin_unlock_irqrestore(&irq_desc[irq].lock, flags);
 804         }
 805
 806         tick_ops->disable_irq();
 807 }
 808 #endif
 809
 810 struct sun5_timer {
 811         u64     count0;
 812         u64     limit0;
 813         u64     count1;
 814         u64     limit1;
 815 };
 816
 817 static struct sun5_timer *prom_timers;
 818 static u64 prom_limit0, prom_limit1;
 819
 820 static void map_prom_timers(void)
 821 {
 822         struct device_node *dp;
 823         const unsigned int *addr;
 824
 825         /* PROM timer node hangs out in the top level of device siblings... */
 826         dp = of_find_node_by_path("/");
 827         dp = dp->child;
 828         while (dp) {
 829                 if (!strcmp(dp->name, "counter-timer"))
 830                         break;
 831                 dp = dp->sibling;
 832         }
 833
 834         /* Assume if node is not present, PROM uses different tick mechanism
 835          * which we should not care about.
 836          */
 837         if (!dp) {
 838                 prom_timers = (struct sun5_timer *) 0;
 839                 return;
 840         }
 841
 842         /* If PROM is really using this, it must be mapped by him. */
 843         addr = of_get_property(dp, "address", NULL);
 844         if (!addr) {
 845                 prom_printf("PROM does not have timer mapped, trying to continue.\n");
 846                 prom_timers = (struct sun5_timer *) 0;
 847                 return;
 848         }
 849         prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
 850 }
 851
 852 static void kill_prom_timer(void)
 853 {
 854         if (!prom_timers)
 855                 return;
 856
 857         /* Save them away for later. */
 858         prom_limit0 = prom_timers->limit0;
 859         prom_limit1 = prom_timers->limit1;
 860
 861         /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
 862          * We turn both off here just to be paranoid.
 863          */
 864         prom_timers->limit0 = 0;
 865         prom_timers->limit1 = 0;
 866
 867         /* Wheee, eat the interrupt packet too... */
 868         __asm__ __volatile__(
 869 "       mov     0x40, %%g2\n"
 870 "       ldxa    [%%g0] %0, %%g1\n"
 871 "       ldxa    [%%g2] %1, %%g1\n"
 872 "       stxa    %%g0, [%%g0] %0\n"
 873 "       membar  #Sync\n"
 874         : /* no outputs */
 875         : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
 876         : "g1", "g2");
 877 }
 878
 879 void notrace init_irqwork_curcpu(void)
 880 {
 881         int cpu = hard_smp_processor_id();
 882
 883         trap_block[cpu].irq_worklist_pa = 0UL;
 884 }
 885
 886 /* Please be very careful with register_one_mondo() and
 887  * sun4v_register_mondo_queues().
 888  *
 889  * On SMP this gets invoked from the CPU trampoline before
 890  * the cpu has fully taken over the trap table from OBP,
 891  * and it's kernel stack + %g6 thread register state is
 892  * not fully cooked yet.
 893  *
 894  * Therefore you cannot make any OBP calls, not even prom_printf,
 895  * from these two routines.
 896  */
 897 static void __cpuinit notrace register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask)
 898 {
 899         unsigned long num_entries = (qmask + 1) / 64;
 900         unsigned long status;
 901
 902         status = sun4v_cpu_qconf(type, paddr, num_entries);
 903         if (status != HV_EOK) {
 904                 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
 905                             "err %lu\n", type, paddr, num_entries, status);
 906                 prom_halt();
 907         }
 908 }
 909
 910 void __cpuinit notrace sun4v_register_mondo_queues(int this_cpu)
 911 {
 912         struct trap_per_cpu *tb = &trap_block[this_cpu];
 913
 914         register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO,
 915                            tb->cpu_mondo_qmask);
 916         register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO,
 917                            tb->dev_mondo_qmask);
 918         register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR,
 919                            tb->resum_qmask);
 920         register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR,
 921                            tb->nonresum_qmask);
 922 }
 923
 924 /* Each queue region must be a power of 2 multiple of 64 bytes in
 925  * size.  The base real address must be aligned to the size of the
 926  * region.  Thus, an 8KB queue must be 8KB aligned, for example.
 927  */
 928 static void __init alloc_one_queue(unsigned long *pa_ptr, unsigned long qmask)
 929 {
 930         unsigned long size = PAGE_ALIGN(qmask + 1);
 931         unsigned long order = get_order(size);
 932         unsigned long p;
 933
 934         p = __get_free_pages(GFP_KERNEL, order);
 935         if (!p) {
 936                 prom_printf("SUN4V: Error, cannot allocate queue.\n");
 937                 prom_halt();
 938         }
 939
 940         *pa_ptr = __pa(p);
 941 }
 942
 943 static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb)
 944 {
 945 #ifdef CONFIG_SMP
 946         unsigned long page;
 947
 948         BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
 949
 950         page = get_zeroed_page(GFP_KERNEL);
 951         if (!page) {
 952                 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
 953                 prom_halt();
 954         }
 955
 956         tb->cpu_mondo_block_pa = __pa(page);
 957         tb->cpu_list_pa = __pa(page + 64);
 958 #endif
 959 }
 960
 961 /* Allocate mondo and error queues for all possible cpus.  */
 962 static void __init sun4v_init_mondo_queues(void)
 963 {
 964         int cpu;
 965
 966         for_each_possible_cpu(cpu) {
 967                 struct trap_per_cpu *tb = &trap_block[cpu];
 968
 969                 alloc_one_queue(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask);
 970                 alloc_one_queue(&tb->dev_mondo_pa, tb->dev_mondo_qmask);
 971                 alloc_one_queue(&tb->resum_mondo_pa, tb->resum_qmask);
 972                 alloc_one_queue(&tb->resum_kernel_buf_pa, tb->resum_qmask);
 973                 alloc_one_queue(&tb->nonresum_mondo_pa, tb->nonresum_qmask);
 974                 alloc_one_queue(&tb->nonresum_kernel_buf_pa,
 975                                 tb->nonresum_qmask);
 976         }
 977 }
 978
 979 static void __init init_send_mondo_info(void)
 980 {
 981         int cpu;
 982
 983         for_each_possible_cpu(cpu) {
 984                 struct trap_per_cpu *tb = &trap_block[cpu];
 985
 986                 init_cpu_send_mondo_info(tb);
 987         }
 988 }
 989
 990 static struct irqaction timer_irq_action = {
 991         .name = "timer",
 992 };
 993
 994 /* Only invoked on boot processor. */
 995 void __init init_IRQ(void)
 996 {
 997         unsigned long size;
 998
 999         map_prom_timers();
1000         kill_prom_timer();
1001
1002         size = sizeof(struct ino_bucket) * NUM_IVECS;
1003         ivector_table = kzalloc(size, GFP_KERNEL);
1004         if (!ivector_table) {
1005                 prom_printf("Fatal error, cannot allocate ivector_table\n");
1006                 prom_halt();
1007         }
1008         __flush_dcache_range((unsigned long) ivector_table,
1009                              ((unsigned long) ivector_table) + size);
1010
1011         ivector_table_pa = __pa(ivector_table);
1012
1013         if (tlb_type == hypervisor)
1014                 sun4v_init_mondo_queues();
1015
1016         init_send_mondo_info();
1017
1018         if (tlb_type == hypervisor) {
1019                 /* Load up the boot cpu's entries.  */
1020                 sun4v_register_mondo_queues(hard_smp_processor_id());
1021         }
1022
1023         /* We need to clear any IRQ's pending in the soft interrupt
1024          * registers, a spurious one could be left around from the
1025          * PROM timer which we just disabled.
1026          */
1027         clear_softint(get_softint());
1028
1029         /* Now that ivector table is initialized, it is safe
1030          * to receive IRQ vector traps.  We will normally take
1031          * one or two right now, in case some device PROM used
1032          * to boot us wants to speak to us.  We just ignore them.
1033          */
1034         __asm__ __volatile__("rdpr      %%pstate, %%g1\n\t"
1035                              "or        %%g1, %0, %%g1\n\t"
1036                              "wrpr      %%g1, 0x0, %%pstate"
1037                              : /* No outputs */
1038                              : "i" (PSTATE_IE)
1039                              : "g1");
1040
1041         irq_desc[0].action = &timer_irq_action;
1042 }