arch/sparc/kernel/irq_64.c

   1 /* irq.c: UltraSparc IRQ handling/init/registry.
   2  *
   3  * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  * Copyright (C) 1998  Eddie C. Dost    (ecd@skynet.be)
   5  * Copyright (C) 1998  Jakub Jelinek    (jj@ultra.linux.cz)
   6  */
   7
   8 #include <linux/sched.h>
   9 #include <linux/linkage.h>
  10 #include <linux/ptrace.h>
  11 #include <linux/errno.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/signal.h>
  14 #include <linux/mm.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/slab.h>
  17 #include <linux/random.h>
  18 #include <linux/init.h>
  19 #include <linux/delay.h>
  20 #include <linux/proc_fs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/ftrace.h>
  23 #include <linux/irq.h>
  24 #include <linux/kmemleak.h>
  25
  26 #include <asm/ptrace.h>
  27 #include <asm/processor.h>
  28 #include <linux/atomic.h>
  29 #include <asm/system.h>
  30 #include <asm/irq.h>
  31 #include <asm/io.h>
  32 #include <asm/iommu.h>
  33 #include <asm/upa.h>
  34 #include <asm/oplib.h>
  35 #include <asm/prom.h>
  36 #include <asm/timer.h>
  37 #include <asm/smp.h>
  38 #include <asm/starfire.h>
  39 #include <asm/uaccess.h>
  40 #include <asm/cache.h>
  41 #include <asm/cpudata.h>
  42 #include <asm/auxio.h>
  43 #include <asm/head.h>
  44 #include <asm/hypervisor.h>
  45 #include <asm/cacheflush.h>
  46
  47 #include "entry.h"
  48 #include "cpumap.h"
  49 #include "kstack.h"
  50
  51 #define NUM_IVECS       (IMAP_INR + 1)
  52
  53 struct ino_bucket *ivector_table;
  54 unsigned long ivector_table_pa;
  55
  56 /* On several sun4u processors, it is illegal to mix bypass and
  57  * non-bypass accesses.  Therefore we access all INO buckets
  58  * using bypass accesses only.
  59  */
  60 static unsigned long bucket_get_chain_pa(unsigned long bucket_pa)
  61 {
  62         unsigned long ret;
  63
  64         __asm__ __volatile__("ldxa      [%1] %2, %0"
  65                              : "=&r" (ret)
  66                              : "r" (bucket_pa +
  67                                     offsetof(struct ino_bucket,
  68                                              __irq_chain_pa)),
  69                                "i" (ASI_PHYS_USE_EC));
  70
  71         return ret;
  72 }
  73
  74 static void bucket_clear_chain_pa(unsigned long bucket_pa)
  75 {
  76         __asm__ __volatile__("stxa      %%g0, [%0] %1"
  77                              : /* no outputs */
  78                              : "r" (bucket_pa +
  79                                     offsetof(struct ino_bucket,
  80                                              __irq_chain_pa)),
  81                                "i" (ASI_PHYS_USE_EC));
  82 }
  83
  84 static unsigned int bucket_get_irq(unsigned long bucket_pa)
  85 {
  86         unsigned int ret;
  87
  88         __asm__ __volatile__("lduwa     [%1] %2, %0"
  89                              : "=&r" (ret)
  90                              : "r" (bucket_pa +
  91                                     offsetof(struct ino_bucket,
  92                                              __irq)),
  93                                "i" (ASI_PHYS_USE_EC));
  94
  95         return ret;
  96 }
  97
  98 static void bucket_set_irq(unsigned long bucket_pa, unsigned int irq)
  99 {
 100         __asm__ __volatile__("stwa      %0, [%1] %2"
 101                              : /* no outputs */
 102                              : "r" (irq),
 103                                "r" (bucket_pa +
 104                                     offsetof(struct ino_bucket,
 105                                              __irq)),
 106                                "i" (ASI_PHYS_USE_EC));
 107 }
 108
 109 #define irq_work_pa(__cpu)      &(trap_block[(__cpu)].irq_worklist_pa)
 110
 111 static struct {
 112         unsigned int dev_handle;
 113         unsigned int dev_ino;
 114         unsigned int in_use;
 115 } irq_table[NR_IRQS];
 116 static DEFINE_SPINLOCK(irq_alloc_lock);
 117
 118 unsigned char irq_alloc(unsigned int dev_handle, unsigned int dev_ino)
 119 {
 120         unsigned long flags;
 121         unsigned char ent;
 122
 123         BUILD_BUG_ON(NR_IRQS >= 256);
 124
 125         spin_lock_irqsave(&irq_alloc_lock, flags);
 126
 127         for (ent = 1; ent < NR_IRQS; ent++) {
 128                 if (!irq_table[ent].in_use)
 129                         break;
 130         }
 131         if (ent >= NR_IRQS) {
 132                 printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
 133                 ent = 0;
 134         } else {
 135                 irq_table[ent].dev_handle = dev_handle;
 136                 irq_table[ent].dev_ino = dev_ino;
 137                 irq_table[ent].in_use = 1;
 138         }
 139
 140         spin_unlock_irqrestore(&irq_alloc_lock, flags);
 141
 142         return ent;
 143 }
 144
 145 #ifdef CONFIG_PCI_MSI
 146 void irq_free(unsigned int irq)
 147 {
 148         unsigned long flags;
 149
 150         if (irq >= NR_IRQS)
 151                 return;
 152
 153         spin_lock_irqsave(&irq_alloc_lock, flags);
 154
 155         irq_table[irq].in_use = 0;
 156
 157         spin_unlock_irqrestore(&irq_alloc_lock, flags);
 158 }
 159 #endif
 160
 161 /*
 162  * /proc/interrupts printing:
 163  */
 164 int arch_show_interrupts(struct seq_file *p, int prec)
 165 {
 166         int j;
 167
 168         seq_printf(p, "NMI: ");
 169         for_each_online_cpu(j)
 170                 seq_printf(p, "%10u ", cpu_data(j).__nmi_count);
 171         seq_printf(p, "     Non-maskable interrupts\n");
 172         return 0;
 173 }
 174
 175 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
 176 {
 177         unsigned int tid;
 178
 179         if (this_is_starfire) {
 180                 tid = starfire_translate(imap, cpuid);
 181                 tid <<= IMAP_TID_SHIFT;
 182                 tid &= IMAP_TID_UPA;
 183         } else {
 184                 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 185                         unsigned long ver;
 186
 187                         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 188                         if ((ver >> 32UL) == __JALAPENO_ID ||
 189                             (ver >> 32UL) == __SERRANO_ID) {
 190                                 tid = cpuid << IMAP_TID_SHIFT;
 191                                 tid &= IMAP_TID_JBUS;
 192                         } else {
 193                                 unsigned int a = cpuid & 0x1f;
 194                                 unsigned int n = (cpuid >> 5) & 0x1f;
 195
 196                                 tid = ((a << IMAP_AID_SHIFT) |
 197                                        (n << IMAP_NID_SHIFT));
 198                                 tid &= (IMAP_AID_SAFARI |
 199                                         IMAP_NID_SAFARI);
 200                         }
 201                 } else {
 202                         tid = cpuid << IMAP_TID_SHIFT;
 203                         tid &= IMAP_TID_UPA;
 204                 }
 205         }
 206
 207         return tid;
 208 }
 209
 210 struct irq_handler_data {
 211         unsigned long   iclr;
 212         unsigned long   imap;
 213
 214         void            (*pre_handler)(unsigned int, void *, void *);
 215         void            *arg1;
 216         void            *arg2;
 217 };
 218
 219 #ifdef CONFIG_SMP
 220 static int irq_choose_cpu(unsigned int irq, const struct cpumask *affinity)
 221 {
 222         cpumask_t mask;
 223         int cpuid;
 224
 225         cpumask_copy(&mask, affinity);
 226         if (cpumask_equal(&mask, cpu_online_mask)) {
 227                 cpuid = map_to_cpu(irq);
 228         } else {
 229                 cpumask_t tmp;
 230
 231                 cpumask_and(&tmp, cpu_online_mask, &mask);
 232                 cpuid = cpumask_empty(&tmp) ? map_to_cpu(irq) : cpumask_first(&tmp);
 233         }
 234
 235         return cpuid;
 236 }
 237 #else
 238 #define irq_choose_cpu(irq, affinity)   \
 239         real_hard_smp_processor_id()
 240 #endif
 241
 242 static void sun4u_irq_enable(struct irq_data *data)
 243 {
 244         struct irq_handler_data *handler_data = data->handler_data;
 245
 246         if (likely(handler_data)) {
 247                 unsigned long cpuid, imap, val;
 248                 unsigned int tid;
 249
 250                 cpuid = irq_choose_cpu(data->irq, data->affinity);
 251                 imap = handler_data->imap;
 252
 253                 tid = sun4u_compute_tid(imap, cpuid);
 254
 255                 val = upa_readq(imap);
 256                 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
 257                          IMAP_AID_SAFARI | IMAP_NID_SAFARI);
 258                 val |= tid | IMAP_VALID;
 259                 upa_writeq(val, imap);
 260                 upa_writeq(ICLR_IDLE, handler_data->iclr);
 261         }
 262 }
 263
 264 static int sun4u_set_affinity(struct irq_data *data,
 265                                const struct cpumask *mask, bool force)
 266 {
 267         struct irq_handler_data *handler_data = data->handler_data;
 268
 269         if (likely(handler_data)) {
 270                 unsigned long cpuid, imap, val;
 271                 unsigned int tid;
 272
 273                 cpuid = irq_choose_cpu(data->irq, mask);
 274                 imap = handler_data->imap;
 275
 276                 tid = sun4u_compute_tid(imap, cpuid);
 277
 278                 val = upa_readq(imap);
 279                 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
 280                          IMAP_AID_SAFARI | IMAP_NID_SAFARI);
 281                 val |= tid | IMAP_VALID;
 282                 upa_writeq(val, imap);
 283                 upa_writeq(ICLR_IDLE, handler_data->iclr);
 284         }
 285
 286         return 0;
 287 }
 288
 289 /* Don't do anything.  The desc->status check for IRQ_DISABLED in
 290  * handler_irq() will skip the handler call and that will leave the
 291  * interrupt in the sent state.  The next ->enable() call will hit the
 292  * ICLR register to reset the state machine.
 293  *
 294  * This scheme is necessary, instead of clearing the Valid bit in the
 295  * IMAP register, to handle the case of IMAP registers being shared by
 296  * multiple INOs (and thus ICLR registers).  Since we use a different
 297  * virtual IRQ for each shared IMAP instance, the generic code thinks
 298  * there is only one user so it prematurely calls ->disable() on
 299  * free_irq().
 300  *
 301  * We have to provide an explicit ->disable() method instead of using
 302  * NULL to get the default.  The reason is that if the generic code
 303  * sees that, it also hooks up a default ->shutdown method which
 304  * invokes ->mask() which we do not want.  See irq_chip_set_defaults().
 305  */
 306 static void sun4u_irq_disable(struct irq_data *data)
 307 {
 308 }
 309
 310 static void sun4u_irq_eoi(struct irq_data *data)
 311 {
 312         struct irq_handler_data *handler_data = data->handler_data;
 313
 314         if (likely(handler_data))
 315                 upa_writeq(ICLR_IDLE, handler_data->iclr);
 316 }
 317
 318 static void sun4v_irq_enable(struct irq_data *data)
 319 {
 320         unsigned int ino = irq_table[data->irq].dev_ino;
 321         unsigned long cpuid = irq_choose_cpu(data->irq, data->affinity);
 322         int err;
 323
 324         err = sun4v_intr_settarget(ino, cpuid);
 325         if (err != HV_EOK)
 326                 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
 327                        "err(%d)\n", ino, cpuid, err);
 328         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 329         if (err != HV_EOK)
 330                 printk(KERN_ERR "sun4v_intr_setstate(%x): "
 331                        "err(%d)\n", ino, err);
 332         err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
 333         if (err != HV_EOK)
 334                 printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n",
 335                        ino, err);
 336 }
 337
 338 static int sun4v_set_affinity(struct irq_data *data,
 339                                const struct cpumask *mask, bool force)
 340 {
 341         unsigned int ino = irq_table[data->irq].dev_ino;
 342         unsigned long cpuid = irq_choose_cpu(data->irq, mask);
 343         int err;
 344
 345         err = sun4v_intr_settarget(ino, cpuid);
 346         if (err != HV_EOK)
 347                 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
 348                        "err(%d)\n", ino, cpuid, err);
 349
 350         return 0;
 351 }
 352
 353 static void sun4v_irq_disable(struct irq_data *data)
 354 {
 355         unsigned int ino = irq_table[data->irq].dev_ino;
 356         int err;
 357
 358         err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
 359         if (err != HV_EOK)
 360                 printk(KERN_ERR "sun4v_intr_setenabled(%x): "
 361                        "err(%d)\n", ino, err);
 362 }
 363
 364 static void sun4v_irq_eoi(struct irq_data *data)
 365 {
 366         unsigned int ino = irq_table[data->irq].dev_ino;
 367         int err;
 368
 369         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 370         if (err != HV_EOK)
 371                 printk(KERN_ERR "sun4v_intr_setstate(%x): "
 372                        "err(%d)\n", ino, err);
 373 }
 374
 375 static void sun4v_virq_enable(struct irq_data *data)
 376 {
 377         unsigned long cpuid, dev_handle, dev_ino;
 378         int err;
 379
 380         cpuid = irq_choose_cpu(data->irq, data->affinity);
 381
 382         dev_handle = irq_table[data->irq].dev_handle;
 383         dev_ino = irq_table[data->irq].dev_ino;
 384
 385         err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
 386         if (err != HV_EOK)
 387                 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
 388                        "err(%d)\n",
 389                        dev_handle, dev_ino, cpuid, err);
 390         err = sun4v_vintr_set_state(dev_handle, dev_ino,
 391                                     HV_INTR_STATE_IDLE);
 392         if (err != HV_EOK)
 393                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 394                        "HV_INTR_STATE_IDLE): err(%d)\n",
 395                        dev_handle, dev_ino, err);
 396         err = sun4v_vintr_set_valid(dev_handle, dev_ino,
 397                                     HV_INTR_ENABLED);
 398         if (err != HV_EOK)
 399                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 400                        "HV_INTR_ENABLED): err(%d)\n",
 401                        dev_handle, dev_ino, err);
 402 }
 403
 404 static int sun4v_virt_set_affinity(struct irq_data *data,
 405                                     const struct cpumask *mask, bool force)
 406 {
 407         unsigned long cpuid, dev_handle, dev_ino;
 408         int err;
 409
 410         cpuid = irq_choose_cpu(data->irq, mask);
 411
 412         dev_handle = irq_table[data->irq].dev_handle;
 413         dev_ino = irq_table[data->irq].dev_ino;
 414
 415         err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
 416         if (err != HV_EOK)
 417                 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
 418                        "err(%d)\n",
 419                        dev_handle, dev_ino, cpuid, err);
 420
 421         return 0;
 422 }
 423
 424 static void sun4v_virq_disable(struct irq_data *data)
 425 {
 426         unsigned long dev_handle, dev_ino;
 427         int err;
 428
 429         dev_handle = irq_table[data->irq].dev_handle;
 430         dev_ino = irq_table[data->irq].dev_ino;
 431
 432         err = sun4v_vintr_set_valid(dev_handle, dev_ino,
 433                                     HV_INTR_DISABLED);
 434         if (err != HV_EOK)
 435                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 436                        "HV_INTR_DISABLED): err(%d)\n",
 437                        dev_handle, dev_ino, err);
 438 }
 439
 440 static void sun4v_virq_eoi(struct irq_data *data)
 441 {
 442         unsigned long dev_handle, dev_ino;
 443         int err;
 444
 445         dev_handle = irq_table[data->irq].dev_handle;
 446         dev_ino = irq_table[data->irq].dev_ino;
 447
 448         err = sun4v_vintr_set_state(dev_handle, dev_ino,
 449                                     HV_INTR_STATE_IDLE);
 450         if (err != HV_EOK)
 451                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 452                        "HV_INTR_STATE_IDLE): err(%d)\n",
 453                        dev_handle, dev_ino, err);
 454 }
 455
 456 static struct irq_chip sun4u_irq = {
 457         .name                   = "sun4u",
 458         .irq_enable             = sun4u_irq_enable,
 459         .irq_disable            = sun4u_irq_disable,
 460         .irq_eoi                = sun4u_irq_eoi,
 461         .irq_set_affinity       = sun4u_set_affinity,
 462         .flags                  = IRQCHIP_EOI_IF_HANDLED,
 463 };
 464
 465 static struct irq_chip sun4v_irq = {
 466         .name                   = "sun4v",
 467         .irq_enable             = sun4v_irq_enable,
 468         .irq_disable            = sun4v_irq_disable,
 469         .irq_eoi                = sun4v_irq_eoi,
 470         .irq_set_affinity       = sun4v_set_affinity,
 471         .flags                  = IRQCHIP_EOI_IF_HANDLED,
 472 };
 473
 474 static struct irq_chip sun4v_virq = {
 475         .name                   = "vsun4v",
 476         .irq_enable             = sun4v_virq_enable,
 477         .irq_disable            = sun4v_virq_disable,
 478         .irq_eoi                = sun4v_virq_eoi,
 479         .irq_set_affinity       = sun4v_virt_set_affinity,
 480         .flags                  = IRQCHIP_EOI_IF_HANDLED,
 481 };
 482
 483 static void pre_flow_handler(struct irq_data *d)
 484 {
 485         struct irq_handler_data *handler_data = irq_data_get_irq_handler_data(d);
 486         unsigned int ino = irq_table[d->irq].dev_ino;
 487
 488         handler_data->pre_handler(ino, handler_data->arg1, handler_data->arg2);
 489 }
 490
 491 void irq_install_pre_handler(int irq,
 492                              void (*func)(unsigned int, void *, void *),
 493                              void *arg1, void *arg2)
 494 {
 495         struct irq_handler_data *handler_data = irq_get_handler_data(irq);
 496
 497         handler_data->pre_handler = func;
 498         handler_data->arg1 = arg1;
 499         handler_data->arg2 = arg2;
 500
 501         __irq_set_preflow_handler(irq, pre_flow_handler);
 502 }
 503
 504 unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
 505 {
 506         struct ino_bucket *bucket;
 507         struct irq_handler_data *handler_data;
 508         unsigned int irq;
 509         int ino;
 510
 511         BUG_ON(tlb_type == hypervisor);
 512
 513         ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
 514         bucket = &ivector_table[ino];
 515         irq = bucket_get_irq(__pa(bucket));
 516         if (!irq) {
 517                 irq = irq_alloc(0, ino);
 518                 bucket_set_irq(__pa(bucket), irq);
 519                 irq_set_chip_and_handler_name(irq, &sun4u_irq,
 520                                               handle_fasteoi_irq, "IVEC");
 521         }
 522
 523         handler_data = irq_get_handler_data(irq);
 524         if (unlikely(handler_data))
 525                 goto out;
 526
 527         handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 528         if (unlikely(!handler_data)) {
 529                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
 530                 prom_halt();
 531         }
 532         irq_set_handler_data(irq, handler_data);
 533
 534         handler_data->imap  = imap;
 535         handler_data->iclr  = iclr;
 536
 537 out:
 538         return irq;
 539 }
 540
 541 static unsigned int sun4v_build_common(unsigned long sysino,
 542                                        struct irq_chip *chip)
 543 {
 544         struct ino_bucket *bucket;
 545         struct irq_handler_data *handler_data;
 546         unsigned int irq;
 547
 548         BUG_ON(tlb_type != hypervisor);
 549
 550         bucket = &ivector_table[sysino];
 551         irq = bucket_get_irq(__pa(bucket));
 552         if (!irq) {
 553                 irq = irq_alloc(0, sysino);
 554                 bucket_set_irq(__pa(bucket), irq);
 555                 irq_set_chip_and_handler_name(irq, chip, handle_fasteoi_irq,
 556                                               "IVEC");
 557         }
 558
 559         handler_data = irq_get_handler_data(irq);
 560         if (unlikely(handler_data))
 561                 goto out;
 562
 563         handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 564         if (unlikely(!handler_data)) {
 565                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
 566                 prom_halt();
 567         }
 568         irq_set_handler_data(irq, handler_data);
 569
 570         /* Catch accidental accesses to these things.  IMAP/ICLR handling
 571          * is done by hypervisor calls on sun4v platforms, not by direct
 572          * register accesses.
 573          */
 574         handler_data->imap = ~0UL;
 575         handler_data->iclr = ~0UL;
 576
 577 out:
 578         return irq;
 579 }
 580
 581 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
 582 {
 583         unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino);
 584
 585         return sun4v_build_common(sysino, &sun4v_irq);
 586 }
 587
 588 unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
 589 {
 590         struct irq_handler_data *handler_data;
 591         unsigned long hv_err, cookie;
 592         struct ino_bucket *bucket;
 593         unsigned int irq;
 594
 595         bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC);
 596         if (unlikely(!bucket))
 597                 return 0;
 598
 599         /* The only reference we store to the IRQ bucket is
 600          * by physical address which kmemleak can't see, tell
 601          * it that this object explicitly is not a leak and
 602          * should be scanned.
 603          */
 604         kmemleak_not_leak(bucket);
 605
 606         __flush_dcache_range((unsigned long) bucket,
 607                              ((unsigned long) bucket +
 608                               sizeof(struct ino_bucket)));
 609
 610         irq = irq_alloc(devhandle, devino);
 611         bucket_set_irq(__pa(bucket), irq);
 612
 613         irq_set_chip_and_handler_name(irq, &sun4v_virq, handle_fasteoi_irq,
 614                                       "IVEC");
 615
 616         handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 617         if (unlikely(!handler_data))
 618                 return 0;
 619
 620         /* In order to make the LDC channel startup sequence easier,
 621          * especially wrt. locking, we do not let request_irq() enable
 622          * the interrupt.
 623          */
 624         irq_set_status_flags(irq, IRQ_NOAUTOEN);
 625         irq_set_handler_data(irq, handler_data);
 626
 627         /* Catch accidental accesses to these things.  IMAP/ICLR handling
 628          * is done by hypervisor calls on sun4v platforms, not by direct
 629          * register accesses.
 630          */
 631         handler_data->imap = ~0UL;
 632         handler_data->iclr = ~0UL;
 633
 634         cookie = ~__pa(bucket);
 635         hv_err = sun4v_vintr_set_cookie(devhandle, devino, cookie);
 636         if (hv_err) {
 637                 prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] "
 638                             "err=%lu\n", devhandle, devino, hv_err);
 639                 prom_halt();
 640         }
 641
 642         return irq;
 643 }
 644
 645 void ack_bad_irq(unsigned int irq)
 646 {
 647         unsigned int ino = irq_table[irq].dev_ino;
 648
 649         if (!ino)
 650                 ino = 0xdeadbeef;
 651
 652         printk(KERN_CRIT "Unexpected IRQ from ino[%x] irq[%u]\n",
 653                ino, irq);
 654 }
 655
 656 void *hardirq_stack[NR_CPUS];
 657 void *softirq_stack[NR_CPUS];
 658
 659 void __irq_entry handler_irq(int pil, struct pt_regs *regs)
 660 {
 661         unsigned long pstate, bucket_pa;
 662         struct pt_regs *old_regs;
 663         void *orig_sp;
 664
 665         clear_softint(1 << pil);
 666
 667         old_regs = set_irq_regs(regs);
 668         irq_enter();
 669
 670         /* Grab an atomic snapshot of the pending IVECs.  */
 671         __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
 672                              "wrpr      %0, %3, %%pstate\n\t"
 673                              "ldx       [%2], %1\n\t"
 674                              "stx       %%g0, [%2]\n\t"
 675                              "wrpr      %0, 0x0, %%pstate\n\t"
 676                              : "=&r" (pstate), "=&r" (bucket_pa)
 677                              : "r" (irq_work_pa(smp_processor_id())),
 678                                "i" (PSTATE_IE)
 679                              : "memory");
 680
 681         orig_sp = set_hardirq_stack();
 682
 683         while (bucket_pa) {
 684                 unsigned long next_pa;
 685                 unsigned int irq;
 686
 687                 next_pa = bucket_get_chain_pa(bucket_pa);
 688                 irq = bucket_get_irq(bucket_pa);
 689                 bucket_clear_chain_pa(bucket_pa);
 690
 691                 generic_handle_irq(irq);
 692
 693                 bucket_pa = next_pa;
 694         }
 695
 696         restore_hardirq_stack(orig_sp);
 697
 698         irq_exit();
 699         set_irq_regs(old_regs);
 700 }
 701
 702 void do_softirq(void)
 703 {
 704         unsigned long flags;
 705
 706         if (in_interrupt())
 707                 return;
 708
 709         local_irq_save(flags);
 710
 711         if (local_softirq_pending()) {
 712                 void *orig_sp, *sp = softirq_stack[smp_processor_id()];
 713
 714                 sp += THREAD_SIZE - 192 - STACK_BIAS;
 715
 716                 __asm__ __volatile__("mov %%sp, %0\n\t"
 717                                      "mov %1, %%sp"
 718                                      : "=&r" (orig_sp)
 719                                      : "r" (sp));
 720                 __do_softirq();
 721                 __asm__ __volatile__("mov %0, %%sp"
 722                                      : : "r" (orig_sp));
 723         }
 724
 725         local_irq_restore(flags);
 726 }
 727
 728 #ifdef CONFIG_HOTPLUG_CPU
 729 void fixup_irqs(void)
 730 {
 731         unsigned int irq;
 732
 733         for (irq = 0; irq < NR_IRQS; irq++) {
 734                 struct irq_desc *desc = irq_to_desc(irq);
 735                 struct irq_data *data = irq_desc_get_irq_data(desc);
 736                 unsigned long flags;
 737
 738                 raw_spin_lock_irqsave(&desc->lock, flags);
 739                 if (desc->action && !irqd_is_per_cpu(data)) {
 740                         if (data->chip->irq_set_affinity)
 741                                 data->chip->irq_set_affinity(data,
 742                                                              data->affinity,
 743                                                              false);
 744                 }
 745                 raw_spin_unlock_irqrestore(&desc->lock, flags);
 746         }
 747
 748         tick_ops->disable_irq();
 749 }
 750 #endif
 751
 752 struct sun5_timer {
 753         u64     count0;
 754         u64     limit0;
 755         u64     count1;
 756         u64     limit1;
 757 };
 758
 759 static struct sun5_timer *prom_timers;
 760 static u64 prom_limit0, prom_limit1;
 761
 762 static void map_prom_timers(void)
 763 {
 764         struct device_node *dp;
 765         const unsigned int *addr;
 766
 767         /* PROM timer node hangs out in the top level of device siblings... */
 768         dp = of_find_node_by_path("/");
 769         dp = dp->child;
 770         while (dp) {
 771                 if (!strcmp(dp->name, "counter-timer"))
 772                         break;
 773                 dp = dp->sibling;
 774         }
 775
 776         /* Assume if node is not present, PROM uses different tick mechanism
 777          * which we should not care about.
 778          */
 779         if (!dp) {
 780                 prom_timers = (struct sun5_timer *) 0;
 781                 return;
 782         }
 783
 784         /* If PROM is really using this, it must be mapped by him. */
 785         addr = of_get_property(dp, "address", NULL);
 786         if (!addr) {
 787                 prom_printf("PROM does not have timer mapped, trying to continue.\n");
 788                 prom_timers = (struct sun5_timer *) 0;
 789                 return;
 790         }
 791         prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
 792 }
 793
 794 static void kill_prom_timer(void)
 795 {
 796         if (!prom_timers)
 797                 return;
 798
 799         /* Save them away for later. */
 800         prom_limit0 = prom_timers->limit0;
 801         prom_limit1 = prom_timers->limit1;
 802
 803         /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
 804          * We turn both off here just to be paranoid.
 805          */
 806         prom_timers->limit0 = 0;
 807         prom_timers->limit1 = 0;
 808
 809         /* Wheee, eat the interrupt packet too... */
 810         __asm__ __volatile__(
 811 "       mov     0x40, %%g2\n"
 812 "       ldxa    [%%g0] %0, %%g1\n"
 813 "       ldxa    [%%g2] %1, %%g1\n"
 814 "       stxa    %%g0, [%%g0] %0\n"
 815 "       membar  #Sync\n"
 816         : /* no outputs */
 817         : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
 818         : "g1", "g2");
 819 }
 820
 821 void notrace init_irqwork_curcpu(void)
 822 {
 823         int cpu = hard_smp_processor_id();
 824
 825         trap_block[cpu].irq_worklist_pa = 0UL;
 826 }
 827
 828 /* Please be very careful with register_one_mondo() and
 829  * sun4v_register_mondo_queues().
 830  *
 831  * On SMP this gets invoked from the CPU trampoline before
 832  * the cpu has fully taken over the trap table from OBP,
 833  * and it's kernel stack + %g6 thread register state is
 834  * not fully cooked yet.
 835  *
 836  * Therefore you cannot make any OBP calls, not even prom_printf,
 837  * from these two routines.
 838  */
 839 static void __cpuinit notrace register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask)
 840 {
 841         unsigned long num_entries = (qmask + 1) / 64;
 842         unsigned long status;
 843
 844         status = sun4v_cpu_qconf(type, paddr, num_entries);
 845         if (status != HV_EOK) {
 846                 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
 847                             "err %lu\n", type, paddr, num_entries, status);
 848                 prom_halt();
 849         }
 850 }
 851
 852 void __cpuinit notrace sun4v_register_mondo_queues(int this_cpu)
 853 {
 854         struct trap_per_cpu *tb = &trap_block[this_cpu];
 855
 856         register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO,
 857                            tb->cpu_mondo_qmask);
 858         register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO,
 859                            tb->dev_mondo_qmask);
 860         register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR,
 861                            tb->resum_qmask);
 862         register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR,
 863                            tb->nonresum_qmask);
 864 }
 865
 866 /* Each queue region must be a power of 2 multiple of 64 bytes in
 867  * size.  The base real address must be aligned to the size of the
 868  * region.  Thus, an 8KB queue must be 8KB aligned, for example.
 869  */
 870 static void __init alloc_one_queue(unsigned long *pa_ptr, unsigned long qmask)
 871 {
 872         unsigned long size = PAGE_ALIGN(qmask + 1);
 873         unsigned long order = get_order(size);
 874         unsigned long p;
 875
 876         p = __get_free_pages(GFP_KERNEL, order);
 877         if (!p) {
 878                 prom_printf("SUN4V: Error, cannot allocate queue.\n");
 879                 prom_halt();
 880         }
 881
 882         *pa_ptr = __pa(p);
 883 }
 884
 885 static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb)
 886 {
 887 #ifdef CONFIG_SMP
 888         unsigned long page;
 889
 890         BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
 891
 892         page = get_zeroed_page(GFP_KERNEL);
 893         if (!page) {
 894                 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
 895                 prom_halt();
 896         }
 897
 898         tb->cpu_mondo_block_pa = __pa(page);
 899         tb->cpu_list_pa = __pa(page + 64);
 900 #endif
 901 }
 902
 903 /* Allocate mondo and error queues for all possible cpus.  */
 904 static void __init sun4v_init_mondo_queues(void)
 905 {
 906         int cpu;
 907
 908         for_each_possible_cpu(cpu) {
 909                 struct trap_per_cpu *tb = &trap_block[cpu];
 910
 911                 alloc_one_queue(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask);
 912                 alloc_one_queue(&tb->dev_mondo_pa, tb->dev_mondo_qmask);
 913                 alloc_one_queue(&tb->resum_mondo_pa, tb->resum_qmask);
 914                 alloc_one_queue(&tb->resum_kernel_buf_pa, tb->resum_qmask);
 915                 alloc_one_queue(&tb->nonresum_mondo_pa, tb->nonresum_qmask);
 916                 alloc_one_queue(&tb->nonresum_kernel_buf_pa,
 917                                 tb->nonresum_qmask);
 918         }
 919 }
 920
 921 static void __init init_send_mondo_info(void)
 922 {
 923         int cpu;
 924
 925         for_each_possible_cpu(cpu) {
 926                 struct trap_per_cpu *tb = &trap_block[cpu];
 927
 928                 init_cpu_send_mondo_info(tb);
 929         }
 930 }
 931
 932 static struct irqaction timer_irq_action = {
 933         .name = "timer",
 934 };
 935
 936 /* Only invoked on boot processor. */
 937 void __init init_IRQ(void)
 938 {
 939         unsigned long size;
 940
 941         map_prom_timers();
 942         kill_prom_timer();
 943
 944         size = sizeof(struct ino_bucket) * NUM_IVECS;
 945         ivector_table = kzalloc(size, GFP_KERNEL);
 946         if (!ivector_table) {
 947                 prom_printf("Fatal error, cannot allocate ivector_table\n");
 948                 prom_halt();
 949         }
 950         __flush_dcache_range((unsigned long) ivector_table,
 951                              ((unsigned long) ivector_table) + size);
 952
 953         ivector_table_pa = __pa(ivector_table);
 954
 955         if (tlb_type == hypervisor)
 956                 sun4v_init_mondo_queues();
 957
 958         init_send_mondo_info();
 959
 960         if (tlb_type == hypervisor) {
 961                 /* Load up the boot cpu's entries.  */
 962                 sun4v_register_mondo_queues(hard_smp_processor_id());
 963         }
 964
 965         /* We need to clear any IRQ's pending in the soft interrupt
 966          * registers, a spurious one could be left around from the
 967          * PROM timer which we just disabled.
 968          */
 969         clear_softint(get_softint());
 970
 971         /* Now that ivector table is initialized, it is safe
 972          * to receive IRQ vector traps.  We will normally take
 973          * one or two right now, in case some device PROM used
 974          * to boot us wants to speak to us.  We just ignore them.
 975          */
 976         __asm__ __volatile__("rdpr      %%pstate, %%g1\n\t"
 977                              "or        %%g1, %0, %%g1\n\t"
 978                              "wrpr      %%g1, 0x0, %%pstate"
 979                              : /* No outputs */
 980                              : "i" (PSTATE_IE)
 981                              : "g1");
 982
 983         irq_to_desc(0)->action = &timer_irq_action;
 984 }