2 * arch/sh/mm/tlb-pteaex.c
4 * TLB operations for SH-X3 CPUs featuring PTE ASID Extensions.
6 * Copyright (C) 2009 Paul Mundt
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/kernel.h>
15 #include <asm/system.h>
16 #include <asm/mmu_context.h>
17 #include <asm/cacheflush.h>
19 void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
21 unsigned long flags, pteval, vpn;
24 * Handle debugger faulting in for debugee.
26 if (vma && current->active_mm != vma->vm_mm)
29 local_irq_save(flags);
31 /* Set PTEH register */
32 vpn = address & MMU_VPN_MASK;
33 __raw_writel(vpn, MMU_PTEH);
36 __raw_writel(get_asid(), MMU_PTEAEX);
40 /* Set PTEA register */
43 * For the extended mode TLB this is trivial, only the ESZ and
44 * EPR bits need to be written out to PTEA, with the remainder of
45 * the protection bits (with the exception of the compat-mode SZ
46 * and PR bits, which are cleared) being written out in PTEL.
48 __raw_writel(pte.pte_high, MMU_PTEA);
51 /* Set PTEL register */
52 pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
53 #ifdef CONFIG_CACHE_WRITETHROUGH
56 /* conveniently, we want all the software flags to be 0 anyway */
57 __raw_writel(pteval, MMU_PTEL);
60 asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
61 local_irq_restore(flags);
65 * While SH-X2 extended TLB mode splits out the memory-mapped I/UTLB
66 * data arrays, SH-X3 cores with PTEAEX split out the memory-mapped
67 * address arrays. In compat mode the second array is inaccessible, while
68 * in extended mode, the legacy 8-bit ASID field in address array 1 has
69 * undefined behaviour.
71 void __uses_jump_to_uncached local_flush_tlb_one(unsigned long asid,
75 __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT);
76 __raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
81 * Load the entry for 'addr' into the TLB and wire the entry.
83 void tlb_wire_entry(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
85 unsigned long status, flags;
88 local_irq_save(flags);
90 /* Load the entry into the TLB */
91 __update_tlb(vma, addr, pte);
93 /* ... and wire it up. */
94 status = ctrl_inl(MMUCR);
95 urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
99 * Make sure we're not trying to wire the last TLB entry slot.
103 urb = urb % MMUCR_URB_NENTRIES;
105 status |= (urb << MMUCR_URB_SHIFT);
106 ctrl_outl(status, MMUCR);
109 local_irq_restore(flags);
113 * Unwire the last wired TLB entry.
115 * It should also be noted that it is not possible to wire and unwire
116 * TLB entries in an arbitrary order. If you wire TLB entry N, followed
117 * by entry N+1, you must unwire entry N+1 first, then entry N. In this
118 * respect, it works like a stack or LIFO queue.
120 void tlb_unwire_entry(void)
122 unsigned long status, flags;
125 local_irq_save(flags);
127 status = ctrl_inl(MMUCR);
128 urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
129 status &= ~MMUCR_URB;
132 * Make sure we're not trying to unwire a TLB entry when none
135 BUG_ON(urb++ == MMUCR_URB_NENTRIES);
137 urb = urb % MMUCR_URB_NENTRIES;
139 status |= (urb << MMUCR_URB_SHIFT);
140 ctrl_outl(status, MMUCR);
143 local_irq_restore(flags);