4 * Privileged Space Mapping Buffer (PMB) Support.
6 * Copyright (C) 2005 - 2010 Paul Mundt
7 * Copyright (C) 2010 Matt Fleming
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/sysdev.h>
16 #include <linux/cpu.h>
17 #include <linux/module.h>
18 #include <linux/slab.h>
19 #include <linux/bitops.h>
20 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/err.h>
25 #include <asm/sizes.h>
26 #include <asm/system.h>
27 #include <asm/uaccess.h>
28 #include <asm/pgtable.h>
31 #include <asm/mmu_context.h>
33 static void pmb_unmap_entry(struct pmb_entry *);
35 static struct pmb_entry pmb_entry_list[NR_PMB_ENTRIES];
36 static DECLARE_BITMAP(pmb_map, NR_PMB_ENTRIES);
38 static __always_inline unsigned long mk_pmb_entry(unsigned int entry)
40 return (entry & PMB_E_MASK) << PMB_E_SHIFT;
43 static __always_inline unsigned long mk_pmb_addr(unsigned int entry)
45 return mk_pmb_entry(entry) | PMB_ADDR;
48 static __always_inline unsigned long mk_pmb_data(unsigned int entry)
50 return mk_pmb_entry(entry) | PMB_DATA;
53 static int pmb_alloc_entry(void)
58 pos = find_first_zero_bit(pmb_map, NR_PMB_ENTRIES);
60 if (unlikely(pos > NR_PMB_ENTRIES))
63 if (test_and_set_bit(pos, pmb_map))
69 static struct pmb_entry *pmb_alloc(unsigned long vpn, unsigned long ppn,
70 unsigned long flags, int entry)
72 struct pmb_entry *pmbe;
75 if (entry == PMB_NO_ENTRY) {
76 pos = pmb_alloc_entry();
80 if (test_and_set_bit(entry, pmb_map))
81 return ERR_PTR(-ENOSPC);
85 pmbe = &pmb_entry_list[pos];
87 return ERR_PTR(-ENOMEM);
98 static void pmb_free(struct pmb_entry *pmbe)
100 clear_bit(pmbe->entry, pmb_map);
101 pmbe->entry = PMB_NO_ENTRY;
105 * Must be run uncached.
107 static void set_pmb_entry(struct pmb_entry *pmbe)
111 __raw_writel(pmbe->vpn | PMB_V, mk_pmb_addr(pmbe->entry));
113 #ifdef CONFIG_CACHE_WRITETHROUGH
115 * When we are in 32-bit address extended mode, CCR.CB becomes
116 * invalid, so care must be taken to manually adjust cacheable
119 if (likely(pmbe->flags & PMB_C))
120 pmbe->flags |= PMB_WT;
123 __raw_writel(pmbe->ppn | pmbe->flags | PMB_V, mk_pmb_data(pmbe->entry));
128 static void clear_pmb_entry(struct pmb_entry *pmbe)
130 unsigned int entry = pmbe->entry;
136 addr = mk_pmb_addr(entry);
137 __raw_writel(__raw_readl(addr) & ~PMB_V, addr);
139 addr = mk_pmb_data(entry);
140 __raw_writel(__raw_readl(addr) & ~PMB_V, addr);
149 { .size = SZ_512M, .flag = PMB_SZ_512M, },
150 { .size = SZ_128M, .flag = PMB_SZ_128M, },
151 { .size = SZ_64M, .flag = PMB_SZ_64M, },
152 { .size = SZ_16M, .flag = PMB_SZ_16M, },
155 long pmb_remap(unsigned long vaddr, unsigned long phys,
156 unsigned long size, pgprot_t prot)
158 struct pmb_entry *pmbp, *pmbe;
159 unsigned long wanted;
164 flags = pgprot_val(prot);
166 /* Convert typical pgprot value to the PMB equivalent */
167 if (flags & _PAGE_CACHABLE) {
168 if (flags & _PAGE_WT)
173 pmb_flags = PMB_WT | PMB_UB;
179 for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++) {
180 if (size < pmb_sizes[i].size)
183 pmbe = pmb_alloc(vaddr, phys, pmb_flags | pmb_sizes[i].flag,
192 phys += pmb_sizes[i].size;
193 vaddr += pmb_sizes[i].size;
194 size -= pmb_sizes[i].size;
196 pmbe->size = pmb_sizes[i].size;
199 * Link adjacent entries that span multiple PMB entries
200 * for easier tear-down.
208 * Instead of trying smaller sizes on every iteration
209 * (even if we succeed in allocating space), try using
210 * pmb_sizes[i].size again.
215 if (size >= 0x1000000)
218 return wanted - size;
221 pmb_unmap_entry(pmbp);
226 void pmb_unmap(unsigned long addr)
228 struct pmb_entry *pmbe;
231 for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
232 if (test_bit(i, pmb_map)) {
233 pmbe = &pmb_entry_list[i];
234 if (pmbe->vpn == addr) {
235 pmb_unmap_entry(pmbe);
242 static void pmb_unmap_entry(struct pmb_entry *pmbe)
247 if (!test_bit(pmbe->entry, pmb_map)) {
253 struct pmb_entry *pmblink = pmbe;
256 * We may be called before this pmb_entry has been
257 * entered into the PMB table via set_pmb_entry(), but
258 * that's OK because we've allocated a unique slot for
259 * this entry in pmb_alloc() (even if we haven't filled
262 * Therefore, calling clear_pmb_entry() is safe as no
263 * other mapping can be using that slot.
265 clear_pmb_entry(pmbe);
267 pmbe = pmblink->link;
273 static __always_inline unsigned int pmb_ppn_in_range(unsigned long ppn)
275 return ppn >= __pa(memory_start) && ppn < __pa(memory_end);
278 static int pmb_synchronize_mappings(void)
280 unsigned int applied = 0;
281 struct pmb_entry *pmbp = NULL;
284 pr_info("PMB: boot mappings:\n");
287 * Run through the initial boot mappings, log the established
288 * ones, and blow away anything that falls outside of the valid
289 * PPN range. Specifically, we only care about existing mappings
290 * that impact the cached/uncached sections.
292 * Note that touching these can be a bit of a minefield; the boot
293 * loader can establish multi-page mappings with the same caching
294 * attributes, so we need to ensure that we aren't modifying a
295 * mapping that we're presently executing from, or may execute
296 * from in the case of straddling page boundaries.
298 * In the future we will have to tidy up after the boot loader by
299 * jumping between the cached and uncached mappings and tearing
300 * down alternating mappings while executing from the other.
302 for (i = 0; i < NR_PMB_ENTRIES; i++) {
303 unsigned long addr, data;
304 unsigned long addr_val, data_val;
305 unsigned long ppn, vpn, flags;
307 struct pmb_entry *pmbe;
309 addr = mk_pmb_addr(i);
310 data = mk_pmb_data(i);
312 addr_val = __raw_readl(addr);
313 data_val = __raw_readl(data);
316 * Skip over any bogus entries
318 if (!(data_val & PMB_V) || !(addr_val & PMB_V))
321 ppn = data_val & PMB_PFN_MASK;
322 vpn = addr_val & PMB_PFN_MASK;
325 * Only preserve in-range mappings.
327 if (!pmb_ppn_in_range(ppn)) {
329 * Invalidate anything out of bounds.
331 __raw_writel(addr_val & ~PMB_V, addr);
332 __raw_writel(data_val & ~PMB_V, data);
337 * Update the caching attributes if necessary
339 if (data_val & PMB_C) {
340 #if defined(CONFIG_CACHE_WRITETHROUGH)
342 #elif defined(CONFIG_CACHE_WRITEBACK)
345 data_val &= ~(PMB_C | PMB_WT);
347 __raw_writel(data_val, data);
350 size = data_val & PMB_SZ_MASK;
351 flags = size | (data_val & PMB_CACHE_MASK);
353 pmbe = pmb_alloc(vpn, ppn, flags, i);
359 for (j = 0; j < ARRAY_SIZE(pmb_sizes); j++)
360 if (pmb_sizes[j].flag == size)
361 pmbe->size = pmb_sizes[j].size;
364 * Compare the previous entry against the current one to
365 * see if the entries span a contiguous mapping. If so,
366 * setup the entry links accordingly.
368 if (pmbp && ((pmbe->vpn == (pmbp->vpn + pmbp->size)) &&
369 (pmbe->ppn == (pmbp->ppn + pmbp->size))))
374 pr_info("\t0x%08lx -> 0x%08lx [ %ldMB %scached ]\n",
375 vpn >> PAGE_SHIFT, ppn >> PAGE_SHIFT, pmbe->size >> 20,
376 (data_val & PMB_C) ? "" : "un");
381 return (applied == 0);
391 * Sync our software copy of the PMB mappings with those in
392 * hardware. The mappings in the hardware PMB were either set up
393 * by the bootloader or very early on by the kernel.
395 ret = pmb_synchronize_mappings();
396 if (unlikely(ret == 0)) {
401 __raw_writel(0, PMB_IRMCR);
403 /* Flush out the TLB */
404 __raw_writel(__raw_readl(MMUCR) | MMUCR_TI, MMUCR);
411 bool __in_29bit_mode(void)
413 return (__raw_readl(PMB_PASCR) & PASCR_SE) == 0;
416 static int pmb_seq_show(struct seq_file *file, void *iter)
420 seq_printf(file, "V: Valid, C: Cacheable, WT: Write-Through\n"
421 "CB: Copy-Back, B: Buffered, UB: Unbuffered\n");
422 seq_printf(file, "ety vpn ppn size flags\n");
424 for (i = 0; i < NR_PMB_ENTRIES; i++) {
425 unsigned long addr, data;
429 addr = __raw_readl(mk_pmb_addr(i));
430 data = __raw_readl(mk_pmb_data(i));
432 size = data & PMB_SZ_MASK;
433 sz_str = (size == PMB_SZ_16M) ? " 16MB":
434 (size == PMB_SZ_64M) ? " 64MB":
435 (size == PMB_SZ_128M) ? "128MB":
438 /* 02: V 0x88 0x08 128MB C CB B */
439 seq_printf(file, "%02d: %c 0x%02lx 0x%02lx %s %c %s %s\n",
440 i, ((addr & PMB_V) && (data & PMB_V)) ? 'V' : ' ',
441 (addr >> 24) & 0xff, (data >> 24) & 0xff,
442 sz_str, (data & PMB_C) ? 'C' : ' ',
443 (data & PMB_WT) ? "WT" : "CB",
444 (data & PMB_UB) ? "UB" : " B");
450 static int pmb_debugfs_open(struct inode *inode, struct file *file)
452 return single_open(file, pmb_seq_show, NULL);
455 static const struct file_operations pmb_debugfs_fops = {
456 .owner = THIS_MODULE,
457 .open = pmb_debugfs_open,
460 .release = single_release,
463 static int __init pmb_debugfs_init(void)
465 struct dentry *dentry;
467 dentry = debugfs_create_file("pmb", S_IFREG | S_IRUGO,
468 sh_debugfs_root, NULL, &pmb_debugfs_fops);
472 return PTR_ERR(dentry);
476 postcore_initcall(pmb_debugfs_init);
479 static int pmb_sysdev_suspend(struct sys_device *dev, pm_message_t state)
481 static pm_message_t prev_state;
484 /* Restore the PMB after a resume from hibernation */
485 if (state.event == PM_EVENT_ON &&
486 prev_state.event == PM_EVENT_FREEZE) {
487 struct pmb_entry *pmbe;
488 for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
489 if (test_bit(i, pmb_map)) {
490 pmbe = &pmb_entry_list[i];
499 static int pmb_sysdev_resume(struct sys_device *dev)
501 return pmb_sysdev_suspend(dev, PMSG_ON);
504 static struct sysdev_driver pmb_sysdev_driver = {
505 .suspend = pmb_sysdev_suspend,
506 .resume = pmb_sysdev_resume,
509 static int __init pmb_sysdev_init(void)
511 return sysdev_driver_register(&cpu_sysdev_class, &pmb_sysdev_driver);
513 subsys_initcall(pmb_sysdev_init);