arch/sh/kernel/traps_32.c

   1 /*
   2  * 'traps.c' handles hardware traps and faults after we have saved some
   3  * state in 'entry.S'.
   4  *
   5  *  SuperH version: Copyright (C) 1999 Niibe Yutaka
   6  *                  Copyright (C) 2000 Philipp Rumpf
   7  *                  Copyright (C) 2000 David Howells
   8  *                  Copyright (C) 2002 - 2007 Paul Mundt
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/ptrace.h>
  16 #include <linux/hardirq.h>
  17 #include <linux/init.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/module.h>
  20 #include <linux/kallsyms.h>
  21 #include <linux/io.h>
  22 #include <linux/bug.h>
  23 #include <linux/debug_locks.h>
  24 #include <linux/kdebug.h>
  25 #include <linux/kexec.h>
  26 #include <linux/limits.h>
  27 #include <linux/sysfs.h>
  28 #include <linux/uaccess.h>
  29 #include <asm/system.h>
  30 #include <asm/alignment.h>
  31 #include <asm/fpu.h>
  32 #include <asm/kprobes.h>
  33 #include <asm/sh_bios.h>
  34
  35 #ifdef CONFIG_CPU_SH2
  36 # define TRAP_RESERVED_INST     4
  37 # define TRAP_ILLEGAL_SLOT_INST 6
  38 # define TRAP_ADDRESS_ERROR     9
  39 # ifdef CONFIG_CPU_SH2A
  40 #  define TRAP_UBC              12
  41 #  define TRAP_FPU_ERROR        13
  42 #  define TRAP_DIVZERO_ERROR    17
  43 #  define TRAP_DIVOVF_ERROR     18
  44 # endif
  45 #else
  46 #define TRAP_RESERVED_INST      12
  47 #define TRAP_ILLEGAL_SLOT_INST  13
  48 #endif
  49
  50 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
  51 {
  52         unsigned long p;
  53         int i;
  54
  55         printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
  56
  57         for (p = bottom & ~31; p < top; ) {
  58                 printk("%04lx: ", p & 0xffff);
  59
  60                 for (i = 0; i < 8; i++, p += 4) {
  61                         unsigned int val;
  62
  63                         if (p < bottom || p >= top)
  64                                 printk("         ");
  65                         else {
  66                                 if (__get_user(val, (unsigned int __user *)p)) {
  67                                         printk("\n");
  68                                         return;
  69                                 }
  70                                 printk("%08x ", val);
  71                         }
  72                 }
  73                 printk("\n");
  74         }
  75 }
  76
  77 static DEFINE_SPINLOCK(die_lock);
  78
  79 void die(const char * str, struct pt_regs * regs, long err)
  80 {
  81         static int die_counter;
  82
  83         oops_enter();
  84
  85         spin_lock_irq(&die_lock);
  86         console_verbose();
  87         bust_spinlocks(1);
  88
  89         printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
  90         sysfs_printk_last_file();
  91         print_modules();
  92         show_regs(regs);
  93
  94         printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
  95                         task_pid_nr(current), task_stack_page(current) + 1);
  96
  97         if (!user_mode(regs) || in_interrupt())
  98                 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
  99                          (unsigned long)task_stack_page(current));
 100
 101         notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
 102
 103         bust_spinlocks(0);
 104         add_taint(TAINT_DIE);
 105         spin_unlock_irq(&die_lock);
 106         oops_exit();
 107
 108         if (kexec_should_crash(current))
 109                 crash_kexec(regs);
 110
 111         if (in_interrupt())
 112                 panic("Fatal exception in interrupt");
 113
 114         if (panic_on_oops)
 115                 panic("Fatal exception");
 116
 117         do_exit(SIGSEGV);
 118 }
 119
 120 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
 121                                  long err)
 122 {
 123         if (!user_mode(regs))
 124                 die(str, regs, err);
 125 }
 126
 127 /*
 128  * try and fix up kernelspace address errors
 129  * - userspace errors just cause EFAULT to be returned, resulting in SEGV
 130  * - kernel/userspace interfaces cause a jump to an appropriate handler
 131  * - other kernel errors are bad
 132  */
 133 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
 134 {
 135         if (!user_mode(regs)) {
 136                 const struct exception_table_entry *fixup;
 137                 fixup = search_exception_tables(regs->pc);
 138                 if (fixup) {
 139                         regs->pc = fixup->fixup;
 140                         return;
 141                 }
 142
 143                 die(str, regs, err);
 144         }
 145 }
 146
 147 static inline void sign_extend(unsigned int count, unsigned char *dst)
 148 {
 149 #ifdef __LITTLE_ENDIAN__
 150         if ((count == 1) && dst[0] & 0x80) {
 151                 dst[1] = 0xff;
 152                 dst[2] = 0xff;
 153                 dst[3] = 0xff;
 154         }
 155         if ((count == 2) && dst[1] & 0x80) {
 156                 dst[2] = 0xff;
 157                 dst[3] = 0xff;
 158         }
 159 #else
 160         if ((count == 1) && dst[3] & 0x80) {
 161                 dst[2] = 0xff;
 162                 dst[1] = 0xff;
 163                 dst[0] = 0xff;
 164         }
 165         if ((count == 2) && dst[2] & 0x80) {
 166                 dst[1] = 0xff;
 167                 dst[0] = 0xff;
 168         }
 169 #endif
 170 }
 171
 172 static struct mem_access user_mem_access = {
 173         copy_from_user,
 174         copy_to_user,
 175 };
 176
 177 /*
 178  * handle an instruction that does an unaligned memory access by emulating the
 179  * desired behaviour
 180  * - note that PC _may not_ point to the faulting instruction
 181  *   (if that instruction is in a branch delay slot)
 182  * - return 0 if emulation okay, -EFAULT on existential error
 183  */
 184 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
 185                                 struct mem_access *ma)
 186 {
 187         int ret, index, count;
 188         unsigned long *rm, *rn;
 189         unsigned char *src, *dst;
 190         unsigned char __user *srcu, *dstu;
 191
 192         index = (instruction>>8)&15;    /* 0x0F00 */
 193         rn = &regs->regs[index];
 194
 195         index = (instruction>>4)&15;    /* 0x00F0 */
 196         rm = &regs->regs[index];
 197
 198         count = 1<<(instruction&3);
 199
 200         switch (count) {
 201         case 1: inc_unaligned_byte_access(); break;
 202         case 2: inc_unaligned_word_access(); break;
 203         case 4: inc_unaligned_dword_access(); break;
 204         case 8: inc_unaligned_multi_access(); break;
 205         }
 206
 207         ret = -EFAULT;
 208         switch (instruction>>12) {
 209         case 0: /* mov.[bwl] to/from memory via r0+rn */
 210                 if (instruction & 8) {
 211                         /* from memory */
 212                         srcu = (unsigned char __user *)*rm;
 213                         srcu += regs->regs[0];
 214                         dst = (unsigned char *)rn;
 215                         *(unsigned long *)dst = 0;
 216
 217 #if !defined(__LITTLE_ENDIAN__)
 218                         dst += 4-count;
 219 #endif
 220                         if (ma->from(dst, srcu, count))
 221                                 goto fetch_fault;
 222
 223                         sign_extend(count, dst);
 224                 } else {
 225                         /* to memory */
 226                         src = (unsigned char *)rm;
 227 #if !defined(__LITTLE_ENDIAN__)
 228                         src += 4-count;
 229 #endif
 230                         dstu = (unsigned char __user *)*rn;
 231                         dstu += regs->regs[0];
 232
 233                         if (ma->to(dstu, src, count))
 234                                 goto fetch_fault;
 235                 }
 236                 ret = 0;
 237                 break;
 238
 239         case 1: /* mov.l Rm,@(disp,Rn) */
 240                 src = (unsigned char*) rm;
 241                 dstu = (unsigned char __user *)*rn;
 242                 dstu += (instruction&0x000F)<<2;
 243
 244                 if (ma->to(dstu, src, 4))
 245                         goto fetch_fault;
 246                 ret = 0;
 247                 break;
 248
 249         case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
 250                 if (instruction & 4)
 251                         *rn -= count;
 252                 src = (unsigned char*) rm;
 253                 dstu = (unsigned char __user *)*rn;
 254 #if !defined(__LITTLE_ENDIAN__)
 255                 src += 4-count;
 256 #endif
 257                 if (ma->to(dstu, src, count))
 258                         goto fetch_fault;
 259                 ret = 0;
 260                 break;
 261
 262         case 5: /* mov.l @(disp,Rm),Rn */
 263                 srcu = (unsigned char __user *)*rm;
 264                 srcu += (instruction & 0x000F) << 2;
 265                 dst = (unsigned char *)rn;
 266                 *(unsigned long *)dst = 0;
 267
 268                 if (ma->from(dst, srcu, 4))
 269                         goto fetch_fault;
 270                 ret = 0;
 271                 break;
 272
 273         case 6: /* mov.[bwl] from memory, possibly with post-increment */
 274                 srcu = (unsigned char __user *)*rm;
 275                 if (instruction & 4)
 276                         *rm += count;
 277                 dst = (unsigned char*) rn;
 278                 *(unsigned long*)dst = 0;
 279
 280 #if !defined(__LITTLE_ENDIAN__)
 281                 dst += 4-count;
 282 #endif
 283                 if (ma->from(dst, srcu, count))
 284                         goto fetch_fault;
 285                 sign_extend(count, dst);
 286                 ret = 0;
 287                 break;
 288
 289         case 8:
 290                 switch ((instruction&0xFF00)>>8) {
 291                 case 0x81: /* mov.w R0,@(disp,Rn) */
 292                         src = (unsigned char *) &regs->regs[0];
 293 #if !defined(__LITTLE_ENDIAN__)
 294                         src += 2;
 295 #endif
 296                         dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
 297                         dstu += (instruction & 0x000F) << 1;
 298
 299                         if (ma->to(dstu, src, 2))
 300                                 goto fetch_fault;
 301                         ret = 0;
 302                         break;
 303
 304                 case 0x85: /* mov.w @(disp,Rm),R0 */
 305                         srcu = (unsigned char __user *)*rm;
 306                         srcu += (instruction & 0x000F) << 1;
 307                         dst = (unsigned char *) &regs->regs[0];
 308                         *(unsigned long *)dst = 0;
 309
 310 #if !defined(__LITTLE_ENDIAN__)
 311                         dst += 2;
 312 #endif
 313                         if (ma->from(dst, srcu, 2))
 314                                 goto fetch_fault;
 315                         sign_extend(2, dst);
 316                         ret = 0;
 317                         break;
 318                 }
 319                 break;
 320         }
 321         return ret;
 322
 323  fetch_fault:
 324         /* Argh. Address not only misaligned but also non-existent.
 325          * Raise an EFAULT and see if it's trapped
 326          */
 327         die_if_no_fixup("Fault in unaligned fixup", regs, 0);
 328         return -EFAULT;
 329 }
 330
 331 /*
 332  * emulate the instruction in the delay slot
 333  * - fetches the instruction from PC+2
 334  */
 335 static inline int handle_delayslot(struct pt_regs *regs,
 336                                    insn_size_t old_instruction,
 337                                    struct mem_access *ma)
 338 {
 339         insn_size_t instruction;
 340         void __user *addr = (void __user *)(regs->pc +
 341                 instruction_size(old_instruction));
 342
 343         if (copy_from_user(&instruction, addr, sizeof(instruction))) {
 344                 /* the instruction-fetch faulted */
 345                 if (user_mode(regs))
 346                         return -EFAULT;
 347
 348                 /* kernel */
 349                 die("delay-slot-insn faulting in handle_unaligned_delayslot",
 350                     regs, 0);
 351         }
 352
 353         return handle_unaligned_ins(instruction, regs, ma);
 354 }
 355
 356 /*
 357  * handle an instruction that does an unaligned memory access
 358  * - have to be careful of branch delay-slot instructions that fault
 359  *  SH3:
 360  *   - if the branch would be taken PC points to the branch
 361  *   - if the branch would not be taken, PC points to delay-slot
 362  *  SH4:
 363  *   - PC always points to delayed branch
 364  * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
 365  */
 366
 367 /* Macros to determine offset from current PC for branch instructions */
 368 /* Explicit type coercion is used to force sign extension where needed */
 369 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
 370 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
 371
 372 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
 373                             struct mem_access *ma, int expected)
 374 {
 375         u_int rm;
 376         int ret, index;
 377
 378         /*
 379          * XXX: We can't handle mixed 16/32-bit instructions yet
 380          */
 381         if (instruction_size(instruction) != 2)
 382                 return -EINVAL;
 383
 384         index = (instruction>>8)&15;    /* 0x0F00 */
 385         rm = regs->regs[index];
 386
 387         /* shout about fixups */
 388         if (!expected)
 389                 unaligned_fixups_notify(current, instruction, regs);
 390
 391         ret = -EFAULT;
 392         switch (instruction&0xF000) {
 393         case 0x0000:
 394                 if (instruction==0x000B) {
 395                         /* rts */
 396                         ret = handle_delayslot(regs, instruction, ma);
 397                         if (ret==0)
 398                                 regs->pc = regs->pr;
 399                 }
 400                 else if ((instruction&0x00FF)==0x0023) {
 401                         /* braf @Rm */
 402                         ret = handle_delayslot(regs, instruction, ma);
 403                         if (ret==0)
 404                                 regs->pc += rm + 4;
 405                 }
 406                 else if ((instruction&0x00FF)==0x0003) {
 407                         /* bsrf @Rm */
 408                         ret = handle_delayslot(regs, instruction, ma);
 409                         if (ret==0) {
 410                                 regs->pr = regs->pc + 4;
 411                                 regs->pc += rm + 4;
 412                         }
 413                 }
 414                 else {
 415                         /* mov.[bwl] to/from memory via r0+rn */
 416                         goto simple;
 417                 }
 418                 break;
 419
 420         case 0x1000: /* mov.l Rm,@(disp,Rn) */
 421                 goto simple;
 422
 423         case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
 424                 goto simple;
 425
 426         case 0x4000:
 427                 if ((instruction&0x00FF)==0x002B) {
 428                         /* jmp @Rm */
 429                         ret = handle_delayslot(regs, instruction, ma);
 430                         if (ret==0)
 431                                 regs->pc = rm;
 432                 }
 433                 else if ((instruction&0x00FF)==0x000B) {
 434                         /* jsr @Rm */
 435                         ret = handle_delayslot(regs, instruction, ma);
 436                         if (ret==0) {
 437                                 regs->pr = regs->pc + 4;
 438                                 regs->pc = rm;
 439                         }
 440                 }
 441                 else {
 442                         /* mov.[bwl] to/from memory via r0+rn */
 443                         goto simple;
 444                 }
 445                 break;
 446
 447         case 0x5000: /* mov.l @(disp,Rm),Rn */
 448                 goto simple;
 449
 450         case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
 451                 goto simple;
 452
 453         case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
 454                 switch (instruction&0x0F00) {
 455                 case 0x0100: /* mov.w R0,@(disp,Rm) */
 456                         goto simple;
 457                 case 0x0500: /* mov.w @(disp,Rm),R0 */
 458                         goto simple;
 459                 case 0x0B00: /* bf   lab - no delayslot*/
 460                         break;
 461                 case 0x0F00: /* bf/s lab */
 462                         ret = handle_delayslot(regs, instruction, ma);
 463                         if (ret==0) {
 464 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 465                                 if ((regs->sr & 0x00000001) != 0)
 466                                         regs->pc += 4; /* next after slot */
 467                                 else
 468 #endif
 469                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 470                         }
 471                         break;
 472                 case 0x0900: /* bt   lab - no delayslot */
 473                         break;
 474                 case 0x0D00: /* bt/s lab */
 475                         ret = handle_delayslot(regs, instruction, ma);
 476                         if (ret==0) {
 477 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 478                                 if ((regs->sr & 0x00000001) == 0)
 479                                         regs->pc += 4; /* next after slot */
 480                                 else
 481 #endif
 482                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 483                         }
 484                         break;
 485                 }
 486                 break;
 487
 488         case 0xA000: /* bra label */
 489                 ret = handle_delayslot(regs, instruction, ma);
 490                 if (ret==0)
 491                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 492                 break;
 493
 494         case 0xB000: /* bsr label */
 495                 ret = handle_delayslot(regs, instruction, ma);
 496                 if (ret==0) {
 497                         regs->pr = regs->pc + 4;
 498                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 499                 }
 500                 break;
 501         }
 502         return ret;
 503
 504         /* handle non-delay-slot instruction */
 505  simple:
 506         ret = handle_unaligned_ins(instruction, regs, ma);
 507         if (ret==0)
 508                 regs->pc += instruction_size(instruction);
 509         return ret;
 510 }
 511
 512 /*
 513  * Handle various address error exceptions:
 514  *  - instruction address error:
 515  *       misaligned PC
 516  *       PC >= 0x80000000 in user mode
 517  *  - data address error (read and write)
 518  *       misaligned data access
 519  *       access to >= 0x80000000 is user mode
 520  * Unfortuntaly we can't distinguish between instruction address error
 521  * and data address errors caused by read accesses.
 522  */
 523 asmlinkage void do_address_error(struct pt_regs *regs,
 524                                  unsigned long writeaccess,
 525                                  unsigned long address)
 526 {
 527         unsigned long error_code = 0;
 528         mm_segment_t oldfs;
 529         siginfo_t info;
 530         insn_size_t instruction;
 531         int tmp;
 532
 533         /* Intentional ifdef */
 534 #ifdef CONFIG_CPU_HAS_SR_RB
 535         error_code = lookup_exception_vector();
 536 #endif
 537
 538         oldfs = get_fs();
 539
 540         if (user_mode(regs)) {
 541                 int si_code = BUS_ADRERR;
 542                 unsigned int user_action;
 543
 544                 local_irq_enable();
 545                 inc_unaligned_user_access();
 546
 547                 set_fs(USER_DS);
 548                 if (copy_from_user(&instruction, (insn_size_t *)(regs->pc & ~1),
 549                                    sizeof(instruction))) {
 550                         set_fs(oldfs);
 551                         goto uspace_segv;
 552                 }
 553                 set_fs(oldfs);
 554
 555                 /* shout about userspace fixups */
 556                 unaligned_fixups_notify(current, instruction, regs);
 557
 558                 user_action = unaligned_user_action();
 559                 if (user_action & UM_FIXUP)
 560                         goto fixup;
 561                 if (user_action & UM_SIGNAL)
 562                         goto uspace_segv;
 563                 else {
 564                         /* ignore */
 565                         regs->pc += instruction_size(instruction);
 566                         return;
 567                 }
 568
 569 fixup:
 570                 /* bad PC is not something we can fix */
 571                 if (regs->pc & 1) {
 572                         si_code = BUS_ADRALN;
 573                         goto uspace_segv;
 574                 }
 575
 576                 set_fs(USER_DS);
 577                 tmp = handle_unaligned_access(instruction, regs,
 578                                               &user_mem_access, 0);
 579                 set_fs(oldfs);
 580
 581                 if (tmp == 0)
 582                         return; /* sorted */
 583 uspace_segv:
 584                 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
 585                        "access (PC %lx PR %lx)\n", current->comm, regs->pc,
 586                        regs->pr);
 587
 588                 info.si_signo = SIGBUS;
 589                 info.si_errno = 0;
 590                 info.si_code = si_code;
 591                 info.si_addr = (void __user *)address;
 592                 force_sig_info(SIGBUS, &info, current);
 593         } else {
 594                 inc_unaligned_kernel_access();
 595
 596                 if (regs->pc & 1)
 597                         die("unaligned program counter", regs, error_code);
 598
 599                 set_fs(KERNEL_DS);
 600                 if (copy_from_user(&instruction, (void __user *)(regs->pc),
 601                                    sizeof(instruction))) {
 602                         /* Argh. Fault on the instruction itself.
 603                            This should never happen non-SMP
 604                         */
 605                         set_fs(oldfs);
 606                         die("insn faulting in do_address_error", regs, 0);
 607                 }
 608
 609                 unaligned_fixups_notify(current, instruction, regs);
 610
 611                 handle_unaligned_access(instruction, regs,
 612                                         &user_mem_access, 0);
 613                 set_fs(oldfs);
 614         }
 615 }
 616
 617 #ifdef CONFIG_SH_DSP
 618 /*
 619  *      SH-DSP support gerg@snapgear.com.
 620  */
 621 int is_dsp_inst(struct pt_regs *regs)
 622 {
 623         unsigned short inst = 0;
 624
 625         /*
 626          * Safe guard if DSP mode is already enabled or we're lacking
 627          * the DSP altogether.
 628          */
 629         if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
 630                 return 0;
 631
 632         get_user(inst, ((unsigned short *) regs->pc));
 633
 634         inst &= 0xf000;
 635
 636         /* Check for any type of DSP or support instruction */
 637         if ((inst == 0xf000) || (inst == 0x4000))
 638                 return 1;
 639
 640         return 0;
 641 }
 642 #else
 643 #define is_dsp_inst(regs)       (0)
 644 #endif /* CONFIG_SH_DSP */
 645
 646 #ifdef CONFIG_CPU_SH2A
 647 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
 648                                 unsigned long r6, unsigned long r7,
 649                                 struct pt_regs __regs)
 650 {
 651         siginfo_t info;
 652
 653         switch (r4) {
 654         case TRAP_DIVZERO_ERROR:
 655                 info.si_code = FPE_INTDIV;
 656                 break;
 657         case TRAP_DIVOVF_ERROR:
 658                 info.si_code = FPE_INTOVF;
 659                 break;
 660         }
 661
 662         force_sig_info(SIGFPE, &info, current);
 663 }
 664 #endif
 665
 666 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
 667                                 unsigned long r6, unsigned long r7,
 668                                 struct pt_regs __regs)
 669 {
 670         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 671         unsigned long error_code;
 672         struct task_struct *tsk = current;
 673
 674 #ifdef CONFIG_SH_FPU_EMU
 675         unsigned short inst = 0;
 676         int err;
 677
 678         get_user(inst, (unsigned short*)regs->pc);
 679
 680         err = do_fpu_inst(inst, regs);
 681         if (!err) {
 682                 regs->pc += instruction_size(inst);
 683                 return;
 684         }
 685         /* not a FPU inst. */
 686 #endif
 687
 688 #ifdef CONFIG_SH_DSP
 689         /* Check if it's a DSP instruction */
 690         if (is_dsp_inst(regs)) {
 691                 /* Enable DSP mode, and restart instruction. */
 692                 regs->sr |= SR_DSP;
 693                 /* Save DSP mode */
 694                 tsk->thread.dsp_status.status |= SR_DSP;
 695                 return;
 696         }
 697 #endif
 698
 699         error_code = lookup_exception_vector();
 700
 701         local_irq_enable();
 702         force_sig(SIGILL, tsk);
 703         die_if_no_fixup("reserved instruction", regs, error_code);
 704 }
 705
 706 #ifdef CONFIG_SH_FPU_EMU
 707 static int emulate_branch(unsigned short inst, struct pt_regs *regs)
 708 {
 709         /*
 710          * bfs: 8fxx: PC+=d*2+4;
 711          * bts: 8dxx: PC+=d*2+4;
 712          * bra: axxx: PC+=D*2+4;
 713          * bsr: bxxx: PC+=D*2+4  after PR=PC+4;
 714          * braf:0x23: PC+=Rn*2+4;
 715          * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
 716          * jmp: 4x2b: PC=Rn;
 717          * jsr: 4x0b: PC=Rn      after PR=PC+4;
 718          * rts: 000b: PC=PR;
 719          */
 720         if (((inst & 0xf000) == 0xb000)  ||     /* bsr */
 721             ((inst & 0xf0ff) == 0x0003)  ||     /* bsrf */
 722             ((inst & 0xf0ff) == 0x400b))        /* jsr */
 723                 regs->pr = regs->pc + 4;
 724
 725         if ((inst & 0xfd00) == 0x8d00) {        /* bfs, bts */
 726                 regs->pc += SH_PC_8BIT_OFFSET(inst);
 727                 return 0;
 728         }
 729
 730         if ((inst & 0xe000) == 0xa000) {        /* bra, bsr */
 731                 regs->pc += SH_PC_12BIT_OFFSET(inst);
 732                 return 0;
 733         }
 734
 735         if ((inst & 0xf0df) == 0x0003) {        /* braf, bsrf */
 736                 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
 737                 return 0;
 738         }
 739
 740         if ((inst & 0xf0df) == 0x400b) {        /* jmp, jsr */
 741                 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
 742                 return 0;
 743         }
 744
 745         if ((inst & 0xffff) == 0x000b) {        /* rts */
 746                 regs->pc = regs->pr;
 747                 return 0;
 748         }
 749
 750         return 1;
 751 }
 752 #endif
 753
 754 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
 755                                 unsigned long r6, unsigned long r7,
 756                                 struct pt_regs __regs)
 757 {
 758         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 759         unsigned long inst;
 760         struct task_struct *tsk = current;
 761
 762         if (kprobe_handle_illslot(regs->pc) == 0)
 763                 return;
 764
 765 #ifdef CONFIG_SH_FPU_EMU
 766         get_user(inst, (unsigned short *)regs->pc + 1);
 767         if (!do_fpu_inst(inst, regs)) {
 768                 get_user(inst, (unsigned short *)regs->pc);
 769                 if (!emulate_branch(inst, regs))
 770                         return;
 771                 /* fault in branch.*/
 772         }
 773         /* not a FPU inst. */
 774 #endif
 775
 776         inst = lookup_exception_vector();
 777
 778         local_irq_enable();
 779         force_sig(SIGILL, tsk);
 780         die_if_no_fixup("illegal slot instruction", regs, inst);
 781 }
 782
 783 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
 784                                    unsigned long r6, unsigned long r7,
 785                                    struct pt_regs __regs)
 786 {
 787         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 788         long ex;
 789
 790         ex = lookup_exception_vector();
 791         die_if_kernel("exception", regs, ex);
 792 }
 793
 794 void __cpuinit per_cpu_trap_init(void)
 795 {
 796         extern void *vbr_base;
 797
 798         /* NOTE: The VBR value should be at P1
 799            (or P2, virtural "fixed" address space).
 800            It's definitely should not in physical address.  */
 801
 802         asm volatile("ldc       %0, vbr"
 803                      : /* no output */
 804                      : "r" (&vbr_base)
 805                      : "memory");
 806 }
 807
 808 void *set_exception_table_vec(unsigned int vec, void *handler)
 809 {
 810         extern void *exception_handling_table[];
 811         void *old_handler;
 812
 813         old_handler = exception_handling_table[vec];
 814         exception_handling_table[vec] = handler;
 815         return old_handler;
 816 }
 817
 818 void __init trap_init(void)
 819 {
 820         set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
 821         set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
 822
 823 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
 824     defined(CONFIG_SH_FPU_EMU)
 825         /*
 826          * For SH-4 lacking an FPU, treat floating point instructions as
 827          * reserved. They'll be handled in the math-emu case, or faulted on
 828          * otherwise.
 829          */
 830         set_exception_table_evt(0x800, do_reserved_inst);
 831         set_exception_table_evt(0x820, do_illegal_slot_inst);
 832 #elif defined(CONFIG_SH_FPU)
 833         set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
 834         set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
 835 #endif
 836
 837 #ifdef CONFIG_CPU_SH2
 838         set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
 839 #endif
 840 #ifdef CONFIG_CPU_SH2A
 841         set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
 842         set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
 843 #ifdef CONFIG_SH_FPU
 844         set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
 845 #endif
 846 #endif
 847
 848 #ifdef TRAP_UBC
 849         set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler);
 850 #endif
 851
 852         /* Save off the BIOS VBR, if there is one */
 853         sh_bios_vbr_init();
 854
 855         /* Setup VBR for boot cpu */
 856         per_cpu_trap_init();
 857 }
 858
 859 void show_stack(struct task_struct *tsk, unsigned long *sp)
 860 {
 861         unsigned long stack;
 862
 863         if (!tsk)
 864                 tsk = current;
 865         if (tsk == current)
 866                 sp = (unsigned long *)current_stack_pointer;
 867         else
 868                 sp = (unsigned long *)tsk->thread.sp;
 869
 870         stack = (unsigned long)sp;
 871         dump_mem("Stack: ", stack, THREAD_SIZE +
 872                  (unsigned long)task_stack_page(tsk));
 873         show_trace(tsk, sp, NULL);
 874 }
 875
 876 void dump_stack(void)
 877 {
 878         show_stack(NULL, NULL);
 879 }
 880 EXPORT_SYMBOL(dump_stack);