2 * 'traps.c' handles hardware traps and faults after we have saved some
5 * SuperH version: Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2000 Philipp Rumpf
7 * Copyright (C) 2000 David Howells
8 * Copyright (C) 2002 - 2010 Paul Mundt
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/kernel.h>
15 #include <linux/ptrace.h>
16 #include <linux/hardirq.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/module.h>
20 #include <linux/kallsyms.h>
22 #include <linux/bug.h>
23 #include <linux/debug_locks.h>
24 #include <linux/kdebug.h>
25 #include <linux/kexec.h>
26 #include <linux/limits.h>
27 #include <linux/sysfs.h>
28 #include <linux/uaccess.h>
29 #include <linux/perf_event.h>
30 #include <asm/system.h>
31 #include <asm/alignment.h>
33 #include <asm/kprobes.h>
36 # define TRAP_RESERVED_INST 4
37 # define TRAP_ILLEGAL_SLOT_INST 6
38 # define TRAP_ADDRESS_ERROR 9
39 # ifdef CONFIG_CPU_SH2A
41 # define TRAP_FPU_ERROR 13
42 # define TRAP_DIVZERO_ERROR 17
43 # define TRAP_DIVOVF_ERROR 18
46 #define TRAP_RESERVED_INST 12
47 #define TRAP_ILLEGAL_SLOT_INST 13
50 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
55 printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
57 for (p = bottom & ~31; p < top; ) {
58 printk("%04lx: ", p & 0xffff);
60 for (i = 0; i < 8; i++, p += 4) {
63 if (p < bottom || p >= top)
66 if (__get_user(val, (unsigned int __user *)p)) {
77 static DEFINE_SPINLOCK(die_lock);
79 void die(const char * str, struct pt_regs * regs, long err)
81 static int die_counter;
85 spin_lock_irq(&die_lock);
89 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
93 printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
94 task_pid_nr(current), task_stack_page(current) + 1);
96 if (!user_mode(regs) || in_interrupt())
97 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
98 (unsigned long)task_stack_page(current));
100 notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
103 add_taint(TAINT_DIE);
104 spin_unlock_irq(&die_lock);
107 if (kexec_should_crash(current))
111 panic("Fatal exception in interrupt");
114 panic("Fatal exception");
119 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
122 if (!user_mode(regs))
127 * try and fix up kernelspace address errors
128 * - userspace errors just cause EFAULT to be returned, resulting in SEGV
129 * - kernel/userspace interfaces cause a jump to an appropriate handler
130 * - other kernel errors are bad
132 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
134 if (!user_mode(regs)) {
135 const struct exception_table_entry *fixup;
136 fixup = search_exception_tables(regs->pc);
138 regs->pc = fixup->fixup;
146 static inline void sign_extend(unsigned int count, unsigned char *dst)
148 #ifdef __LITTLE_ENDIAN__
149 if ((count == 1) && dst[0] & 0x80) {
154 if ((count == 2) && dst[1] & 0x80) {
159 if ((count == 1) && dst[3] & 0x80) {
164 if ((count == 2) && dst[2] & 0x80) {
171 static struct mem_access user_mem_access = {
177 * handle an instruction that does an unaligned memory access by emulating the
179 * - note that PC _may not_ point to the faulting instruction
180 * (if that instruction is in a branch delay slot)
181 * - return 0 if emulation okay, -EFAULT on existential error
183 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
184 struct mem_access *ma)
186 int ret, index, count;
187 unsigned long *rm, *rn;
188 unsigned char *src, *dst;
189 unsigned char __user *srcu, *dstu;
191 index = (instruction>>8)&15; /* 0x0F00 */
192 rn = ®s->regs[index];
194 index = (instruction>>4)&15; /* 0x00F0 */
195 rm = ®s->regs[index];
197 count = 1<<(instruction&3);
200 case 1: inc_unaligned_byte_access(); break;
201 case 2: inc_unaligned_word_access(); break;
202 case 4: inc_unaligned_dword_access(); break;
203 case 8: inc_unaligned_multi_access(); break;
207 switch (instruction>>12) {
208 case 0: /* mov.[bwl] to/from memory via r0+rn */
209 if (instruction & 8) {
211 srcu = (unsigned char __user *)*rm;
212 srcu += regs->regs[0];
213 dst = (unsigned char *)rn;
214 *(unsigned long *)dst = 0;
216 #if !defined(__LITTLE_ENDIAN__)
219 if (ma->from(dst, srcu, count))
222 sign_extend(count, dst);
225 src = (unsigned char *)rm;
226 #if !defined(__LITTLE_ENDIAN__)
229 dstu = (unsigned char __user *)*rn;
230 dstu += regs->regs[0];
232 if (ma->to(dstu, src, count))
238 case 1: /* mov.l Rm,@(disp,Rn) */
239 src = (unsigned char*) rm;
240 dstu = (unsigned char __user *)*rn;
241 dstu += (instruction&0x000F)<<2;
243 if (ma->to(dstu, src, 4))
248 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
251 src = (unsigned char*) rm;
252 dstu = (unsigned char __user *)*rn;
253 #if !defined(__LITTLE_ENDIAN__)
256 if (ma->to(dstu, src, count))
261 case 5: /* mov.l @(disp,Rm),Rn */
262 srcu = (unsigned char __user *)*rm;
263 srcu += (instruction & 0x000F) << 2;
264 dst = (unsigned char *)rn;
265 *(unsigned long *)dst = 0;
267 if (ma->from(dst, srcu, 4))
272 case 6: /* mov.[bwl] from memory, possibly with post-increment */
273 srcu = (unsigned char __user *)*rm;
276 dst = (unsigned char*) rn;
277 *(unsigned long*)dst = 0;
279 #if !defined(__LITTLE_ENDIAN__)
282 if (ma->from(dst, srcu, count))
284 sign_extend(count, dst);
289 switch ((instruction&0xFF00)>>8) {
290 case 0x81: /* mov.w R0,@(disp,Rn) */
291 src = (unsigned char *) ®s->regs[0];
292 #if !defined(__LITTLE_ENDIAN__)
295 dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
296 dstu += (instruction & 0x000F) << 1;
298 if (ma->to(dstu, src, 2))
303 case 0x85: /* mov.w @(disp,Rm),R0 */
304 srcu = (unsigned char __user *)*rm;
305 srcu += (instruction & 0x000F) << 1;
306 dst = (unsigned char *) ®s->regs[0];
307 *(unsigned long *)dst = 0;
309 #if !defined(__LITTLE_ENDIAN__)
312 if (ma->from(dst, srcu, 2))
323 /* Argh. Address not only misaligned but also non-existent.
324 * Raise an EFAULT and see if it's trapped
326 die_if_no_fixup("Fault in unaligned fixup", regs, 0);
331 * emulate the instruction in the delay slot
332 * - fetches the instruction from PC+2
334 static inline int handle_delayslot(struct pt_regs *regs,
335 insn_size_t old_instruction,
336 struct mem_access *ma)
338 insn_size_t instruction;
339 void __user *addr = (void __user *)(regs->pc +
340 instruction_size(old_instruction));
342 if (copy_from_user(&instruction, addr, sizeof(instruction))) {
343 /* the instruction-fetch faulted */
348 die("delay-slot-insn faulting in handle_unaligned_delayslot",
352 return handle_unaligned_ins(instruction, regs, ma);
356 * handle an instruction that does an unaligned memory access
357 * - have to be careful of branch delay-slot instructions that fault
359 * - if the branch would be taken PC points to the branch
360 * - if the branch would not be taken, PC points to delay-slot
362 * - PC always points to delayed branch
363 * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
366 /* Macros to determine offset from current PC for branch instructions */
367 /* Explicit type coercion is used to force sign extension where needed */
368 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
369 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
371 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
372 struct mem_access *ma, int expected,
373 unsigned long address)
379 * XXX: We can't handle mixed 16/32-bit instructions yet
381 if (instruction_size(instruction) != 2)
384 index = (instruction>>8)&15; /* 0x0F00 */
385 rm = regs->regs[index];
388 * Log the unexpected fixups, and then pass them on to perf.
390 * We intentionally don't report the expected cases to perf as
391 * otherwise the trapped I/O case will skew the results too much
395 unaligned_fixups_notify(current, instruction, regs);
396 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1,
401 switch (instruction&0xF000) {
403 if (instruction==0x000B) {
405 ret = handle_delayslot(regs, instruction, ma);
409 else if ((instruction&0x00FF)==0x0023) {
411 ret = handle_delayslot(regs, instruction, ma);
415 else if ((instruction&0x00FF)==0x0003) {
417 ret = handle_delayslot(regs, instruction, ma);
419 regs->pr = regs->pc + 4;
424 /* mov.[bwl] to/from memory via r0+rn */
429 case 0x1000: /* mov.l Rm,@(disp,Rn) */
432 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
436 if ((instruction&0x00FF)==0x002B) {
438 ret = handle_delayslot(regs, instruction, ma);
442 else if ((instruction&0x00FF)==0x000B) {
444 ret = handle_delayslot(regs, instruction, ma);
446 regs->pr = regs->pc + 4;
451 /* mov.[bwl] to/from memory via r0+rn */
456 case 0x5000: /* mov.l @(disp,Rm),Rn */
459 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
462 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
463 switch (instruction&0x0F00) {
464 case 0x0100: /* mov.w R0,@(disp,Rm) */
466 case 0x0500: /* mov.w @(disp,Rm),R0 */
468 case 0x0B00: /* bf lab - no delayslot*/
471 case 0x0F00: /* bf/s lab */
472 ret = handle_delayslot(regs, instruction, ma);
474 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
475 if ((regs->sr & 0x00000001) != 0)
476 regs->pc += 4; /* next after slot */
479 regs->pc += SH_PC_8BIT_OFFSET(instruction);
482 case 0x0900: /* bt lab - no delayslot */
485 case 0x0D00: /* bt/s lab */
486 ret = handle_delayslot(regs, instruction, ma);
488 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
489 if ((regs->sr & 0x00000001) == 0)
490 regs->pc += 4; /* next after slot */
493 regs->pc += SH_PC_8BIT_OFFSET(instruction);
499 case 0xA000: /* bra label */
500 ret = handle_delayslot(regs, instruction, ma);
502 regs->pc += SH_PC_12BIT_OFFSET(instruction);
505 case 0xB000: /* bsr label */
506 ret = handle_delayslot(regs, instruction, ma);
508 regs->pr = regs->pc + 4;
509 regs->pc += SH_PC_12BIT_OFFSET(instruction);
515 /* handle non-delay-slot instruction */
517 ret = handle_unaligned_ins(instruction, regs, ma);
519 regs->pc += instruction_size(instruction);
524 * Handle various address error exceptions:
525 * - instruction address error:
527 * PC >= 0x80000000 in user mode
528 * - data address error (read and write)
529 * misaligned data access
530 * access to >= 0x80000000 is user mode
531 * Unfortuntaly we can't distinguish between instruction address error
532 * and data address errors caused by read accesses.
534 asmlinkage void do_address_error(struct pt_regs *regs,
535 unsigned long writeaccess,
536 unsigned long address)
538 unsigned long error_code = 0;
541 insn_size_t instruction;
544 /* Intentional ifdef */
545 #ifdef CONFIG_CPU_HAS_SR_RB
546 error_code = lookup_exception_vector();
551 if (user_mode(regs)) {
552 int si_code = BUS_ADRERR;
553 unsigned int user_action;
556 inc_unaligned_user_access();
559 if (copy_from_user(&instruction, (insn_size_t *)(regs->pc & ~1),
560 sizeof(instruction))) {
566 /* shout about userspace fixups */
567 unaligned_fixups_notify(current, instruction, regs);
569 user_action = unaligned_user_action();
570 if (user_action & UM_FIXUP)
572 if (user_action & UM_SIGNAL)
576 regs->pc += instruction_size(instruction);
581 /* bad PC is not something we can fix */
583 si_code = BUS_ADRALN;
588 tmp = handle_unaligned_access(instruction, regs,
596 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
597 "access (PC %lx PR %lx)\n", current->comm, regs->pc,
600 info.si_signo = SIGBUS;
602 info.si_code = si_code;
603 info.si_addr = (void __user *)address;
604 force_sig_info(SIGBUS, &info, current);
606 inc_unaligned_kernel_access();
609 die("unaligned program counter", regs, error_code);
612 if (copy_from_user(&instruction, (void __user *)(regs->pc),
613 sizeof(instruction))) {
614 /* Argh. Fault on the instruction itself.
615 This should never happen non-SMP
618 die("insn faulting in do_address_error", regs, 0);
621 unaligned_fixups_notify(current, instruction, regs);
623 handle_unaligned_access(instruction, regs, &user_mem_access,
631 * SH-DSP support gerg@snapgear.com.
633 int is_dsp_inst(struct pt_regs *regs)
635 unsigned short inst = 0;
638 * Safe guard if DSP mode is already enabled or we're lacking
639 * the DSP altogether.
641 if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
644 get_user(inst, ((unsigned short *) regs->pc));
648 /* Check for any type of DSP or support instruction */
649 if ((inst == 0xf000) || (inst == 0x4000))
655 #define is_dsp_inst(regs) (0)
656 #endif /* CONFIG_SH_DSP */
658 #ifdef CONFIG_CPU_SH2A
659 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
660 unsigned long r6, unsigned long r7,
661 struct pt_regs __regs)
666 case TRAP_DIVZERO_ERROR:
667 info.si_code = FPE_INTDIV;
669 case TRAP_DIVOVF_ERROR:
670 info.si_code = FPE_INTOVF;
674 force_sig_info(SIGFPE, &info, current);
678 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
679 unsigned long r6, unsigned long r7,
680 struct pt_regs __regs)
682 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
683 unsigned long error_code;
684 struct task_struct *tsk = current;
686 #ifdef CONFIG_SH_FPU_EMU
687 unsigned short inst = 0;
690 get_user(inst, (unsigned short*)regs->pc);
692 err = do_fpu_inst(inst, regs);
694 regs->pc += instruction_size(inst);
697 /* not a FPU inst. */
701 /* Check if it's a DSP instruction */
702 if (is_dsp_inst(regs)) {
703 /* Enable DSP mode, and restart instruction. */
706 tsk->thread.dsp_status.status |= SR_DSP;
711 error_code = lookup_exception_vector();
714 force_sig(SIGILL, tsk);
715 die_if_no_fixup("reserved instruction", regs, error_code);
718 #ifdef CONFIG_SH_FPU_EMU
719 static int emulate_branch(unsigned short inst, struct pt_regs *regs)
722 * bfs: 8fxx: PC+=d*2+4;
723 * bts: 8dxx: PC+=d*2+4;
724 * bra: axxx: PC+=D*2+4;
725 * bsr: bxxx: PC+=D*2+4 after PR=PC+4;
726 * braf:0x23: PC+=Rn*2+4;
727 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
729 * jsr: 4x0b: PC=Rn after PR=PC+4;
732 if (((inst & 0xf000) == 0xb000) || /* bsr */
733 ((inst & 0xf0ff) == 0x0003) || /* bsrf */
734 ((inst & 0xf0ff) == 0x400b)) /* jsr */
735 regs->pr = regs->pc + 4;
737 if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */
738 regs->pc += SH_PC_8BIT_OFFSET(inst);
742 if ((inst & 0xe000) == 0xa000) { /* bra, bsr */
743 regs->pc += SH_PC_12BIT_OFFSET(inst);
747 if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */
748 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
752 if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */
753 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
757 if ((inst & 0xffff) == 0x000b) { /* rts */
766 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
767 unsigned long r6, unsigned long r7,
768 struct pt_regs __regs)
770 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
772 struct task_struct *tsk = current;
774 if (kprobe_handle_illslot(regs->pc) == 0)
777 #ifdef CONFIG_SH_FPU_EMU
778 get_user(inst, (unsigned short *)regs->pc + 1);
779 if (!do_fpu_inst(inst, regs)) {
780 get_user(inst, (unsigned short *)regs->pc);
781 if (!emulate_branch(inst, regs))
783 /* fault in branch.*/
785 /* not a FPU inst. */
788 inst = lookup_exception_vector();
791 force_sig(SIGILL, tsk);
792 die_if_no_fixup("illegal slot instruction", regs, inst);
795 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
796 unsigned long r6, unsigned long r7,
797 struct pt_regs __regs)
799 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
802 ex = lookup_exception_vector();
803 die_if_kernel("exception", regs, ex);
806 void __cpuinit per_cpu_trap_init(void)
808 extern void *vbr_base;
810 /* NOTE: The VBR value should be at P1
811 (or P2, virtural "fixed" address space).
812 It's definitely should not in physical address. */
814 asm volatile("ldc %0, vbr"
819 /* disable exception blocking now when the vbr has been setup */
823 void *set_exception_table_vec(unsigned int vec, void *handler)
825 extern void *exception_handling_table[];
828 old_handler = exception_handling_table[vec];
829 exception_handling_table[vec] = handler;
833 void __init trap_init(void)
835 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
836 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
838 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
839 defined(CONFIG_SH_FPU_EMU)
841 * For SH-4 lacking an FPU, treat floating point instructions as
842 * reserved. They'll be handled in the math-emu case, or faulted on
845 set_exception_table_evt(0x800, do_reserved_inst);
846 set_exception_table_evt(0x820, do_illegal_slot_inst);
847 #elif defined(CONFIG_SH_FPU)
848 set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
849 set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
852 #ifdef CONFIG_CPU_SH2
853 set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
855 #ifdef CONFIG_CPU_SH2A
856 set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
857 set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
859 set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
864 set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler);
868 void show_stack(struct task_struct *tsk, unsigned long *sp)
875 sp = (unsigned long *)current_stack_pointer;
877 sp = (unsigned long *)tsk->thread.sp;
879 stack = (unsigned long)sp;
880 dump_mem("Stack: ", stack, THREAD_SIZE +
881 (unsigned long)task_stack_page(tsk));
882 show_trace(tsk, sp, NULL);
885 void dump_stack(void)
887 show_stack(NULL, NULL);
889 EXPORT_SYMBOL(dump_stack);