arch/sh/kernel/cpu/sh4a/setup-sh7786.c

   1 /*
   2  * SH7786 Setup
   3  *
   4  * Copyright (C) 2009  Renesas Solutions Corp.
   5  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
   6  * Paul Mundt <paul.mundt@renesas.com>
   7  *
   8  * Based on SH7785 Setup
   9  *
  10  *  Copyright (C) 2007  Paul Mundt
  11  *
  12  * This file is subject to the terms and conditions of the GNU General Public
  13  * License.  See the file "COPYING" in the main directory of this archive
  14  * for more details.
  15  */
  16 #include <linux/platform_device.h>
  17 #include <linux/init.h>
  18 #include <linux/serial.h>
  19 #include <linux/serial_sci.h>
  20 #include <linux/io.h>
  21 #include <linux/mm.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/sh_timer.h>
  24 #include <asm/mmzone.h>
  25
  26 static struct plat_sci_port scif0_platform_data = {
  27         .mapbase        = 0xffea0000,
  28         .flags          = UPF_BOOT_AUTOCONF,
  29         .type           = PORT_SCIF,
  30         .irqs           = { 40, 41, 43, 42 },
  31 };
  32
  33 static struct platform_device scif0_device = {
  34         .name           = "sh-sci",
  35         .id             = 0,
  36         .dev            = {
  37                 .platform_data  = &scif0_platform_data,
  38         },
  39 };
  40
  41 /*
  42  * The rest of these all have multiplexed IRQs
  43  */
  44 static struct plat_sci_port scif1_platform_data = {
  45         .mapbase        = 0xffeb0000,
  46         .flags          = UPF_BOOT_AUTOCONF,
  47         .type           = PORT_SCIF,
  48         .irqs           = { 44, 44, 44, 44 },
  49 };
  50
  51 static struct platform_device scif1_device = {
  52         .name           = "sh-sci",
  53         .id             = 1,
  54         .dev            = {
  55                 .platform_data  = &scif1_platform_data,
  56         },
  57 };
  58
  59 static struct plat_sci_port scif2_platform_data = {
  60         .mapbase        = 0xffec0000,
  61         .flags          = UPF_BOOT_AUTOCONF,
  62         .type           = PORT_SCIF,
  63         .irqs           = { 50, 50, 50, 50 },
  64 };
  65
  66 static struct platform_device scif2_device = {
  67         .name           = "sh-sci",
  68         .id             = 2,
  69         .dev            = {
  70                 .platform_data  = &scif2_platform_data,
  71         },
  72 };
  73
  74 static struct plat_sci_port scif3_platform_data = {
  75         .mapbase        = 0xffed0000,
  76         .flags          = UPF_BOOT_AUTOCONF,
  77         .type           = PORT_SCIF,
  78         .irqs           = { 51, 51, 51, 51 },
  79 };
  80
  81 static struct platform_device scif3_device = {
  82         .name           = "sh-sci",
  83         .id             = 3,
  84         .dev            = {
  85                 .platform_data  = &scif3_platform_data,
  86         },
  87 };
  88
  89 static struct plat_sci_port scif4_platform_data = {
  90         .mapbase        = 0xffee0000,
  91         .flags          = UPF_BOOT_AUTOCONF,
  92         .type           = PORT_SCIF,
  93         .irqs           = { 52, 52, 52, 52 },
  94 };
  95
  96 static struct platform_device scif4_device = {
  97         .name           = "sh-sci",
  98         .id             = 4,
  99         .dev            = {
 100                 .platform_data  = &scif4_platform_data,
 101         },
 102 };
 103
 104 static struct plat_sci_port scif5_platform_data = {
 105         .mapbase        = 0xffef0000,
 106         .flags          = UPF_BOOT_AUTOCONF,
 107         .type           = PORT_SCIF,
 108         .irqs           = { 53, 53, 53, 53 },
 109 };
 110
 111 static struct platform_device scif5_device = {
 112         .name           = "sh-sci",
 113         .id             = 5,
 114         .dev            = {
 115                 .platform_data  = &scif5_platform_data,
 116         },
 117 };
 118
 119 static struct sh_timer_config tmu0_platform_data = {
 120         .channel_offset = 0x04,
 121         .timer_bit = 0,
 122         .clk = "peripheral_clk",
 123         .clockevent_rating = 200,
 124 };
 125
 126 static struct resource tmu0_resources[] = {
 127         [0] = {
 128                 .start  = 0xffd80008,
 129                 .end    = 0xffd80013,
 130                 .flags  = IORESOURCE_MEM,
 131         },
 132         [1] = {
 133                 .start  = 16,
 134                 .flags  = IORESOURCE_IRQ,
 135         },
 136 };
 137
 138 static struct platform_device tmu0_device = {
 139         .name           = "sh_tmu",
 140         .id             = 0,
 141         .dev = {
 142                 .platform_data  = &tmu0_platform_data,
 143         },
 144         .resource       = tmu0_resources,
 145         .num_resources  = ARRAY_SIZE(tmu0_resources),
 146 };
 147
 148 static struct sh_timer_config tmu1_platform_data = {
 149         .channel_offset = 0x10,
 150         .timer_bit = 1,
 151         .clk = "peripheral_clk",
 152         .clocksource_rating = 200,
 153 };
 154
 155 static struct resource tmu1_resources[] = {
 156         [0] = {
 157                 .start  = 0xffd80014,
 158                 .end    = 0xffd8001f,
 159                 .flags  = IORESOURCE_MEM,
 160         },
 161         [1] = {
 162                 .start  = 17,
 163                 .flags  = IORESOURCE_IRQ,
 164         },
 165 };
 166
 167 static struct platform_device tmu1_device = {
 168         .name           = "sh_tmu",
 169         .id             = 1,
 170         .dev = {
 171                 .platform_data  = &tmu1_platform_data,
 172         },
 173         .resource       = tmu1_resources,
 174         .num_resources  = ARRAY_SIZE(tmu1_resources),
 175 };
 176
 177 static struct sh_timer_config tmu2_platform_data = {
 178         .channel_offset = 0x1c,
 179         .timer_bit = 2,
 180         .clk = "peripheral_clk",
 181 };
 182
 183 static struct resource tmu2_resources[] = {
 184         [0] = {
 185                 .start  = 0xffd80020,
 186                 .end    = 0xffd8002f,
 187                 .flags  = IORESOURCE_MEM,
 188         },
 189         [1] = {
 190                 .start  = 18,
 191                 .flags  = IORESOURCE_IRQ,
 192         },
 193 };
 194
 195 static struct platform_device tmu2_device = {
 196         .name           = "sh_tmu",
 197         .id             = 2,
 198         .dev = {
 199                 .platform_data  = &tmu2_platform_data,
 200         },
 201         .resource       = tmu2_resources,
 202         .num_resources  = ARRAY_SIZE(tmu2_resources),
 203 };
 204
 205 static struct sh_timer_config tmu3_platform_data = {
 206         .channel_offset = 0x04,
 207         .timer_bit = 0,
 208         .clk = "peripheral_clk",
 209 };
 210
 211 static struct resource tmu3_resources[] = {
 212         [0] = {
 213                 .start  = 0xffda0008,
 214                 .end    = 0xffda0013,
 215                 .flags  = IORESOURCE_MEM,
 216         },
 217         [1] = {
 218                 .start  = 20,
 219                 .flags  = IORESOURCE_IRQ,
 220         },
 221 };
 222
 223 static struct platform_device tmu3_device = {
 224         .name           = "sh_tmu",
 225         .id             = 3,
 226         .dev = {
 227                 .platform_data  = &tmu3_platform_data,
 228         },
 229         .resource       = tmu3_resources,
 230         .num_resources  = ARRAY_SIZE(tmu3_resources),
 231 };
 232
 233 static struct sh_timer_config tmu4_platform_data = {
 234         .channel_offset = 0x10,
 235         .timer_bit = 1,
 236         .clk = "peripheral_clk",
 237 };
 238
 239 static struct resource tmu4_resources[] = {
 240         [0] = {
 241                 .start  = 0xffda0014,
 242                 .end    = 0xffda001f,
 243                 .flags  = IORESOURCE_MEM,
 244         },
 245         [1] = {
 246                 .start  = 21,
 247                 .flags  = IORESOURCE_IRQ,
 248         },
 249 };
 250
 251 static struct platform_device tmu4_device = {
 252         .name           = "sh_tmu",
 253         .id             = 4,
 254         .dev = {
 255                 .platform_data  = &tmu4_platform_data,
 256         },
 257         .resource       = tmu4_resources,
 258         .num_resources  = ARRAY_SIZE(tmu4_resources),
 259 };
 260
 261 static struct sh_timer_config tmu5_platform_data = {
 262         .channel_offset = 0x1c,
 263         .timer_bit = 2,
 264         .clk = "peripheral_clk",
 265 };
 266
 267 static struct resource tmu5_resources[] = {
 268         [0] = {
 269                 .start  = 0xffda0020,
 270                 .end    = 0xffda002b,
 271                 .flags  = IORESOURCE_MEM,
 272         },
 273         [1] = {
 274                 .start  = 22,
 275                 .flags  = IORESOURCE_IRQ,
 276         },
 277 };
 278
 279 static struct platform_device tmu5_device = {
 280         .name           = "sh_tmu",
 281         .id             = 5,
 282         .dev = {
 283                 .platform_data  = &tmu5_platform_data,
 284         },
 285         .resource       = tmu5_resources,
 286         .num_resources  = ARRAY_SIZE(tmu5_resources),
 287 };
 288
 289 static struct sh_timer_config tmu6_platform_data = {
 290         .channel_offset = 0x04,
 291         .timer_bit = 0,
 292         .clk = "peripheral_clk",
 293 };
 294
 295 static struct resource tmu6_resources[] = {
 296         [0] = {
 297                 .start  = 0xffdc0008,
 298                 .end    = 0xffdc0013,
 299                 .flags  = IORESOURCE_MEM,
 300         },
 301         [1] = {
 302                 .start  = 45,
 303                 .flags  = IORESOURCE_IRQ,
 304         },
 305 };
 306
 307 static struct platform_device tmu6_device = {
 308         .name           = "sh_tmu",
 309         .id             = 6,
 310         .dev = {
 311                 .platform_data  = &tmu6_platform_data,
 312         },
 313         .resource       = tmu6_resources,
 314         .num_resources  = ARRAY_SIZE(tmu6_resources),
 315 };
 316
 317 static struct sh_timer_config tmu7_platform_data = {
 318         .channel_offset = 0x10,
 319         .timer_bit = 1,
 320         .clk = "peripheral_clk",
 321 };
 322
 323 static struct resource tmu7_resources[] = {
 324         [0] = {
 325                 .start  = 0xffdc0014,
 326                 .end    = 0xffdc001f,
 327                 .flags  = IORESOURCE_MEM,
 328         },
 329         [1] = {
 330                 .start  = 45,
 331                 .flags  = IORESOURCE_IRQ,
 332         },
 333 };
 334
 335 static struct platform_device tmu7_device = {
 336         .name           = "sh_tmu",
 337         .id             = 7,
 338         .dev = {
 339                 .platform_data  = &tmu7_platform_data,
 340         },
 341         .resource       = tmu7_resources,
 342         .num_resources  = ARRAY_SIZE(tmu7_resources),
 343 };
 344
 345 static struct sh_timer_config tmu8_platform_data = {
 346         .channel_offset = 0x1c,
 347         .timer_bit = 2,
 348         .clk = "peripheral_clk",
 349 };
 350
 351 static struct resource tmu8_resources[] = {
 352         [0] = {
 353                 .start  = 0xffdc0020,
 354                 .end    = 0xffdc002b,
 355                 .flags  = IORESOURCE_MEM,
 356         },
 357         [1] = {
 358                 .start  = 45,
 359                 .flags  = IORESOURCE_IRQ,
 360         },
 361 };
 362
 363 static struct platform_device tmu8_device = {
 364         .name           = "sh_tmu",
 365         .id             = 8,
 366         .dev = {
 367                 .platform_data  = &tmu8_platform_data,
 368         },
 369         .resource       = tmu8_resources,
 370         .num_resources  = ARRAY_SIZE(tmu8_resources),
 371 };
 372
 373 static struct sh_timer_config tmu9_platform_data = {
 374         .channel_offset = 0x04,
 375         .timer_bit = 0,
 376         .clk = "peripheral_clk",
 377 };
 378
 379 static struct resource tmu9_resources[] = {
 380         [0] = {
 381                 .start  = 0xffde0008,
 382                 .end    = 0xffde0013,
 383                 .flags  = IORESOURCE_MEM,
 384         },
 385         [1] = {
 386                 .start  = 46,
 387                 .flags  = IORESOURCE_IRQ,
 388         },
 389 };
 390
 391 static struct platform_device tmu9_device = {
 392         .name           = "sh_tmu",
 393         .id             = 9,
 394         .dev = {
 395                 .platform_data  = &tmu9_platform_data,
 396         },
 397         .resource       = tmu9_resources,
 398         .num_resources  = ARRAY_SIZE(tmu9_resources),
 399 };
 400
 401 static struct sh_timer_config tmu10_platform_data = {
 402         .channel_offset = 0x10,
 403         .timer_bit = 1,
 404         .clk = "peripheral_clk",
 405 };
 406
 407 static struct resource tmu10_resources[] = {
 408         [0] = {
 409                 .start  = 0xffde0014,
 410                 .end    = 0xffde001f,
 411                 .flags  = IORESOURCE_MEM,
 412         },
 413         [1] = {
 414                 .start  = 46,
 415                 .flags  = IORESOURCE_IRQ,
 416         },
 417 };
 418
 419 static struct platform_device tmu10_device = {
 420         .name           = "sh_tmu",
 421         .id             = 10,
 422         .dev = {
 423                 .platform_data  = &tmu10_platform_data,
 424         },
 425         .resource       = tmu10_resources,
 426         .num_resources  = ARRAY_SIZE(tmu10_resources),
 427 };
 428
 429 static struct sh_timer_config tmu11_platform_data = {
 430         .channel_offset = 0x1c,
 431         .timer_bit = 2,
 432         .clk = "peripheral_clk",
 433 };
 434
 435 static struct resource tmu11_resources[] = {
 436         [0] = {
 437                 .start  = 0xffde0020,
 438                 .end    = 0xffde002b,
 439                 .flags  = IORESOURCE_MEM,
 440         },
 441         [1] = {
 442                 .start  = 46,
 443                 .flags  = IORESOURCE_IRQ,
 444         },
 445 };
 446
 447 static struct platform_device tmu11_device = {
 448         .name           = "sh_tmu",
 449         .id             = 11,
 450         .dev = {
 451                 .platform_data  = &tmu11_platform_data,
 452         },
 453         .resource       = tmu11_resources,
 454         .num_resources  = ARRAY_SIZE(tmu11_resources),
 455 };
 456
 457 static struct resource usb_ohci_resources[] = {
 458         [0] = {
 459                 .start  = 0xffe70400,
 460                 .end    = 0xffe704ff,
 461                 .flags  = IORESOURCE_MEM,
 462         },
 463         [1] = {
 464                 .start  = 77,
 465                 .end    = 77,
 466                 .flags  = IORESOURCE_IRQ,
 467         },
 468 };
 469
 470 static u64 usb_ohci_dma_mask = DMA_BIT_MASK(32);
 471 static struct platform_device usb_ohci_device = {
 472         .name           = "sh_ohci",
 473         .id             = -1,
 474         .dev = {
 475                 .dma_mask               = &usb_ohci_dma_mask,
 476                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 477         },
 478         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
 479         .resource       = usb_ohci_resources,
 480 };
 481
 482 static struct platform_device *sh7786_early_devices[] __initdata = {
 483         &scif0_device,
 484         &scif1_device,
 485         &scif2_device,
 486         &scif3_device,
 487         &scif4_device,
 488         &scif5_device,
 489         &tmu0_device,
 490         &tmu1_device,
 491         &tmu2_device,
 492         &tmu3_device,
 493         &tmu4_device,
 494         &tmu5_device,
 495         &tmu6_device,
 496         &tmu7_device,
 497         &tmu8_device,
 498         &tmu9_device,
 499         &tmu10_device,
 500         &tmu11_device,
 501 };
 502
 503 static struct platform_device *sh7786_devices[] __initdata = {
 504         &usb_ohci_device,
 505 };
 506
 507
 508 /*
 509  * Please call this function if your platform board
 510  * use external clock for USB
 511  * */
 512 #define USBCTL0         0xffe70858
 513 #define CLOCK_MODE_MASK 0xffffff7f
 514 #define EXT_CLOCK_MODE  0x00000080
 515 void __init sh7786_usb_use_exclock(void)
 516 {
 517         u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
 518         __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
 519 }
 520
 521 #define USBINITREG1     0xffe70094
 522 #define USBINITREG2     0xffe7009c
 523 #define USBINITVAL1     0x00ff0040
 524 #define USBINITVAL2     0x00000001
 525
 526 #define USBPCTL1        0xffe70804
 527 #define USBST           0xffe70808
 528 #define PHY_ENB         0x00000001
 529 #define PLL_ENB         0x00000002
 530 #define PHY_RST         0x00000004
 531 #define ACT_PLL_STATUS  0xc0000000
 532 static void __init sh7786_usb_setup(void)
 533 {
 534         int i = 1000000;
 535
 536         /*
 537          * USB initial settings
 538          *
 539          * The following settings are necessary
 540          * for using the USB modules.
 541          *
 542          * see "USB Inital Settings" for detail
 543          */
 544         __raw_writel(USBINITVAL1, USBINITREG1);
 545         __raw_writel(USBINITVAL2, USBINITREG2);
 546
 547         /*
 548          * Set the PHY and PLL enable bit
 549          */
 550         __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
 551         while (i--) {
 552                 if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
 553                         /* Set the PHY RST bit */
 554                         __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
 555                         printk(KERN_INFO "sh7786 usb setup done\n");
 556                         break;
 557                 }
 558                 cpu_relax();
 559         }
 560 }
 561
 562 static int __init sh7786_devices_setup(void)
 563 {
 564         int ret;
 565
 566         sh7786_usb_setup();
 567
 568         ret = platform_add_devices(sh7786_early_devices,
 569                                    ARRAY_SIZE(sh7786_early_devices));
 570         if (unlikely(ret != 0))
 571                 return ret;
 572
 573         return platform_add_devices(sh7786_devices,
 574                                     ARRAY_SIZE(sh7786_devices));
 575 }
 576 arch_initcall(sh7786_devices_setup);
 577
 578 void __init plat_early_device_setup(void)
 579 {
 580         early_platform_add_devices(sh7786_early_devices,
 581                                    ARRAY_SIZE(sh7786_early_devices));
 582 }
 583
 584 enum {
 585         UNUSED = 0,
 586
 587         /* interrupt sources */
 588
 589         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 590         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 591         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 592         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 593
 594         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 595         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 596         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 597         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 598
 599         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 600         WDT,
 601         TMU0_0, TMU0_1, TMU0_2, TMU0_3,
 602         TMU1_0, TMU1_1, TMU1_2,
 603         DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
 604         HUDI1, HUDI0,
 605         DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
 606         HPB_0, HPB_1, HPB_2,
 607         SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
 608         SCIF1,
 609         TMU2, TMU3,
 610         SCIF2, SCIF3, SCIF4, SCIF5,
 611         Eth_0, Eth_1,
 612         PCIeC0_0, PCIeC0_1, PCIeC0_2,
 613         PCIeC1_0, PCIeC1_1, PCIeC1_2,
 614         USB,
 615         I2C0, I2C1,
 616         DU,
 617         SSI0, SSI1, SSI2, SSI3,
 618         PCIeC2_0, PCIeC2_1, PCIeC2_2,
 619         HAC0, HAC1,
 620         FLCTL,
 621         HSPI,
 622         GPIO0, GPIO1,
 623         Thermal,
 624         INTICI0, INTICI1, INTICI2, INTICI3,
 625         INTICI4, INTICI5, INTICI6, INTICI7,
 626 };
 627
 628 static struct intc_vect vectors[] __initdata = {
 629         INTC_VECT(WDT, 0x3e0),
 630         INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
 631         INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
 632         INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
 633         INTC_VECT(TMU1_2, 0x4c0),
 634         INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
 635         INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
 636         INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
 637         INTC_VECT(DMAC0_6, 0x5c0),
 638         INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
 639         INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
 640         INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
 641         INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
 642         INTC_VECT(HPB_2, 0x6e0),
 643         INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
 644         INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
 645         INTC_VECT(SCIF1, 0x780),
 646         INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
 647         INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
 648         INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
 649         INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
 650         INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
 651         INTC_VECT(PCIeC0_2, 0xb20),
 652         INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
 653         INTC_VECT(PCIeC1_2, 0xb80),
 654         INTC_VECT(USB, 0xba0),
 655         INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
 656         INTC_VECT(DU, 0xd00),
 657         INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
 658         INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
 659         INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
 660         INTC_VECT(PCIeC2_2, 0xde0),
 661         INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
 662         INTC_VECT(FLCTL, 0xe40),
 663         INTC_VECT(HSPI, 0xe80),
 664         INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
 665         INTC_VECT(Thermal, 0xee0),
 666         INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
 667         INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
 668         INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
 669         INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
 670 };
 671
 672 #define CnINTMSK0       0xfe410030
 673 #define CnINTMSK1       0xfe410040
 674 #define CnINTMSKCLR0    0xfe410050
 675 #define CnINTMSKCLR1    0xfe410060
 676 #define CnINT2MSKR0     0xfe410a20
 677 #define CnINT2MSKR1     0xfe410a24
 678 #define CnINT2MSKR2     0xfe410a28
 679 #define CnINT2MSKR3     0xfe410a2c
 680 #define CnINT2MSKCR0    0xfe410a30
 681 #define CnINT2MSKCR1    0xfe410a34
 682 #define CnINT2MSKCR2    0xfe410a38
 683 #define CnINT2MSKCR3    0xfe410a3c
 684 #define INTMSK2         0xfe410068
 685 #define INTMSKCLR2      0xfe41006c
 686
 687 static struct intc_mask_reg mask_registers[] __initdata = {
 688         { CnINTMSK0, CnINTMSKCLR0, 32,
 689           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 690         { INTMSK2, INTMSKCLR2, 32,
 691           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 692             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 693             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 694             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 695             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 696             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 697             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 698             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 699         { CnINT2MSKR0, CnINT2MSKCR0 , 32,
 700           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 701             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } },
 702         { CnINT2MSKR1, CnINT2MSKCR1, 32,
 703           { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
 704             DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
 705             HUDI1, HUDI0,
 706             DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
 707             HPB_0, HPB_1, HPB_2,
 708             SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
 709             SCIF1,
 710             TMU2, TMU3, 0, } },
 711         { CnINT2MSKR2, CnINT2MSKCR2, 32,
 712           { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
 713             Eth_0, Eth_1,
 714             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 715             PCIeC0_0, PCIeC0_1, PCIeC0_2,
 716             PCIeC1_0, PCIeC1_1, PCIeC1_2,
 717             USB, 0, 0 } },
 718         { CnINT2MSKR3, CnINT2MSKCR3, 32,
 719           { 0, 0, 0, 0, 0, 0,
 720             I2C0, I2C1,
 721             DU, SSI0, SSI1, SSI2, SSI3,
 722             PCIeC2_0, PCIeC2_1, PCIeC2_2,
 723             HAC0, HAC1,
 724             FLCTL, 0,
 725             HSPI, GPIO0, GPIO1, Thermal,
 726             0, 0, 0, 0, 0, 0, 0, 0 } },
 727 };
 728
 729 static struct intc_prio_reg prio_registers[] __initdata = {
 730         { 0xfe410010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
 731                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
 732         { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
 733         { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
 734                                                  TMU0_2, TMU0_3 } },
 735         { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
 736                                                  TMU1_2, 0 } },
 737         { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
 738                                                  DMAC0_2, DMAC0_3 } },
 739         { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
 740                                                  DMAC0_6, HUDI1 } },
 741         { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
 742                                                  DMAC1_1, DMAC1_2 } },
 743         { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
 744                                                  HPB_1, HPB_2 } },
 745         { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
 746                                                  SCIF0_2, SCIF0_3 } },
 747         { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
 748         { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
 749         { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
 750                                                   Eth_0, Eth_1 } },
 751         { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
 752         { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
 753         { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
 754         { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
 755         { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
 756                                                   PCIeC1_0, PCIeC1_1 } },
 757         { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
 758         { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
 759         { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
 760         { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
 761         { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
 762                                                   PCIeC2_1, PCIeC2_2 } },
 763         { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
 764         { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
 765                                                   GPIO1, Thermal } },
 766         { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
 767         { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
 768         { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
 769           { INTICI7, INTICI6, INTICI5, INTICI4,
 770             INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
 771 };
 772
 773 static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL,
 774                          mask_registers, prio_registers, NULL);
 775
 776 /* Support for external interrupt pins in IRQ mode */
 777
 778 static struct intc_vect vectors_irq0123[] __initdata = {
 779         INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
 780         INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
 781 };
 782
 783 static struct intc_vect vectors_irq4567[] __initdata = {
 784         INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
 785         INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
 786 };
 787
 788 static struct intc_sense_reg sense_registers[] __initdata = {
 789         { 0xfe41001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 790                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 791 };
 792
 793 static struct intc_mask_reg ack_registers[] __initdata = {
 794         { 0xfe410024, 0, 32, /* INTREQ */
 795           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 796 };
 797
 798 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
 799                              vectors_irq0123, NULL, mask_registers,
 800                              prio_registers, sense_registers, ack_registers);
 801
 802 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
 803                              vectors_irq4567, NULL, mask_registers,
 804                              prio_registers, sense_registers, ack_registers);
 805
 806 /* External interrupt pins in IRL mode */
 807
 808 static struct intc_vect vectors_irl0123[] __initdata = {
 809         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 810         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 811         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 812         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 813         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 814         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 815         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 816         INTC_VECT(IRL0_HHHL, 0x3c0),
 817 };
 818
 819 static struct intc_vect vectors_irl4567[] __initdata = {
 820         INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
 821         INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
 822         INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
 823         INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
 824         INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
 825         INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
 826         INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
 827         INTC_VECT(IRL4_HHHL, 0xac0),
 828 };
 829
 830 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
 831                          NULL, mask_registers, NULL, NULL);
 832
 833 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
 834                          NULL, mask_registers, NULL, NULL);
 835
 836 #define INTC_ICR0       0xfe410000
 837 #define INTC_INTMSK0    CnINTMSK0
 838 #define INTC_INTMSK1    CnINTMSK1
 839 #define INTC_INTMSK2    INTMSK2
 840 #define INTC_INTMSKCLR1 CnINTMSKCLR1
 841 #define INTC_INTMSKCLR2 INTMSKCLR2
 842
 843 void __init plat_irq_setup(void)
 844 {
 845         /* disable IRQ3-0 + IRQ7-4 */
 846         __raw_writel(0xff000000, INTC_INTMSK0);
 847
 848         /* disable IRL3-0 + IRL7-4 */
 849         __raw_writel(0xc0000000, INTC_INTMSK1);
 850         __raw_writel(0xfffefffe, INTC_INTMSK2);
 851
 852         /* select IRL mode for IRL3-0 + IRL7-4 */
 853         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 854
 855         register_intc_controller(&intc_desc);
 856 }
 857
 858 void __init plat_irq_setup_pins(int mode)
 859 {
 860         switch (mode) {
 861         case IRQ_MODE_IRQ7654:
 862                 /* select IRQ mode for IRL7-4 */
 863                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
 864                 register_intc_controller(&intc_desc_irq4567);
 865                 break;
 866         case IRQ_MODE_IRQ3210:
 867                 /* select IRQ mode for IRL3-0 */
 868                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 869                 register_intc_controller(&intc_desc_irq0123);
 870                 break;
 871         case IRQ_MODE_IRL7654:
 872                 /* enable IRL7-4 but don't provide any masking */
 873                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 874                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 875                 break;
 876         case IRQ_MODE_IRL3210:
 877                 /* enable IRL0-3 but don't provide any masking */
 878                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 879                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 880                 break;
 881         case IRQ_MODE_IRL7654_MASK:
 882                 /* enable IRL7-4 and mask using cpu intc controller */
 883                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 884                 register_intc_controller(&intc_desc_irl4567);
 885                 break;
 886         case IRQ_MODE_IRL3210_MASK:
 887                 /* enable IRL0-3 and mask using cpu intc controller */
 888                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 889                 register_intc_controller(&intc_desc_irl0123);
 890                 break;
 891         default:
 892                 BUG();
 893         }
 894 }
 895
 896 void __init plat_mem_setup(void)
 897 {
 898 }