arch/sh/kernel/cpu/sh4a/setup-sh7786.c

   1 /*
   2  * SH7786 Setup
   3  *
   4  * Copyright (C) 2009  Renesas Solutions Corp.
   5  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
   6  * Paul Mundt <paul.mundt@renesas.com>
   7  *
   8  * Based on SH7785 Setup
   9  *
  10  *  Copyright (C) 2007  Paul Mundt
  11  *
  12  * This file is subject to the terms and conditions of the GNU General Public
  13  * License.  See the file "COPYING" in the main directory of this archive
  14  * for more details.
  15  */
  16 #include <linux/platform_device.h>
  17 #include <linux/init.h>
  18 #include <linux/serial.h>
  19 #include <linux/serial_sci.h>
  20 #include <linux/io.h>
  21 #include <linux/mm.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/sh_timer.h>
  24 #include <asm/mmzone.h>
  25
  26 static struct plat_sci_port scif0_platform_data = {
  27         .mapbase        = 0xffea0000,
  28         .flags          = UPF_BOOT_AUTOCONF,
  29         .type           = PORT_SCIF,
  30         .irqs           = { 40, 41, 43, 42 },
  31 };
  32
  33 static struct platform_device scif0_device = {
  34         .name           = "sh-sci",
  35         .id             = 0,
  36         .dev            = {
  37                 .platform_data  = &scif0_platform_data,
  38         },
  39 };
  40
  41 /*
  42  * The rest of these all have multiplexed IRQs
  43  */
  44 static struct plat_sci_port scif1_platform_data = {
  45         .mapbase        = 0xffeb0000,
  46         .flags          = UPF_BOOT_AUTOCONF,
  47         .type           = PORT_SCIF,
  48         .irqs           = { 44, 44, 44, 44 },
  49 };
  50
  51 static struct platform_device scif1_device = {
  52         .name           = "sh-sci",
  53         .id             = 1,
  54         .dev            = {
  55                 .platform_data  = &scif1_platform_data,
  56         },
  57 };
  58
  59 static struct plat_sci_port scif2_platform_data = {
  60         .mapbase        = 0xffec0000,
  61         .flags          = UPF_BOOT_AUTOCONF,
  62         .type           = PORT_SCIF,
  63         .irqs           = { 50, 50, 50, 50 },
  64 };
  65
  66 static struct platform_device scif2_device = {
  67         .name           = "sh-sci",
  68         .id             = 2,
  69         .dev            = {
  70                 .platform_data  = &scif2_platform_data,
  71         },
  72 };
  73
  74 static struct plat_sci_port scif3_platform_data = {
  75         .mapbase        = 0xffed0000,
  76         .flags          = UPF_BOOT_AUTOCONF,
  77         .type           = PORT_SCIF,
  78         .irqs           = { 51, 51, 51, 51 },
  79 };
  80
  81 static struct platform_device scif3_device = {
  82         .name           = "sh-sci",
  83         .id             = 3,
  84         .dev            = {
  85                 .platform_data  = &scif3_platform_data,
  86         },
  87 };
  88
  89 static struct plat_sci_port scif4_platform_data = {
  90         .mapbase        = 0xffee0000,
  91         .flags          = UPF_BOOT_AUTOCONF,
  92         .type           = PORT_SCIF,
  93         .irqs           = { 52, 52, 52, 52 },
  94 };
  95
  96 static struct platform_device scif4_device = {
  97         .name           = "sh-sci",
  98         .id             = 4,
  99         .dev            = {
 100                 .platform_data  = &scif4_platform_data,
 101         },
 102 };
 103
 104 static struct plat_sci_port scif5_platform_data = {
 105         .mapbase        = 0xffef0000,
 106         .flags          = UPF_BOOT_AUTOCONF,
 107         .type           = PORT_SCIF,
 108         .irqs           = { 53, 53, 53, 53 },
 109 };
 110
 111 static struct platform_device scif5_device = {
 112         .name           = "sh-sci",
 113         .id             = 5,
 114         .dev            = {
 115                 .platform_data  = &scif5_platform_data,
 116         },
 117 };
 118
 119 static struct sh_timer_config tmu0_platform_data = {
 120         .channel_offset = 0x04,
 121         .timer_bit = 0,
 122         .clockevent_rating = 200,
 123 };
 124
 125 static struct resource tmu0_resources[] = {
 126         [0] = {
 127                 .start  = 0xffd80008,
 128                 .end    = 0xffd80013,
 129                 .flags  = IORESOURCE_MEM,
 130         },
 131         [1] = {
 132                 .start  = 16,
 133                 .flags  = IORESOURCE_IRQ,
 134         },
 135 };
 136
 137 static struct platform_device tmu0_device = {
 138         .name           = "sh_tmu",
 139         .id             = 0,
 140         .dev = {
 141                 .platform_data  = &tmu0_platform_data,
 142         },
 143         .resource       = tmu0_resources,
 144         .num_resources  = ARRAY_SIZE(tmu0_resources),
 145 };
 146
 147 static struct sh_timer_config tmu1_platform_data = {
 148         .channel_offset = 0x10,
 149         .timer_bit = 1,
 150         .clocksource_rating = 200,
 151 };
 152
 153 static struct resource tmu1_resources[] = {
 154         [0] = {
 155                 .start  = 0xffd80014,
 156                 .end    = 0xffd8001f,
 157                 .flags  = IORESOURCE_MEM,
 158         },
 159         [1] = {
 160                 .start  = 17,
 161                 .flags  = IORESOURCE_IRQ,
 162         },
 163 };
 164
 165 static struct platform_device tmu1_device = {
 166         .name           = "sh_tmu",
 167         .id             = 1,
 168         .dev = {
 169                 .platform_data  = &tmu1_platform_data,
 170         },
 171         .resource       = tmu1_resources,
 172         .num_resources  = ARRAY_SIZE(tmu1_resources),
 173 };
 174
 175 static struct sh_timer_config tmu2_platform_data = {
 176         .channel_offset = 0x1c,
 177         .timer_bit = 2,
 178 };
 179
 180 static struct resource tmu2_resources[] = {
 181         [0] = {
 182                 .start  = 0xffd80020,
 183                 .end    = 0xffd8002f,
 184                 .flags  = IORESOURCE_MEM,
 185         },
 186         [1] = {
 187                 .start  = 18,
 188                 .flags  = IORESOURCE_IRQ,
 189         },
 190 };
 191
 192 static struct platform_device tmu2_device = {
 193         .name           = "sh_tmu",
 194         .id             = 2,
 195         .dev = {
 196                 .platform_data  = &tmu2_platform_data,
 197         },
 198         .resource       = tmu2_resources,
 199         .num_resources  = ARRAY_SIZE(tmu2_resources),
 200 };
 201
 202 static struct sh_timer_config tmu3_platform_data = {
 203         .channel_offset = 0x04,
 204         .timer_bit = 0,
 205 };
 206
 207 static struct resource tmu3_resources[] = {
 208         [0] = {
 209                 .start  = 0xffda0008,
 210                 .end    = 0xffda0013,
 211                 .flags  = IORESOURCE_MEM,
 212         },
 213         [1] = {
 214                 .start  = 20,
 215                 .flags  = IORESOURCE_IRQ,
 216         },
 217 };
 218
 219 static struct platform_device tmu3_device = {
 220         .name           = "sh_tmu",
 221         .id             = 3,
 222         .dev = {
 223                 .platform_data  = &tmu3_platform_data,
 224         },
 225         .resource       = tmu3_resources,
 226         .num_resources  = ARRAY_SIZE(tmu3_resources),
 227 };
 228
 229 static struct sh_timer_config tmu4_platform_data = {
 230         .channel_offset = 0x10,
 231         .timer_bit = 1,
 232 };
 233
 234 static struct resource tmu4_resources[] = {
 235         [0] = {
 236                 .start  = 0xffda0014,
 237                 .end    = 0xffda001f,
 238                 .flags  = IORESOURCE_MEM,
 239         },
 240         [1] = {
 241                 .start  = 21,
 242                 .flags  = IORESOURCE_IRQ,
 243         },
 244 };
 245
 246 static struct platform_device tmu4_device = {
 247         .name           = "sh_tmu",
 248         .id             = 4,
 249         .dev = {
 250                 .platform_data  = &tmu4_platform_data,
 251         },
 252         .resource       = tmu4_resources,
 253         .num_resources  = ARRAY_SIZE(tmu4_resources),
 254 };
 255
 256 static struct sh_timer_config tmu5_platform_data = {
 257         .channel_offset = 0x1c,
 258         .timer_bit = 2,
 259 };
 260
 261 static struct resource tmu5_resources[] = {
 262         [0] = {
 263                 .start  = 0xffda0020,
 264                 .end    = 0xffda002b,
 265                 .flags  = IORESOURCE_MEM,
 266         },
 267         [1] = {
 268                 .start  = 22,
 269                 .flags  = IORESOURCE_IRQ,
 270         },
 271 };
 272
 273 static struct platform_device tmu5_device = {
 274         .name           = "sh_tmu",
 275         .id             = 5,
 276         .dev = {
 277                 .platform_data  = &tmu5_platform_data,
 278         },
 279         .resource       = tmu5_resources,
 280         .num_resources  = ARRAY_SIZE(tmu5_resources),
 281 };
 282
 283 static struct sh_timer_config tmu6_platform_data = {
 284         .channel_offset = 0x04,
 285         .timer_bit = 0,
 286 };
 287
 288 static struct resource tmu6_resources[] = {
 289         [0] = {
 290                 .start  = 0xffdc0008,
 291                 .end    = 0xffdc0013,
 292                 .flags  = IORESOURCE_MEM,
 293         },
 294         [1] = {
 295                 .start  = 45,
 296                 .flags  = IORESOURCE_IRQ,
 297         },
 298 };
 299
 300 static struct platform_device tmu6_device = {
 301         .name           = "sh_tmu",
 302         .id             = 6,
 303         .dev = {
 304                 .platform_data  = &tmu6_platform_data,
 305         },
 306         .resource       = tmu6_resources,
 307         .num_resources  = ARRAY_SIZE(tmu6_resources),
 308 };
 309
 310 static struct sh_timer_config tmu7_platform_data = {
 311         .channel_offset = 0x10,
 312         .timer_bit = 1,
 313 };
 314
 315 static struct resource tmu7_resources[] = {
 316         [0] = {
 317                 .start  = 0xffdc0014,
 318                 .end    = 0xffdc001f,
 319                 .flags  = IORESOURCE_MEM,
 320         },
 321         [1] = {
 322                 .start  = 45,
 323                 .flags  = IORESOURCE_IRQ,
 324         },
 325 };
 326
 327 static struct platform_device tmu7_device = {
 328         .name           = "sh_tmu",
 329         .id             = 7,
 330         .dev = {
 331                 .platform_data  = &tmu7_platform_data,
 332         },
 333         .resource       = tmu7_resources,
 334         .num_resources  = ARRAY_SIZE(tmu7_resources),
 335 };
 336
 337 static struct sh_timer_config tmu8_platform_data = {
 338         .channel_offset = 0x1c,
 339         .timer_bit = 2,
 340 };
 341
 342 static struct resource tmu8_resources[] = {
 343         [0] = {
 344                 .start  = 0xffdc0020,
 345                 .end    = 0xffdc002b,
 346                 .flags  = IORESOURCE_MEM,
 347         },
 348         [1] = {
 349                 .start  = 45,
 350                 .flags  = IORESOURCE_IRQ,
 351         },
 352 };
 353
 354 static struct platform_device tmu8_device = {
 355         .name           = "sh_tmu",
 356         .id             = 8,
 357         .dev = {
 358                 .platform_data  = &tmu8_platform_data,
 359         },
 360         .resource       = tmu8_resources,
 361         .num_resources  = ARRAY_SIZE(tmu8_resources),
 362 };
 363
 364 static struct sh_timer_config tmu9_platform_data = {
 365         .channel_offset = 0x04,
 366         .timer_bit = 0,
 367 };
 368
 369 static struct resource tmu9_resources[] = {
 370         [0] = {
 371                 .start  = 0xffde0008,
 372                 .end    = 0xffde0013,
 373                 .flags  = IORESOURCE_MEM,
 374         },
 375         [1] = {
 376                 .start  = 46,
 377                 .flags  = IORESOURCE_IRQ,
 378         },
 379 };
 380
 381 static struct platform_device tmu9_device = {
 382         .name           = "sh_tmu",
 383         .id             = 9,
 384         .dev = {
 385                 .platform_data  = &tmu9_platform_data,
 386         },
 387         .resource       = tmu9_resources,
 388         .num_resources  = ARRAY_SIZE(tmu9_resources),
 389 };
 390
 391 static struct sh_timer_config tmu10_platform_data = {
 392         .channel_offset = 0x10,
 393         .timer_bit = 1,
 394 };
 395
 396 static struct resource tmu10_resources[] = {
 397         [0] = {
 398                 .start  = 0xffde0014,
 399                 .end    = 0xffde001f,
 400                 .flags  = IORESOURCE_MEM,
 401         },
 402         [1] = {
 403                 .start  = 46,
 404                 .flags  = IORESOURCE_IRQ,
 405         },
 406 };
 407
 408 static struct platform_device tmu10_device = {
 409         .name           = "sh_tmu",
 410         .id             = 10,
 411         .dev = {
 412                 .platform_data  = &tmu10_platform_data,
 413         },
 414         .resource       = tmu10_resources,
 415         .num_resources  = ARRAY_SIZE(tmu10_resources),
 416 };
 417
 418 static struct sh_timer_config tmu11_platform_data = {
 419         .channel_offset = 0x1c,
 420         .timer_bit = 2,
 421 };
 422
 423 static struct resource tmu11_resources[] = {
 424         [0] = {
 425                 .start  = 0xffde0020,
 426                 .end    = 0xffde002b,
 427                 .flags  = IORESOURCE_MEM,
 428         },
 429         [1] = {
 430                 .start  = 46,
 431                 .flags  = IORESOURCE_IRQ,
 432         },
 433 };
 434
 435 static struct platform_device tmu11_device = {
 436         .name           = "sh_tmu",
 437         .id             = 11,
 438         .dev = {
 439                 .platform_data  = &tmu11_platform_data,
 440         },
 441         .resource       = tmu11_resources,
 442         .num_resources  = ARRAY_SIZE(tmu11_resources),
 443 };
 444
 445 static struct resource usb_ohci_resources[] = {
 446         [0] = {
 447                 .start  = 0xffe70400,
 448                 .end    = 0xffe704ff,
 449                 .flags  = IORESOURCE_MEM,
 450         },
 451         [1] = {
 452                 .start  = 77,
 453                 .end    = 77,
 454                 .flags  = IORESOURCE_IRQ,
 455         },
 456 };
 457
 458 static u64 usb_ohci_dma_mask = DMA_BIT_MASK(32);
 459 static struct platform_device usb_ohci_device = {
 460         .name           = "sh_ohci",
 461         .id             = -1,
 462         .dev = {
 463                 .dma_mask               = &usb_ohci_dma_mask,
 464                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 465         },
 466         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
 467         .resource       = usb_ohci_resources,
 468 };
 469
 470 static struct platform_device *sh7786_early_devices[] __initdata = {
 471         &scif0_device,
 472         &scif1_device,
 473         &scif2_device,
 474         &scif3_device,
 475         &scif4_device,
 476         &scif5_device,
 477         &tmu0_device,
 478         &tmu1_device,
 479         &tmu2_device,
 480         &tmu3_device,
 481         &tmu4_device,
 482         &tmu5_device,
 483         &tmu6_device,
 484         &tmu7_device,
 485         &tmu8_device,
 486         &tmu9_device,
 487         &tmu10_device,
 488         &tmu11_device,
 489 };
 490
 491 static struct platform_device *sh7786_devices[] __initdata = {
 492         &usb_ohci_device,
 493 };
 494
 495
 496 /*
 497  * Please call this function if your platform board
 498  * use external clock for USB
 499  * */
 500 #define USBCTL0         0xffe70858
 501 #define CLOCK_MODE_MASK 0xffffff7f
 502 #define EXT_CLOCK_MODE  0x00000080
 503 void __init sh7786_usb_use_exclock(void)
 504 {
 505         u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
 506         __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
 507 }
 508
 509 #define USBINITREG1     0xffe70094
 510 #define USBINITREG2     0xffe7009c
 511 #define USBINITVAL1     0x00ff0040
 512 #define USBINITVAL2     0x00000001
 513
 514 #define USBPCTL1        0xffe70804
 515 #define USBST           0xffe70808
 516 #define PHY_ENB         0x00000001
 517 #define PLL_ENB         0x00000002
 518 #define PHY_RST         0x00000004
 519 #define ACT_PLL_STATUS  0xc0000000
 520 static void __init sh7786_usb_setup(void)
 521 {
 522         int i = 1000000;
 523
 524         /*
 525          * USB initial settings
 526          *
 527          * The following settings are necessary
 528          * for using the USB modules.
 529          *
 530          * see "USB Inital Settings" for detail
 531          */
 532         __raw_writel(USBINITVAL1, USBINITREG1);
 533         __raw_writel(USBINITVAL2, USBINITREG2);
 534
 535         /*
 536          * Set the PHY and PLL enable bit
 537          */
 538         __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
 539         while (i--) {
 540                 if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
 541                         /* Set the PHY RST bit */
 542                         __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
 543                         printk(KERN_INFO "sh7786 usb setup done\n");
 544                         break;
 545                 }
 546                 cpu_relax();
 547         }
 548 }
 549
 550 static int __init sh7786_devices_setup(void)
 551 {
 552         int ret;
 553
 554         sh7786_usb_setup();
 555
 556         ret = platform_add_devices(sh7786_early_devices,
 557                                    ARRAY_SIZE(sh7786_early_devices));
 558         if (unlikely(ret != 0))
 559                 return ret;
 560
 561         return platform_add_devices(sh7786_devices,
 562                                     ARRAY_SIZE(sh7786_devices));
 563 }
 564 arch_initcall(sh7786_devices_setup);
 565
 566 void __init plat_early_device_setup(void)
 567 {
 568         early_platform_add_devices(sh7786_early_devices,
 569                                    ARRAY_SIZE(sh7786_early_devices));
 570 }
 571
 572 enum {
 573         UNUSED = 0,
 574
 575         /* interrupt sources */
 576
 577         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 578         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 579         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 580         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 581
 582         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 583         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 584         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 585         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 586
 587         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 588         WDT,
 589         TMU0_0, TMU0_1, TMU0_2, TMU0_3,
 590         TMU1_0, TMU1_1, TMU1_2,
 591         DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
 592         HUDI1, HUDI0,
 593         DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
 594         HPB_0, HPB_1, HPB_2,
 595         SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
 596         SCIF1,
 597         TMU2, TMU3,
 598         SCIF2, SCIF3, SCIF4, SCIF5,
 599         Eth_0, Eth_1,
 600         PCIeC0_0, PCIeC0_1, PCIeC0_2,
 601         PCIeC1_0, PCIeC1_1, PCIeC1_2,
 602         USB,
 603         I2C0, I2C1,
 604         DU,
 605         SSI0, SSI1, SSI2, SSI3,
 606         PCIeC2_0, PCIeC2_1, PCIeC2_2,
 607         HAC0, HAC1,
 608         FLCTL,
 609         HSPI,
 610         GPIO0, GPIO1,
 611         Thermal,
 612         INTICI0, INTICI1, INTICI2, INTICI3,
 613         INTICI4, INTICI5, INTICI6, INTICI7,
 614 };
 615
 616 static struct intc_vect vectors[] __initdata = {
 617         INTC_VECT(WDT, 0x3e0),
 618         INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
 619         INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
 620         INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
 621         INTC_VECT(TMU1_2, 0x4c0),
 622         INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
 623         INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
 624         INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
 625         INTC_VECT(DMAC0_6, 0x5c0),
 626         INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
 627         INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
 628         INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
 629         INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
 630         INTC_VECT(HPB_2, 0x6e0),
 631         INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
 632         INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
 633         INTC_VECT(SCIF1, 0x780),
 634         INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
 635         INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
 636         INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
 637         INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
 638         INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
 639         INTC_VECT(PCIeC0_2, 0xb20),
 640         INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
 641         INTC_VECT(PCIeC1_2, 0xb80),
 642         INTC_VECT(USB, 0xba0),
 643         INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
 644         INTC_VECT(DU, 0xd00),
 645         INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
 646         INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
 647         INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
 648         INTC_VECT(PCIeC2_2, 0xde0),
 649         INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
 650         INTC_VECT(FLCTL, 0xe40),
 651         INTC_VECT(HSPI, 0xe80),
 652         INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
 653         INTC_VECT(Thermal, 0xee0),
 654         INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
 655         INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
 656         INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
 657         INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
 658 };
 659
 660 #define CnINTMSK0       0xfe410030
 661 #define CnINTMSK1       0xfe410040
 662 #define CnINTMSKCLR0    0xfe410050
 663 #define CnINTMSKCLR1    0xfe410060
 664 #define CnINT2MSKR0     0xfe410a20
 665 #define CnINT2MSKR1     0xfe410a24
 666 #define CnINT2MSKR2     0xfe410a28
 667 #define CnINT2MSKR3     0xfe410a2c
 668 #define CnINT2MSKCR0    0xfe410a30
 669 #define CnINT2MSKCR1    0xfe410a34
 670 #define CnINT2MSKCR2    0xfe410a38
 671 #define CnINT2MSKCR3    0xfe410a3c
 672 #define INTMSK2         0xfe410068
 673 #define INTMSKCLR2      0xfe41006c
 674
 675 static struct intc_mask_reg mask_registers[] __initdata = {
 676         { CnINTMSK0, CnINTMSKCLR0, 32,
 677           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 678         { INTMSK2, INTMSKCLR2, 32,
 679           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 680             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 681             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 682             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 683             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 684             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 685             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 686             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 687         { CnINT2MSKR0, CnINT2MSKCR0 , 32,
 688           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 689             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } },
 690         { CnINT2MSKR1, CnINT2MSKCR1, 32,
 691           { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
 692             DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
 693             HUDI1, HUDI0,
 694             DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
 695             HPB_0, HPB_1, HPB_2,
 696             SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
 697             SCIF1,
 698             TMU2, TMU3, 0, } },
 699         { CnINT2MSKR2, CnINT2MSKCR2, 32,
 700           { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
 701             Eth_0, Eth_1,
 702             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 703             PCIeC0_0, PCIeC0_1, PCIeC0_2,
 704             PCIeC1_0, PCIeC1_1, PCIeC1_2,
 705             USB, 0, 0 } },
 706         { CnINT2MSKR3, CnINT2MSKCR3, 32,
 707           { 0, 0, 0, 0, 0, 0,
 708             I2C0, I2C1,
 709             DU, SSI0, SSI1, SSI2, SSI3,
 710             PCIeC2_0, PCIeC2_1, PCIeC2_2,
 711             HAC0, HAC1,
 712             FLCTL, 0,
 713             HSPI, GPIO0, GPIO1, Thermal,
 714             0, 0, 0, 0, 0, 0, 0, 0 } },
 715 };
 716
 717 static struct intc_prio_reg prio_registers[] __initdata = {
 718         { 0xfe410010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
 719                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
 720         { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
 721         { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
 722                                                  TMU0_2, TMU0_3 } },
 723         { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
 724                                                  TMU1_2, 0 } },
 725         { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
 726                                                  DMAC0_2, DMAC0_3 } },
 727         { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
 728                                                  DMAC0_6, HUDI1 } },
 729         { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
 730                                                  DMAC1_1, DMAC1_2 } },
 731         { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
 732                                                  HPB_1, HPB_2 } },
 733         { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
 734                                                  SCIF0_2, SCIF0_3 } },
 735         { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
 736         { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
 737         { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
 738                                                   Eth_0, Eth_1 } },
 739         { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
 740         { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
 741         { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
 742         { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
 743         { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
 744                                                   PCIeC1_0, PCIeC1_1 } },
 745         { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
 746         { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
 747         { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
 748         { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
 749         { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
 750                                                   PCIeC2_1, PCIeC2_2 } },
 751         { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
 752         { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
 753                                                   GPIO1, Thermal } },
 754         { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
 755         { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
 756         { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
 757           { INTICI7, INTICI6, INTICI5, INTICI4,
 758             INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
 759 };
 760
 761 static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL,
 762                          mask_registers, prio_registers, NULL);
 763
 764 /* Support for external interrupt pins in IRQ mode */
 765
 766 static struct intc_vect vectors_irq0123[] __initdata = {
 767         INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
 768         INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
 769 };
 770
 771 static struct intc_vect vectors_irq4567[] __initdata = {
 772         INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
 773         INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
 774 };
 775
 776 static struct intc_sense_reg sense_registers[] __initdata = {
 777         { 0xfe41001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 778                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 779 };
 780
 781 static struct intc_mask_reg ack_registers[] __initdata = {
 782         { 0xfe410024, 0, 32, /* INTREQ */
 783           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 784 };
 785
 786 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
 787                              vectors_irq0123, NULL, mask_registers,
 788                              prio_registers, sense_registers, ack_registers);
 789
 790 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
 791                              vectors_irq4567, NULL, mask_registers,
 792                              prio_registers, sense_registers, ack_registers);
 793
 794 /* External interrupt pins in IRL mode */
 795
 796 static struct intc_vect vectors_irl0123[] __initdata = {
 797         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 798         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 799         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 800         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 801         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 802         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 803         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 804         INTC_VECT(IRL0_HHHL, 0x3c0),
 805 };
 806
 807 static struct intc_vect vectors_irl4567[] __initdata = {
 808         INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
 809         INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
 810         INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
 811         INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
 812         INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
 813         INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
 814         INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
 815         INTC_VECT(IRL4_HHHL, 0xac0),
 816 };
 817
 818 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
 819                          NULL, mask_registers, NULL, NULL);
 820
 821 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
 822                          NULL, mask_registers, NULL, NULL);
 823
 824 #define INTC_ICR0       0xfe410000
 825 #define INTC_INTMSK0    CnINTMSK0
 826 #define INTC_INTMSK1    CnINTMSK1
 827 #define INTC_INTMSK2    INTMSK2
 828 #define INTC_INTMSKCLR1 CnINTMSKCLR1
 829 #define INTC_INTMSKCLR2 INTMSKCLR2
 830
 831 void __init plat_irq_setup(void)
 832 {
 833         /* disable IRQ3-0 + IRQ7-4 */
 834         __raw_writel(0xff000000, INTC_INTMSK0);
 835
 836         /* disable IRL3-0 + IRL7-4 */
 837         __raw_writel(0xc0000000, INTC_INTMSK1);
 838         __raw_writel(0xfffefffe, INTC_INTMSK2);
 839
 840         /* select IRL mode for IRL3-0 + IRL7-4 */
 841         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 842
 843         register_intc_controller(&intc_desc);
 844 }
 845
 846 void __init plat_irq_setup_pins(int mode)
 847 {
 848         switch (mode) {
 849         case IRQ_MODE_IRQ7654:
 850                 /* select IRQ mode for IRL7-4 */
 851                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
 852                 register_intc_controller(&intc_desc_irq4567);
 853                 break;
 854         case IRQ_MODE_IRQ3210:
 855                 /* select IRQ mode for IRL3-0 */
 856                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 857                 register_intc_controller(&intc_desc_irq0123);
 858                 break;
 859         case IRQ_MODE_IRL7654:
 860                 /* enable IRL7-4 but don't provide any masking */
 861                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 862                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 863                 break;
 864         case IRQ_MODE_IRL3210:
 865                 /* enable IRL0-3 but don't provide any masking */
 866                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 867                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 868                 break;
 869         case IRQ_MODE_IRL7654_MASK:
 870                 /* enable IRL7-4 and mask using cpu intc controller */
 871                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 872                 register_intc_controller(&intc_desc_irl4567);
 873                 break;
 874         case IRQ_MODE_IRL3210_MASK:
 875                 /* enable IRL0-3 and mask using cpu intc controller */
 876                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 877                 register_intc_controller(&intc_desc_irl0123);
 878                 break;
 879         default:
 880                 BUG();
 881         }
 882 }
 883
 884 void __init plat_mem_setup(void)
 885 {
 886 }