arch/sh/kernel/cpu/sh4a/setup-sh7786.c

   1 /*
   2  * SH7786 Setup
   3  *
   4  * Copyright (C) 2009 - 2011  Renesas Solutions Corp.
   5  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
   6  * Paul Mundt <paul.mundt@renesas.com>
   7  *
   8  * Based on SH7785 Setup
   9  *
  10  *  Copyright (C) 2007  Paul Mundt
  11  *
  12  * This file is subject to the terms and conditions of the GNU General Public
  13  * License.  See the file "COPYING" in the main directory of this archive
  14  * for more details.
  15  */
  16 #include <linux/platform_device.h>
  17 #include <linux/init.h>
  18 #include <linux/serial.h>
  19 #include <linux/serial_sci.h>
  20 #include <linux/io.h>
  21 #include <linux/mm.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/sh_timer.h>
  24 #include <linux/sh_dma.h>
  25 #include <linux/sh_intc.h>
  26 #include <cpu/dma-register.h>
  27 #include <asm/mmzone.h>
  28
  29 static struct plat_sci_port scif0_platform_data = {
  30         .mapbase        = 0xffea0000,
  31         .flags          = UPF_BOOT_AUTOCONF,
  32         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  33         .scbrr_algo_id  = SCBRR_ALGO_1,
  34         .type           = PORT_SCIF,
  35         .irqs           = { 40, 41, 43, 42 },
  36         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  37 };
  38
  39 static struct platform_device scif0_device = {
  40         .name           = "sh-sci",
  41         .id             = 0,
  42         .dev            = {
  43                 .platform_data  = &scif0_platform_data,
  44         },
  45 };
  46
  47 /*
  48  * The rest of these all have multiplexed IRQs
  49  */
  50 static struct plat_sci_port scif1_platform_data = {
  51         .mapbase        = 0xffeb0000,
  52         .flags          = UPF_BOOT_AUTOCONF,
  53         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  54         .scbrr_algo_id  = SCBRR_ALGO_1,
  55         .type           = PORT_SCIF,
  56         .irqs           = { 44, 44, 44, 44 },
  57         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  58 };
  59
  60 static struct platform_device scif1_device = {
  61         .name           = "sh-sci",
  62         .id             = 1,
  63         .dev            = {
  64                 .platform_data  = &scif1_platform_data,
  65         },
  66 };
  67
  68 static struct plat_sci_port scif2_platform_data = {
  69         .mapbase        = 0xffec0000,
  70         .flags          = UPF_BOOT_AUTOCONF,
  71         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  72         .scbrr_algo_id  = SCBRR_ALGO_1,
  73         .type           = PORT_SCIF,
  74         .irqs           = { 50, 50, 50, 50 },
  75         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  76 };
  77
  78 static struct platform_device scif2_device = {
  79         .name           = "sh-sci",
  80         .id             = 2,
  81         .dev            = {
  82                 .platform_data  = &scif2_platform_data,
  83         },
  84 };
  85
  86 static struct plat_sci_port scif3_platform_data = {
  87         .mapbase        = 0xffed0000,
  88         .flags          = UPF_BOOT_AUTOCONF,
  89         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  90         .scbrr_algo_id  = SCBRR_ALGO_1,
  91         .type           = PORT_SCIF,
  92         .irqs           = { 51, 51, 51, 51 },
  93         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  94 };
  95
  96 static struct platform_device scif3_device = {
  97         .name           = "sh-sci",
  98         .id             = 3,
  99         .dev            = {
 100                 .platform_data  = &scif3_platform_data,
 101         },
 102 };
 103
 104 static struct plat_sci_port scif4_platform_data = {
 105         .mapbase        = 0xffee0000,
 106         .flags          = UPF_BOOT_AUTOCONF,
 107         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 108         .scbrr_algo_id  = SCBRR_ALGO_1,
 109         .type           = PORT_SCIF,
 110         .irqs           = { 52, 52, 52, 52 },
 111         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 112 };
 113
 114 static struct platform_device scif4_device = {
 115         .name           = "sh-sci",
 116         .id             = 4,
 117         .dev            = {
 118                 .platform_data  = &scif4_platform_data,
 119         },
 120 };
 121
 122 static struct plat_sci_port scif5_platform_data = {
 123         .mapbase        = 0xffef0000,
 124         .flags          = UPF_BOOT_AUTOCONF,
 125         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 126         .scbrr_algo_id  = SCBRR_ALGO_1,
 127         .type           = PORT_SCIF,
 128         .irqs           = { 53, 53, 53, 53 },
 129         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 130 };
 131
 132 static struct platform_device scif5_device = {
 133         .name           = "sh-sci",
 134         .id             = 5,
 135         .dev            = {
 136                 .platform_data  = &scif5_platform_data,
 137         },
 138 };
 139
 140 static struct sh_timer_config tmu0_platform_data = {
 141         .channel_offset = 0x04,
 142         .timer_bit = 0,
 143         .clockevent_rating = 200,
 144 };
 145
 146 static struct resource tmu0_resources[] = {
 147         [0] = {
 148                 .start  = 0xffd80008,
 149                 .end    = 0xffd80013,
 150                 .flags  = IORESOURCE_MEM,
 151         },
 152         [1] = {
 153                 .start  = 16,
 154                 .flags  = IORESOURCE_IRQ,
 155         },
 156 };
 157
 158 static struct platform_device tmu0_device = {
 159         .name           = "sh_tmu",
 160         .id             = 0,
 161         .dev = {
 162                 .platform_data  = &tmu0_platform_data,
 163         },
 164         .resource       = tmu0_resources,
 165         .num_resources  = ARRAY_SIZE(tmu0_resources),
 166 };
 167
 168 static struct sh_timer_config tmu1_platform_data = {
 169         .channel_offset = 0x10,
 170         .timer_bit = 1,
 171         .clocksource_rating = 200,
 172 };
 173
 174 static struct resource tmu1_resources[] = {
 175         [0] = {
 176                 .start  = 0xffd80014,
 177                 .end    = 0xffd8001f,
 178                 .flags  = IORESOURCE_MEM,
 179         },
 180         [1] = {
 181                 .start  = 17,
 182                 .flags  = IORESOURCE_IRQ,
 183         },
 184 };
 185
 186 static struct platform_device tmu1_device = {
 187         .name           = "sh_tmu",
 188         .id             = 1,
 189         .dev = {
 190                 .platform_data  = &tmu1_platform_data,
 191         },
 192         .resource       = tmu1_resources,
 193         .num_resources  = ARRAY_SIZE(tmu1_resources),
 194 };
 195
 196 static struct sh_timer_config tmu2_platform_data = {
 197         .channel_offset = 0x1c,
 198         .timer_bit = 2,
 199 };
 200
 201 static struct resource tmu2_resources[] = {
 202         [0] = {
 203                 .start  = 0xffd80020,
 204                 .end    = 0xffd8002f,
 205                 .flags  = IORESOURCE_MEM,
 206         },
 207         [1] = {
 208                 .start  = 18,
 209                 .flags  = IORESOURCE_IRQ,
 210         },
 211 };
 212
 213 static struct platform_device tmu2_device = {
 214         .name           = "sh_tmu",
 215         .id             = 2,
 216         .dev = {
 217                 .platform_data  = &tmu2_platform_data,
 218         },
 219         .resource       = tmu2_resources,
 220         .num_resources  = ARRAY_SIZE(tmu2_resources),
 221 };
 222
 223 static struct sh_timer_config tmu3_platform_data = {
 224         .channel_offset = 0x04,
 225         .timer_bit = 0,
 226 };
 227
 228 static struct resource tmu3_resources[] = {
 229         [0] = {
 230                 .start  = 0xffda0008,
 231                 .end    = 0xffda0013,
 232                 .flags  = IORESOURCE_MEM,
 233         },
 234         [1] = {
 235                 .start  = 20,
 236                 .flags  = IORESOURCE_IRQ,
 237         },
 238 };
 239
 240 static struct platform_device tmu3_device = {
 241         .name           = "sh_tmu",
 242         .id             = 3,
 243         .dev = {
 244                 .platform_data  = &tmu3_platform_data,
 245         },
 246         .resource       = tmu3_resources,
 247         .num_resources  = ARRAY_SIZE(tmu3_resources),
 248 };
 249
 250 static struct sh_timer_config tmu4_platform_data = {
 251         .channel_offset = 0x10,
 252         .timer_bit = 1,
 253 };
 254
 255 static struct resource tmu4_resources[] = {
 256         [0] = {
 257                 .start  = 0xffda0014,
 258                 .end    = 0xffda001f,
 259                 .flags  = IORESOURCE_MEM,
 260         },
 261         [1] = {
 262                 .start  = 21,
 263                 .flags  = IORESOURCE_IRQ,
 264         },
 265 };
 266
 267 static struct platform_device tmu4_device = {
 268         .name           = "sh_tmu",
 269         .id             = 4,
 270         .dev = {
 271                 .platform_data  = &tmu4_platform_data,
 272         },
 273         .resource       = tmu4_resources,
 274         .num_resources  = ARRAY_SIZE(tmu4_resources),
 275 };
 276
 277 static struct sh_timer_config tmu5_platform_data = {
 278         .channel_offset = 0x1c,
 279         .timer_bit = 2,
 280 };
 281
 282 static struct resource tmu5_resources[] = {
 283         [0] = {
 284                 .start  = 0xffda0020,
 285                 .end    = 0xffda002b,
 286                 .flags  = IORESOURCE_MEM,
 287         },
 288         [1] = {
 289                 .start  = 22,
 290                 .flags  = IORESOURCE_IRQ,
 291         },
 292 };
 293
 294 static struct platform_device tmu5_device = {
 295         .name           = "sh_tmu",
 296         .id             = 5,
 297         .dev = {
 298                 .platform_data  = &tmu5_platform_data,
 299         },
 300         .resource       = tmu5_resources,
 301         .num_resources  = ARRAY_SIZE(tmu5_resources),
 302 };
 303
 304 static struct sh_timer_config tmu6_platform_data = {
 305         .channel_offset = 0x04,
 306         .timer_bit = 0,
 307 };
 308
 309 static struct resource tmu6_resources[] = {
 310         [0] = {
 311                 .start  = 0xffdc0008,
 312                 .end    = 0xffdc0013,
 313                 .flags  = IORESOURCE_MEM,
 314         },
 315         [1] = {
 316                 .start  = 45,
 317                 .flags  = IORESOURCE_IRQ,
 318         },
 319 };
 320
 321 static struct platform_device tmu6_device = {
 322         .name           = "sh_tmu",
 323         .id             = 6,
 324         .dev = {
 325                 .platform_data  = &tmu6_platform_data,
 326         },
 327         .resource       = tmu6_resources,
 328         .num_resources  = ARRAY_SIZE(tmu6_resources),
 329 };
 330
 331 static struct sh_timer_config tmu7_platform_data = {
 332         .channel_offset = 0x10,
 333         .timer_bit = 1,
 334 };
 335
 336 static struct resource tmu7_resources[] = {
 337         [0] = {
 338                 .start  = 0xffdc0014,
 339                 .end    = 0xffdc001f,
 340                 .flags  = IORESOURCE_MEM,
 341         },
 342         [1] = {
 343                 .start  = 45,
 344                 .flags  = IORESOURCE_IRQ,
 345         },
 346 };
 347
 348 static struct platform_device tmu7_device = {
 349         .name           = "sh_tmu",
 350         .id             = 7,
 351         .dev = {
 352                 .platform_data  = &tmu7_platform_data,
 353         },
 354         .resource       = tmu7_resources,
 355         .num_resources  = ARRAY_SIZE(tmu7_resources),
 356 };
 357
 358 static struct sh_timer_config tmu8_platform_data = {
 359         .channel_offset = 0x1c,
 360         .timer_bit = 2,
 361 };
 362
 363 static struct resource tmu8_resources[] = {
 364         [0] = {
 365                 .start  = 0xffdc0020,
 366                 .end    = 0xffdc002b,
 367                 .flags  = IORESOURCE_MEM,
 368         },
 369         [1] = {
 370                 .start  = 45,
 371                 .flags  = IORESOURCE_IRQ,
 372         },
 373 };
 374
 375 static struct platform_device tmu8_device = {
 376         .name           = "sh_tmu",
 377         .id             = 8,
 378         .dev = {
 379                 .platform_data  = &tmu8_platform_data,
 380         },
 381         .resource       = tmu8_resources,
 382         .num_resources  = ARRAY_SIZE(tmu8_resources),
 383 };
 384
 385 static struct sh_timer_config tmu9_platform_data = {
 386         .channel_offset = 0x04,
 387         .timer_bit = 0,
 388 };
 389
 390 static struct resource tmu9_resources[] = {
 391         [0] = {
 392                 .start  = 0xffde0008,
 393                 .end    = 0xffde0013,
 394                 .flags  = IORESOURCE_MEM,
 395         },
 396         [1] = {
 397                 .start  = 46,
 398                 .flags  = IORESOURCE_IRQ,
 399         },
 400 };
 401
 402 static struct platform_device tmu9_device = {
 403         .name           = "sh_tmu",
 404         .id             = 9,
 405         .dev = {
 406                 .platform_data  = &tmu9_platform_data,
 407         },
 408         .resource       = tmu9_resources,
 409         .num_resources  = ARRAY_SIZE(tmu9_resources),
 410 };
 411
 412 static struct sh_timer_config tmu10_platform_data = {
 413         .channel_offset = 0x10,
 414         .timer_bit = 1,
 415 };
 416
 417 static struct resource tmu10_resources[] = {
 418         [0] = {
 419                 .start  = 0xffde0014,
 420                 .end    = 0xffde001f,
 421                 .flags  = IORESOURCE_MEM,
 422         },
 423         [1] = {
 424                 .start  = 46,
 425                 .flags  = IORESOURCE_IRQ,
 426         },
 427 };
 428
 429 static struct platform_device tmu10_device = {
 430         .name           = "sh_tmu",
 431         .id             = 10,
 432         .dev = {
 433                 .platform_data  = &tmu10_platform_data,
 434         },
 435         .resource       = tmu10_resources,
 436         .num_resources  = ARRAY_SIZE(tmu10_resources),
 437 };
 438
 439 static struct sh_timer_config tmu11_platform_data = {
 440         .channel_offset = 0x1c,
 441         .timer_bit = 2,
 442 };
 443
 444 static struct resource tmu11_resources[] = {
 445         [0] = {
 446                 .start  = 0xffde0020,
 447                 .end    = 0xffde002b,
 448                 .flags  = IORESOURCE_MEM,
 449         },
 450         [1] = {
 451                 .start  = 46,
 452                 .flags  = IORESOURCE_IRQ,
 453         },
 454 };
 455
 456 static struct platform_device tmu11_device = {
 457         .name           = "sh_tmu",
 458         .id             = 11,
 459         .dev = {
 460                 .platform_data  = &tmu11_platform_data,
 461         },
 462         .resource       = tmu11_resources,
 463         .num_resources  = ARRAY_SIZE(tmu11_resources),
 464 };
 465
 466 static const struct sh_dmae_channel dmac0_channels[] = {
 467         {
 468                 .offset = 0,
 469                 .dmars = 0,
 470                 .dmars_bit = 0,
 471         }, {
 472                 .offset = 0x10,
 473                 .dmars = 0,
 474                 .dmars_bit = 8,
 475         }, {
 476                 .offset = 0x20,
 477                 .dmars = 4,
 478                 .dmars_bit = 0,
 479         }, {
 480                 .offset = 0x30,
 481                 .dmars = 4,
 482                 .dmars_bit = 8,
 483         }, {
 484                 .offset = 0x50,
 485                 .dmars = 8,
 486                 .dmars_bit = 0,
 487         }, {
 488                 .offset = 0x60,
 489                 .dmars = 8,
 490                 .dmars_bit = 8,
 491         }
 492 };
 493
 494 static const unsigned int ts_shift[] = TS_SHIFT;
 495
 496 static struct sh_dmae_pdata dma0_platform_data = {
 497         .channel        = dmac0_channels,
 498         .channel_num    = ARRAY_SIZE(dmac0_channels),
 499         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 500         .ts_low_mask    = CHCR_TS_LOW_MASK,
 501         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 502         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 503         .ts_shift       = ts_shift,
 504         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 505         .dmaor_init     = DMAOR_INIT,
 506 };
 507
 508 /* Resource order important! */
 509 static struct resource dmac0_resources[] = {
 510         {
 511                 /* Channel registers and DMAOR */
 512                 .start  = 0xfe008020,
 513                 .end    = 0xfe00808f,
 514                 .flags  = IORESOURCE_MEM,
 515         }, {
 516                 /* DMARSx */
 517                 .start  = 0xfe009000,
 518                 .end    = 0xfe00900b,
 519                 .flags  = IORESOURCE_MEM,
 520         }, {
 521                 /* DMA error IRQ */
 522                 .start  = evt2irq(0x5c0),
 523                 .end    = evt2irq(0x5c0),
 524                 .flags  = IORESOURCE_IRQ,
 525         }, {
 526                 /* IRQ for channels 0-5 */
 527                 .start  = evt2irq(0x500),
 528                 .end    = evt2irq(0x5a0),
 529                 .flags  = IORESOURCE_IRQ,
 530         },
 531 };
 532
 533 static struct platform_device dma0_device = {
 534         .name           = "sh-dma-engine",
 535         .id             = 0,
 536         .resource       = dmac0_resources,
 537         .num_resources  = ARRAY_SIZE(dmac0_resources),
 538         .dev            = {
 539                 .platform_data  = &dma0_platform_data,
 540         },
 541 };
 542
 543 #define USB_EHCI_START 0xffe70000
 544 #define USB_OHCI_START 0xffe70400
 545
 546 static struct resource usb_ehci_resources[] = {
 547         [0] = {
 548                 .start  = USB_EHCI_START,
 549                 .end    = USB_EHCI_START + 0x3ff,
 550                 .flags  = IORESOURCE_MEM,
 551         },
 552         [1] = {
 553                 .start  = 77,
 554                 .end    = 77,
 555                 .flags  = IORESOURCE_IRQ,
 556         },
 557 };
 558
 559 static struct platform_device usb_ehci_device = {
 560         .name           = "sh_ehci",
 561         .id             = -1,
 562         .dev = {
 563                 .dma_mask               = &usb_ehci_device.dev.coherent_dma_mask,
 564                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 565         },
 566         .num_resources  = ARRAY_SIZE(usb_ehci_resources),
 567         .resource       = usb_ehci_resources,
 568 };
 569
 570 static struct resource usb_ohci_resources[] = {
 571         [0] = {
 572                 .start  = USB_OHCI_START,
 573                 .end    = USB_OHCI_START + 0x3ff,
 574                 .flags  = IORESOURCE_MEM,
 575         },
 576         [1] = {
 577                 .start  = 77,
 578                 .end    = 77,
 579                 .flags  = IORESOURCE_IRQ,
 580         },
 581 };
 582
 583 static struct platform_device usb_ohci_device = {
 584         .name           = "sh_ohci",
 585         .id             = -1,
 586         .dev = {
 587                 .dma_mask               = &usb_ohci_device.dev.coherent_dma_mask,
 588                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 589         },
 590         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
 591         .resource       = usb_ohci_resources,
 592 };
 593
 594 static struct platform_device *sh7786_early_devices[] __initdata = {
 595         &scif0_device,
 596         &scif1_device,
 597         &scif2_device,
 598         &scif3_device,
 599         &scif4_device,
 600         &scif5_device,
 601         &tmu0_device,
 602         &tmu1_device,
 603         &tmu2_device,
 604         &tmu3_device,
 605         &tmu4_device,
 606         &tmu5_device,
 607         &tmu6_device,
 608         &tmu7_device,
 609         &tmu8_device,
 610         &tmu9_device,
 611         &tmu10_device,
 612         &tmu11_device,
 613 };
 614
 615 static struct platform_device *sh7786_devices[] __initdata = {
 616         &dma0_device,
 617         &usb_ehci_device,
 618         &usb_ohci_device,
 619 };
 620
 621 /*
 622  * Please call this function if your platform board
 623  * use external clock for USB
 624  * */
 625 #define USBCTL0         0xffe70858
 626 #define CLOCK_MODE_MASK 0xffffff7f
 627 #define EXT_CLOCK_MODE  0x00000080
 628
 629 void __init sh7786_usb_use_exclock(void)
 630 {
 631         u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
 632         __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
 633 }
 634
 635 #define USBINITREG1     0xffe70094
 636 #define USBINITREG2     0xffe7009c
 637 #define USBINITVAL1     0x00ff0040
 638 #define USBINITVAL2     0x00000001
 639
 640 #define USBPCTL1        0xffe70804
 641 #define USBST           0xffe70808
 642 #define PHY_ENB         0x00000001
 643 #define PLL_ENB         0x00000002
 644 #define PHY_RST         0x00000004
 645 #define ACT_PLL_STATUS  0xc0000000
 646
 647 static void __init sh7786_usb_setup(void)
 648 {
 649         int i = 1000000;
 650
 651         /*
 652          * USB initial settings
 653          *
 654          * The following settings are necessary
 655          * for using the USB modules.
 656          *
 657          * see "USB Initial Settings" for detail
 658          */
 659         __raw_writel(USBINITVAL1, USBINITREG1);
 660         __raw_writel(USBINITVAL2, USBINITREG2);
 661
 662         /*
 663          * Set the PHY and PLL enable bit
 664          */
 665         __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
 666         while (i--) {
 667                 if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
 668                         /* Set the PHY RST bit */
 669                         __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
 670                         printk(KERN_INFO "sh7786 usb setup done\n");
 671                         break;
 672                 }
 673                 cpu_relax();
 674         }
 675 }
 676
 677 enum {
 678         UNUSED = 0,
 679
 680         /* interrupt sources */
 681         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 682         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 683         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 684         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 685
 686         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 687         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 688         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 689         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 690
 691         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 692         WDT,
 693         TMU0_0, TMU0_1, TMU0_2, TMU0_3,
 694         TMU1_0, TMU1_1, TMU1_2,
 695         DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
 696         HUDI1, HUDI0,
 697         DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
 698         HPB_0, HPB_1, HPB_2,
 699         SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
 700         SCIF1,
 701         TMU2, TMU3,
 702         SCIF2, SCIF3, SCIF4, SCIF5,
 703         Eth_0, Eth_1,
 704         PCIeC0_0, PCIeC0_1, PCIeC0_2,
 705         PCIeC1_0, PCIeC1_1, PCIeC1_2,
 706         USB,
 707         I2C0, I2C1,
 708         DU,
 709         SSI0, SSI1, SSI2, SSI3,
 710         PCIeC2_0, PCIeC2_1, PCIeC2_2,
 711         HAC0, HAC1,
 712         FLCTL,
 713         HSPI,
 714         GPIO0, GPIO1,
 715         Thermal,
 716         INTICI0, INTICI1, INTICI2, INTICI3,
 717         INTICI4, INTICI5, INTICI6, INTICI7,
 718
 719         /* Muxed sub-events */
 720         TXI1, BRI1, RXI1, ERI1,
 721 };
 722
 723 static struct intc_vect sh7786_vectors[] __initdata = {
 724         INTC_VECT(WDT, 0x3e0),
 725         INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
 726         INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
 727         INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
 728         INTC_VECT(TMU1_2, 0x4c0),
 729         INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
 730         INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
 731         INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
 732         INTC_VECT(DMAC0_6, 0x5c0),
 733         INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
 734         INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
 735         INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
 736         INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
 737         INTC_VECT(HPB_2, 0x6e0),
 738         INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
 739         INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
 740         INTC_VECT(SCIF1, 0x780),
 741         INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
 742         INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
 743         INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
 744         INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
 745         INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
 746         INTC_VECT(PCIeC0_2, 0xb20),
 747         INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
 748         INTC_VECT(PCIeC1_2, 0xb80),
 749         INTC_VECT(USB, 0xba0),
 750         INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
 751         INTC_VECT(DU, 0xd00),
 752         INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
 753         INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
 754         INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
 755         INTC_VECT(PCIeC2_2, 0xde0),
 756         INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
 757         INTC_VECT(FLCTL, 0xe40),
 758         INTC_VECT(HSPI, 0xe80),
 759         INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
 760         INTC_VECT(Thermal, 0xee0),
 761         INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
 762         INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
 763         INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
 764         INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
 765 };
 766
 767 #define CnINTMSK0       0xfe410030
 768 #define CnINTMSK1       0xfe410040
 769 #define CnINTMSKCLR0    0xfe410050
 770 #define CnINTMSKCLR1    0xfe410060
 771 #define CnINT2MSKR0     0xfe410a20
 772 #define CnINT2MSKR1     0xfe410a24
 773 #define CnINT2MSKR2     0xfe410a28
 774 #define CnINT2MSKR3     0xfe410a2c
 775 #define CnINT2MSKCR0    0xfe410a30
 776 #define CnINT2MSKCR1    0xfe410a34
 777 #define CnINT2MSKCR2    0xfe410a38
 778 #define CnINT2MSKCR3    0xfe410a3c
 779 #define INTMSK2         0xfe410068
 780 #define INTMSKCLR2      0xfe41006c
 781
 782 #define INTDISTCR0      0xfe4100b0
 783 #define INTDISTCR1      0xfe4100b4
 784 #define INT2DISTCR0     0xfe410900
 785 #define INT2DISTCR1     0xfe410904
 786 #define INT2DISTCR2     0xfe410908
 787 #define INT2DISTCR3     0xfe41090c
 788
 789 static struct intc_mask_reg sh7786_mask_registers[] __initdata = {
 790         { CnINTMSK0, CnINTMSKCLR0, 32,
 791           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
 792             INTC_SMP_BALANCING(INTDISTCR0) },
 793         { INTMSK2, INTMSKCLR2, 32,
 794           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 795             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 796             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 797             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 798             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 799             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 800             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 801             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 802         { CnINT2MSKR0, CnINT2MSKCR0 , 32,
 803           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 804             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT },
 805             INTC_SMP_BALANCING(INT2DISTCR0) },
 806         { CnINT2MSKR1, CnINT2MSKCR1, 32,
 807           { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
 808             DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
 809             HUDI1, HUDI0,
 810             DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
 811             HPB_0, HPB_1, HPB_2,
 812             SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
 813             SCIF1,
 814             TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },
 815         { CnINT2MSKR2, CnINT2MSKCR2, 32,
 816           { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
 817             Eth_0, Eth_1,
 818             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 819             PCIeC0_0, PCIeC0_1, PCIeC0_2,
 820             PCIeC1_0, PCIeC1_1, PCIeC1_2,
 821             USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) },
 822         { CnINT2MSKR3, CnINT2MSKCR3, 32,
 823           { 0, 0, 0, 0, 0, 0,
 824             I2C0, I2C1,
 825             DU, SSI0, SSI1, SSI2, SSI3,
 826             PCIeC2_0, PCIeC2_1, PCIeC2_2,
 827             HAC0, HAC1,
 828             FLCTL, 0,
 829             HSPI, GPIO0, GPIO1, Thermal,
 830             0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
 831 };
 832
 833 static struct intc_prio_reg sh7786_prio_registers[] __initdata = {
 834         { 0xfe410010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
 835                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
 836         { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
 837         { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
 838                                                  TMU0_2, TMU0_3 } },
 839         { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
 840                                                  TMU1_2, 0 } },
 841         { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
 842                                                  DMAC0_2, DMAC0_3 } },
 843         { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
 844                                                  DMAC0_6, HUDI1 } },
 845         { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
 846                                                  DMAC1_1, DMAC1_2 } },
 847         { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
 848                                                  HPB_1, HPB_2 } },
 849         { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
 850                                                  SCIF0_2, SCIF0_3 } },
 851         { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
 852         { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
 853         { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
 854                                                   Eth_0, Eth_1 } },
 855         { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
 856         { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
 857         { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
 858         { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
 859         { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
 860                                                   PCIeC1_0, PCIeC1_1 } },
 861         { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
 862         { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
 863         { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
 864         { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
 865         { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
 866                                                   PCIeC2_1, PCIeC2_2 } },
 867         { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
 868         { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
 869                                                   GPIO1, Thermal } },
 870         { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
 871         { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
 872         { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
 873           { INTICI7, INTICI6, INTICI5, INTICI4,
 874             INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
 875 };
 876
 877 static struct intc_subgroup sh7786_subgroups[] __initdata = {
 878         { 0xfe410c20, 32, SCIF1,
 879           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 880             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } },
 881 };
 882
 883 static struct intc_desc sh7786_intc_desc __initdata = {
 884         .name           = "sh7786",
 885         .hw             = {
 886                 .vectors        = sh7786_vectors,
 887                 .nr_vectors     = ARRAY_SIZE(sh7786_vectors),
 888                 .mask_regs      = sh7786_mask_registers,
 889                 .nr_mask_regs   = ARRAY_SIZE(sh7786_mask_registers),
 890                 .subgroups      = sh7786_subgroups,
 891                 .nr_subgroups   = ARRAY_SIZE(sh7786_subgroups),
 892                 .prio_regs      = sh7786_prio_registers,
 893                 .nr_prio_regs   = ARRAY_SIZE(sh7786_prio_registers),
 894         },
 895 };
 896
 897 /* Support for external interrupt pins in IRQ mode */
 898 static struct intc_vect vectors_irq0123[] __initdata = {
 899         INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
 900         INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
 901 };
 902
 903 static struct intc_vect vectors_irq4567[] __initdata = {
 904         INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
 905         INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
 906 };
 907
 908 static struct intc_sense_reg sh7786_sense_registers[] __initdata = {
 909         { 0xfe41001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 910                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 911 };
 912
 913 static struct intc_mask_reg sh7786_ack_registers[] __initdata = {
 914         { 0xfe410024, 0, 32, /* INTREQ */
 915           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 916 };
 917
 918 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
 919                              vectors_irq0123, NULL, sh7786_mask_registers,
 920                              sh7786_prio_registers, sh7786_sense_registers,
 921                              sh7786_ack_registers);
 922
 923 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
 924                              vectors_irq4567, NULL, sh7786_mask_registers,
 925                              sh7786_prio_registers, sh7786_sense_registers,
 926                              sh7786_ack_registers);
 927
 928 /* External interrupt pins in IRL mode */
 929
 930 static struct intc_vect vectors_irl0123[] __initdata = {
 931         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 932         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 933         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 934         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 935         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 936         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 937         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 938         INTC_VECT(IRL0_HHHL, 0x3c0),
 939 };
 940
 941 static struct intc_vect vectors_irl4567[] __initdata = {
 942         INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
 943         INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
 944         INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
 945         INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
 946         INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
 947         INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
 948         INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
 949         INTC_VECT(IRL4_HHHL, 0xac0),
 950 };
 951
 952 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
 953                          NULL, sh7786_mask_registers, NULL, NULL);
 954
 955 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
 956                          NULL, sh7786_mask_registers, NULL, NULL);
 957
 958 #define INTC_ICR0       0xfe410000
 959 #define INTC_INTMSK0    CnINTMSK0
 960 #define INTC_INTMSK1    CnINTMSK1
 961 #define INTC_INTMSK2    INTMSK2
 962 #define INTC_INTMSKCLR1 CnINTMSKCLR1
 963 #define INTC_INTMSKCLR2 INTMSKCLR2
 964
 965 void __init plat_irq_setup(void)
 966 {
 967         /* disable IRQ3-0 + IRQ7-4 */
 968         __raw_writel(0xff000000, INTC_INTMSK0);
 969
 970         /* disable IRL3-0 + IRL7-4 */
 971         __raw_writel(0xc0000000, INTC_INTMSK1);
 972         __raw_writel(0xfffefffe, INTC_INTMSK2);
 973
 974         /* select IRL mode for IRL3-0 + IRL7-4 */
 975         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 976
 977         register_intc_controller(&sh7786_intc_desc);
 978 }
 979
 980 void __init plat_irq_setup_pins(int mode)
 981 {
 982         switch (mode) {
 983         case IRQ_MODE_IRQ7654:
 984                 /* select IRQ mode for IRL7-4 */
 985                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
 986                 register_intc_controller(&intc_desc_irq4567);
 987                 break;
 988         case IRQ_MODE_IRQ3210:
 989                 /* select IRQ mode for IRL3-0 */
 990                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 991                 register_intc_controller(&intc_desc_irq0123);
 992                 break;
 993         case IRQ_MODE_IRL7654:
 994                 /* enable IRL7-4 but don't provide any masking */
 995                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 996                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 997                 break;
 998         case IRQ_MODE_IRL3210:
 999                 /* enable IRL0-3 but don't provide any masking */
1000                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
1001                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
1002                 break;
1003         case IRQ_MODE_IRL7654_MASK:
1004                 /* enable IRL7-4 and mask using cpu intc controller */
1005                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
1006                 register_intc_controller(&intc_desc_irl4567);
1007                 break;
1008         case IRQ_MODE_IRL3210_MASK:
1009                 /* enable IRL0-3 and mask using cpu intc controller */
1010                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
1011                 register_intc_controller(&intc_desc_irl0123);
1012                 break;
1013         default:
1014                 BUG();
1015         }
1016 }
1017
1018 void __init plat_mem_setup(void)
1019 {
1020 }
1021
1022 static int __init sh7786_devices_setup(void)
1023 {
1024         int ret, irq;
1025
1026         sh7786_usb_setup();
1027
1028         /*
1029          * De-mux SCIF1 IRQs if possible
1030          */
1031         irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
1032         if (irq > 0) {
1033                 scif1_platform_data.irqs[SCIx_TXI_IRQ] = irq;
1034                 scif1_platform_data.irqs[SCIx_ERI_IRQ] =
1035                         intc_irq_lookup(sh7786_intc_desc.name, ERI1);
1036                 scif1_platform_data.irqs[SCIx_BRI_IRQ] =
1037                         intc_irq_lookup(sh7786_intc_desc.name, BRI1);
1038                 scif1_platform_data.irqs[SCIx_RXI_IRQ] =
1039                         intc_irq_lookup(sh7786_intc_desc.name, RXI1);
1040         }
1041
1042         ret = platform_add_devices(sh7786_early_devices,
1043                                    ARRAY_SIZE(sh7786_early_devices));
1044         if (unlikely(ret != 0))
1045                 return ret;
1046
1047         return platform_add_devices(sh7786_devices,
1048                                     ARRAY_SIZE(sh7786_devices));
1049 }
1050 arch_initcall(sh7786_devices_setup);
1051
1052 void __init plat_early_device_setup(void)
1053 {
1054         early_platform_add_devices(sh7786_early_devices,
1055                                    ARRAY_SIZE(sh7786_early_devices));
1056 }