arch/sh/kernel/cpu/sh4a/setup-sh7757.c

   1 /*
   2  * SH7757 Setup
   3  *
   4  * Copyright (C) 2009  Renesas Solutions Corp.
   5  *
   6  *  based on setup-sh7785.c : Copyright (C) 2007  Paul Mundt
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/platform_device.h>
  13 #include <linux/init.h>
  14 #include <linux/serial.h>
  15 #include <linux/serial_sci.h>
  16 #include <linux/io.h>
  17 #include <linux/mm.h>
  18 #include <linux/sh_timer.h>
  19
  20 static struct plat_sci_port scif2_platform_data = {
  21         .mapbase        = 0xfe4b0000,           /* SCIF2 */
  22         .flags          = UPF_BOOT_AUTOCONF,
  23         .type           = PORT_SCIF,
  24         .irqs           = { 40, 40, 40, 40 },
  25 };
  26
  27 static struct platform_device scif2_device = {
  28         .name           = "sh-sci",
  29         .id             = 0,
  30         .dev            = {
  31                 .platform_data  = &scif2_platform_data,
  32         },
  33 };
  34
  35 static struct plat_sci_port scif3_platform_data = {
  36         .mapbase        = 0xfe4c0000,           /* SCIF3 */
  37         .flags          = UPF_BOOT_AUTOCONF,
  38         .type           = PORT_SCIF,
  39         .irqs           = { 76, 76, 76, 76 },
  40 };
  41
  42 static struct platform_device scif3_device = {
  43         .name           = "sh-sci",
  44         .id             = 1,
  45         .dev            = {
  46                 .platform_data  = &scif3_platform_data,
  47         },
  48 };
  49
  50 static struct plat_sci_port scif4_platform_data = {
  51         .mapbase        = 0xfe4d0000,           /* SCIF4 */
  52         .flags          = UPF_BOOT_AUTOCONF,
  53         .type           = PORT_SCIF,
  54         .irqs           = { 104, 104, 104, 104 },
  55 };
  56
  57 static struct platform_device scif4_device = {
  58         .name           = "sh-sci",
  59         .id             = 2,
  60         .dev            = {
  61                 .platform_data  = &scif4_platform_data,
  62         },
  63 };
  64
  65 static struct sh_timer_config tmu0_platform_data = {
  66         .channel_offset = 0x04,
  67         .timer_bit = 0,
  68         .clockevent_rating = 200,
  69 };
  70
  71 static struct resource tmu0_resources[] = {
  72         [0] = {
  73                 .start  = 0xfe430008,
  74                 .end    = 0xfe430013,
  75                 .flags  = IORESOURCE_MEM,
  76         },
  77         [1] = {
  78                 .start  = 28,
  79                 .flags  = IORESOURCE_IRQ,
  80         },
  81 };
  82
  83 static struct platform_device tmu0_device = {
  84         .name           = "sh_tmu",
  85         .id             = 0,
  86         .dev = {
  87                 .platform_data  = &tmu0_platform_data,
  88         },
  89         .resource       = tmu0_resources,
  90         .num_resources  = ARRAY_SIZE(tmu0_resources),
  91 };
  92
  93 static struct sh_timer_config tmu1_platform_data = {
  94         .channel_offset = 0x10,
  95         .timer_bit = 1,
  96         .clocksource_rating = 200,
  97 };
  98
  99 static struct resource tmu1_resources[] = {
 100         [0] = {
 101                 .start  = 0xfe430014,
 102                 .end    = 0xfe43001f,
 103                 .flags  = IORESOURCE_MEM,
 104         },
 105         [1] = {
 106                 .start  = 29,
 107                 .flags  = IORESOURCE_IRQ,
 108         },
 109 };
 110
 111 static struct platform_device tmu1_device = {
 112         .name           = "sh_tmu",
 113         .id             = 1,
 114         .dev = {
 115                 .platform_data  = &tmu1_platform_data,
 116         },
 117         .resource       = tmu1_resources,
 118         .num_resources  = ARRAY_SIZE(tmu1_resources),
 119 };
 120
 121 static struct platform_device *sh7757_devices[] __initdata = {
 122         &scif2_device,
 123         &scif3_device,
 124         &scif4_device,
 125         &tmu0_device,
 126         &tmu1_device,
 127 };
 128
 129 static int __init sh7757_devices_setup(void)
 130 {
 131         return platform_add_devices(sh7757_devices,
 132                                     ARRAY_SIZE(sh7757_devices));
 133 }
 134 arch_initcall(sh7757_devices_setup);
 135
 136 static struct platform_device *sh7757_early_devices[] __initdata = {
 137         &scif2_device,
 138         &scif3_device,
 139         &scif4_device,
 140         &tmu0_device,
 141         &tmu1_device,
 142 };
 143
 144 void __init plat_early_device_setup(void)
 145 {
 146         early_platform_add_devices(sh7757_early_devices,
 147                                    ARRAY_SIZE(sh7757_early_devices));
 148 }
 149
 150 enum {
 151         UNUSED = 0,
 152
 153         /* interrupt sources */
 154
 155         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 156         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 157         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 158         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 159
 160         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 161         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 162         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 163         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 164         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 165
 166         SDHI, DVC,
 167         IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15,
 168         TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
 169         HUDI,
 170         ARC4,
 171         DMAC0_5, DMAC6_7, DMAC8_11,
 172         SCIF0, SCIF1, SCIF2, SCIF3, SCIF4,
 173         USB0, USB1,
 174         JMC,
 175         SPI0, SPI1,
 176         TMR01, TMR23, TMR45,
 177         FRT,
 178         LPC, LPC5, LPC6, LPC7, LPC8,
 179         PECI0, PECI1, PECI2, PECI3, PECI4, PECI5,
 180         ETHERC,
 181         ADC0, ADC1,
 182         SIM,
 183         IIC0_0, IIC0_1, IIC0_2, IIC0_3,
 184         IIC1_0, IIC1_1, IIC1_2, IIC1_3,
 185         IIC2_0, IIC2_1, IIC2_2, IIC2_3,
 186         IIC3_0, IIC3_1, IIC3_2, IIC3_3,
 187         IIC4_0, IIC4_1, IIC4_2, IIC4_3,
 188         IIC5_0, IIC5_1, IIC5_2, IIC5_3,
 189         IIC6_0, IIC6_1, IIC6_2, IIC6_3,
 190         IIC7_0, IIC7_1, IIC7_2, IIC7_3,
 191         IIC8_0, IIC8_1, IIC8_2, IIC8_3,
 192         IIC9_0, IIC9_1, IIC9_2, IIC9_3,
 193         ONFICTL,
 194         MMC1, MMC2,
 195         ECCU,
 196         PCIC,
 197         G200,
 198         RSPI,
 199         SGPIO,
 200         DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19,
 201         DMINT20, DMINT21, DMINT22, DMINT23,
 202         DDRECC,
 203         TSIP,
 204         PCIE_BRIDGE,
 205         WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B,
 206         GETHER0, GETHER1, GETHER2,
 207         PBIA, PBIB, PBIC,
 208         DMAE2, DMAE3,
 209         SERMUX2, SERMUX3,
 210
 211         /* interrupt groups */
 212
 213         TMU012, TMU345,
 214 };
 215
 216 static struct intc_vect vectors[] __initdata = {
 217         INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
 218         INTC_VECT(SDHI, 0x4c0),
 219         INTC_VECT(DVC, 0x4e0),
 220         INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
 221         INTC_VECT(IRQ10, 0x540),
 222         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 223         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 224         INTC_VECT(HUDI, 0x600),
 225         INTC_VECT(ARC4, 0x620),
 226         INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660),
 227         INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0),
 228         INTC_VECT(DMAC0_5, 0x6c0),
 229         INTC_VECT(IRQ11, 0x6e0),
 230         INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
 231         INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
 232         INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0),
 233         INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0),
 234         INTC_VECT(USB0, 0x840),
 235         INTC_VECT(IRQ12, 0x880),
 236         INTC_VECT(JMC, 0x8a0),
 237         INTC_VECT(SPI1, 0x8c0),
 238         INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900),
 239         INTC_VECT(USB1, 0x920),
 240         INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
 241         INTC_VECT(TMR45, 0xa40),
 242         INTC_VECT(FRT, 0xa80),
 243         INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
 244         INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
 245         INTC_VECT(LPC, 0xb20),
 246         INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
 247         INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
 248         INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
 249         INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20),
 250         INTC_VECT(PECI2, 0xc40),
 251         INTC_VECT(IRQ15, 0xc60),
 252         INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
 253         INTC_VECT(SPI0, 0xcc0),
 254         INTC_VECT(ADC1, 0xce0),
 255         INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20),
 256         INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60),
 257         INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
 258         INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
 259         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 260         INTC_VECT(TMU5, 0xe40),
 261         INTC_VECT(ADC0, 0xe60),
 262         INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20),
 263         INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60),
 264         INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420),
 265         INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460),
 266         INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0),
 267         INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520),
 268         INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560),
 269         INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600),
 270         INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640),
 271         INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700),
 272         INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800),
 273         INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840),
 274         INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
 275         INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
 276         INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
 277         INTC_VECT(IIC6_2, 0x1920),
 278         INTC_VECT(ONFICTL, 0x1960),
 279         INTC_VECT(IIC6_3, 0x1980),
 280         INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
 281         INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
 282         INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
 283         INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
 284         INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
 285         INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
 286         INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80),
 287         INTC_VECT(ECCU, 0x1cc0),
 288         INTC_VECT(PCIC, 0x1ce0),
 289         INTC_VECT(G200, 0x1d00),
 290         INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0),
 291         INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0),
 292         INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0),
 293         INTC_VECT(PECI5, 0x1f00),
 294         INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0),
 295         INTC_VECT(SGPIO, 0x1fc0),
 296         INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420),
 297         INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460),
 298         INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0),
 299         INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520),
 300         INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560),
 301         INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600),
 302         INTC_VECT(DDRECC, 0x2620),
 303         INTC_VECT(TSIP, 0x2640),
 304         INTC_VECT(PCIE_BRIDGE, 0x27c0),
 305         INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820),
 306         INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860),
 307         INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0),
 308         INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0),
 309         INTC_VECT(WDT8B, 0x2900),
 310         INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980),
 311         INTC_VECT(GETHER2, 0x29a0),
 312         INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20),
 313         INTC_VECT(PBIC, 0x2a40),
 314         INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80),
 315         INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40),
 316         INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80),
 317         INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20),
 318 };
 319
 320 static struct intc_group groups[] __initdata = {
 321         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 322         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 323 };
 324
 325 static struct intc_mask_reg mask_registers[] __initdata = {
 326         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 327           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 328
 329         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 330           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 331             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 332             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 333             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 334             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 335             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 336             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 337             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 338
 339         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 340           { 0, 0, 0, 0, 0, 0, 0, 0,
 341             0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45,
 342             TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5,
 343             HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012
 344              } },
 345
 346         { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
 347           { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
 348             IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
 349             ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1,
 350             ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
 351              } },
 352
 353         { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
 354           { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0,
 355             0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
 356             IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
 357             IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2
 358              } },
 359
 360         { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */
 361           { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2,
 362             IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
 363             PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3,
 364             IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
 365              } },
 366
 367         { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */
 368           { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0,
 369             0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC,
 370             PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP,
 371             DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22
 372              } },
 373
 374         { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */
 375           { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0,
 376             DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0,
 377             0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8,
 378             DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17
 379              } },
 380 };
 381
 382 #define INTPRI          0xffd00010
 383 #define INT2PRI0        0xffd40000
 384 #define INT2PRI1        0xffd40004
 385 #define INT2PRI2        0xffd40008
 386 #define INT2PRI3        0xffd4000c
 387 #define INT2PRI4        0xffd40010
 388 #define INT2PRI5        0xffd40014
 389 #define INT2PRI6        0xffd40018
 390 #define INT2PRI7        0xffd4001c
 391 #define INT2PRI8        0xffd400a0
 392 #define INT2PRI9        0xffd400a4
 393 #define INT2PRI10       0xffd400a8
 394 #define INT2PRI11       0xffd400ac
 395 #define INT2PRI12       0xffd400b0
 396 #define INT2PRI13       0xffd400b4
 397 #define INT2PRI14       0xffd400b8
 398 #define INT2PRI15       0xffd400bc
 399 #define INT2PRI16       0xffd10000
 400 #define INT2PRI17       0xffd10004
 401 #define INT2PRI18       0xffd10008
 402 #define INT2PRI19       0xffd1000c
 403 #define INT2PRI20       0xffd10010
 404 #define INT2PRI21       0xffd10014
 405 #define INT2PRI22       0xffd10018
 406 #define INT2PRI23       0xffd1001c
 407 #define INT2PRI24       0xffd100a0
 408 #define INT2PRI25       0xffd100a4
 409 #define INT2PRI26       0xffd100a8
 410 #define INT2PRI27       0xffd100ac
 411 #define INT2PRI28       0xffd100b0
 412 #define INT2PRI29       0xffd100b4
 413 #define INT2PRI30       0xffd100b8
 414 #define INT2PRI31       0xffd100bc
 415 #define INT2PRI32       0xffd20000
 416 #define INT2PRI33       0xffd20004
 417 #define INT2PRI34       0xffd20008
 418 #define INT2PRI35       0xffd2000c
 419 #define INT2PRI36       0xffd20010
 420 #define INT2PRI37       0xffd20014
 421 #define INT2PRI38       0xffd20018
 422 #define INT2PRI39       0xffd2001c
 423 #define INT2PRI40       0xffd200a0
 424 #define INT2PRI41       0xffd200a4
 425 #define INT2PRI42       0xffd200a8
 426 #define INT2PRI43       0xffd200ac
 427 #define INT2PRI44       0xffd200b0
 428 #define INT2PRI45       0xffd200b4
 429 #define INT2PRI46       0xffd200b8
 430 #define INT2PRI47       0xffd200bc
 431
 432 static struct intc_prio_reg prio_registers[] __initdata = {
 433         { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
 434                               IRQ4, IRQ5, IRQ6, IRQ7 } },
 435
 436         { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
 437         { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
 438         { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } },
 439         { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } },
 440         { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
 441         { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } },
 442         { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } },
 443         { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
 444         { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
 445         { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
 446         { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } },
 447         { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } },
 448         { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
 449         { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
 450
 451         { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
 452         { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } },
 453         { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
 454         { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
 455         { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
 456         { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
 457         { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } },
 458         { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } },
 459         { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } },
 460         { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
 461         { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } },
 462         { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } },
 463         { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } },
 464         { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
 465         { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } },
 466         { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
 467         { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } },
 468         { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } },
 469         { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } },
 470         { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } },
 471         { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } },
 472         { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } },
 473         { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } },
 474         { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } },
 475         { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } },
 476         { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } },
 477         { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } },
 478         { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } },
 479         { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } },
 480         { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } },
 481         { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } },
 482         { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } },
 483 };
 484
 485 static struct intc_sense_reg sense_registers_irq8to15[] __initdata = {
 486         { 0xffd100f8, 32, 2, /* ICR2 */   { IRQ15, IRQ14, IRQ13, IRQ12,
 487                                             IRQ11, IRQ10, IRQ9, IRQ8 } },
 488 };
 489
 490 static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
 491                          mask_registers, prio_registers,
 492                          sense_registers_irq8to15);
 493
 494 /* Support for external interrupt pins in IRQ mode */
 495 static struct intc_vect vectors_irq0123[] __initdata = {
 496         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 497         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 498 };
 499
 500 static struct intc_vect vectors_irq4567[] __initdata = {
 501         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 502         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 503 };
 504
 505 static struct intc_sense_reg sense_registers[] __initdata = {
 506         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 507                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 508 };
 509
 510 static struct intc_mask_reg ack_registers[] __initdata = {
 511         { 0xffd00024, 0, 32, /* INTREQ */
 512           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 513 };
 514
 515 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123",
 516                              vectors_irq0123, NULL, mask_registers,
 517                              prio_registers, sense_registers, ack_registers);
 518
 519 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567",
 520                              vectors_irq4567, NULL, mask_registers,
 521                              prio_registers, sense_registers, ack_registers);
 522
 523 /* External interrupt pins in IRL mode */
 524 static struct intc_vect vectors_irl0123[] __initdata = {
 525         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 526         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 527         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 528         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 529         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 530         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 531         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 532         INTC_VECT(IRL0_HHHL, 0x3c0),
 533 };
 534
 535 static struct intc_vect vectors_irl4567[] __initdata = {
 536         INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
 537         INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
 538         INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
 539         INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
 540         INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
 541         INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
 542         INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
 543         INTC_VECT(IRL4_HHHL, 0xcc0),
 544 };
 545
 546 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
 547                          NULL, mask_registers, NULL, NULL);
 548
 549 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
 550                          NULL, mask_registers, NULL, NULL);
 551
 552 #define INTC_ICR0       0xffd00000
 553 #define INTC_INTMSK0    0xffd00044
 554 #define INTC_INTMSK1    0xffd00048
 555 #define INTC_INTMSK2    0xffd40080
 556 #define INTC_INTMSKCLR1 0xffd00068
 557 #define INTC_INTMSKCLR2 0xffd40084
 558
 559 void __init plat_irq_setup(void)
 560 {
 561         /* disable IRQ3-0 + IRQ7-4 */
 562         __raw_writel(0xff000000, INTC_INTMSK0);
 563
 564         /* disable IRL3-0 + IRL7-4 */
 565         __raw_writel(0xc0000000, INTC_INTMSK1);
 566         __raw_writel(0xfffefffe, INTC_INTMSK2);
 567
 568         /* select IRL mode for IRL3-0 + IRL7-4 */
 569         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 570
 571         /* disable holding function, ie enable "SH-4 Mode" */
 572         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 573
 574         register_intc_controller(&intc_desc);
 575 }
 576
 577 void __init plat_irq_setup_pins(int mode)
 578 {
 579         switch (mode) {
 580         case IRQ_MODE_IRQ7654:
 581                 /* select IRQ mode for IRL7-4 */
 582                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
 583                 register_intc_controller(&intc_desc_irq4567);
 584                 break;
 585         case IRQ_MODE_IRQ3210:
 586                 /* select IRQ mode for IRL3-0 */
 587                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 588                 register_intc_controller(&intc_desc_irq0123);
 589                 break;
 590         case IRQ_MODE_IRL7654:
 591                 /* enable IRL7-4 but don't provide any masking */
 592                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 593                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 594                 break;
 595         case IRQ_MODE_IRL3210:
 596                 /* enable IRL0-3 but don't provide any masking */
 597                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 598                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 599                 break;
 600         case IRQ_MODE_IRL7654_MASK:
 601                 /* enable IRL7-4 and mask using cpu intc controller */
 602                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 603                 register_intc_controller(&intc_desc_irl4567);
 604                 break;
 605         case IRQ_MODE_IRL3210_MASK:
 606                 /* enable IRL0-3 and mask using cpu intc controller */
 607                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 608                 register_intc_controller(&intc_desc_irl0123);
 609                 break;
 610         default:
 611                 BUG();
 612         }
 613 }
 614
 615 void __init plat_mem_setup(void)
 616 {
 617 }