4 * Copyright (C) 2009 Renesas Solutions Corp.
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 * Based on SH7723 Setup
9 * Copyright (C) 2008 Paul Mundt
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
15 #include <linux/platform_device.h>
16 #include <linux/init.h>
17 #include <linux/serial.h>
19 #include <linux/serial_sci.h>
20 #include <linux/uio_driver.h>
21 #include <linux/sh_timer.h>
23 #include <linux/notifier.h>
25 #include <asm/suspend.h>
26 #include <asm/clock.h>
27 #include <asm/dmaengine.h>
28 #include <asm/mmzone.h>
30 #include <cpu/dma-register.h>
31 #include <cpu/sh7724.h>
34 static struct sh_dmae_channel sh7724_dmae0_channels[] = {
62 static struct sh_dmae_channel sh7724_dmae1_channels[] = {
90 static unsigned int ts_shift[] = TS_SHIFT;
92 static struct sh_dmae_pdata dma0_platform_data = {
93 .channel = sh7724_dmae0_channels,
94 .channel_num = ARRAY_SIZE(sh7724_dmae0_channels),
95 .ts_low_shift = CHCR_TS_LOW_SHIFT,
96 .ts_low_mask = CHCR_TS_LOW_MASK,
97 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
98 .ts_high_mask = CHCR_TS_HIGH_MASK,
100 .ts_shift_num = ARRAY_SIZE(ts_shift),
101 .dmaor_init = DMAOR_INIT,
104 static struct sh_dmae_pdata dma1_platform_data = {
105 .channel = sh7724_dmae1_channels,
106 .channel_num = ARRAY_SIZE(sh7724_dmae1_channels),
107 .ts_low_shift = CHCR_TS_LOW_SHIFT,
108 .ts_low_mask = CHCR_TS_LOW_MASK,
109 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
110 .ts_high_mask = CHCR_TS_HIGH_MASK,
111 .ts_shift = ts_shift,
112 .ts_shift_num = ARRAY_SIZE(ts_shift),
113 .dmaor_init = DMAOR_INIT,
116 /* Resource order important! */
117 static struct resource sh7724_dmae0_resources[] = {
119 /* Channel registers and DMAOR */
122 .flags = IORESOURCE_MEM,
128 .flags = IORESOURCE_MEM,
134 .flags = IORESOURCE_IRQ,
137 /* IRQ for channels 0-3 */
140 .flags = IORESOURCE_IRQ,
143 /* IRQ for channels 4-5 */
146 .flags = IORESOURCE_IRQ,
150 /* Resource order important! */
151 static struct resource sh7724_dmae1_resources[] = {
153 /* Channel registers and DMAOR */
156 .flags = IORESOURCE_MEM,
162 .flags = IORESOURCE_MEM,
168 .flags = IORESOURCE_IRQ,
171 /* IRQ for channels 0-3 */
174 .flags = IORESOURCE_IRQ,
177 /* IRQ for channels 4-5 */
180 .flags = IORESOURCE_IRQ,
184 static struct platform_device dma0_device = {
185 .name = "sh-dma-engine",
187 .resource = sh7724_dmae0_resources,
188 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources),
190 .platform_data = &dma0_platform_data,
193 .hwblk_id = HWBLK_DMAC0,
197 static struct platform_device dma1_device = {
198 .name = "sh-dma-engine",
200 .resource = sh7724_dmae1_resources,
201 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources),
203 .platform_data = &dma1_platform_data,
206 .hwblk_id = HWBLK_DMAC1,
211 static struct plat_sci_port scif0_platform_data = {
212 .mapbase = 0xffe00000,
213 .flags = UPF_BOOT_AUTOCONF,
215 .irqs = { 80, 80, 80, 80 },
219 static struct platform_device scif0_device = {
223 .platform_data = &scif0_platform_data,
227 static struct plat_sci_port scif1_platform_data = {
228 .mapbase = 0xffe10000,
229 .flags = UPF_BOOT_AUTOCONF,
231 .irqs = { 81, 81, 81, 81 },
235 static struct platform_device scif1_device = {
239 .platform_data = &scif1_platform_data,
243 static struct plat_sci_port scif2_platform_data = {
244 .mapbase = 0xffe20000,
245 .flags = UPF_BOOT_AUTOCONF,
247 .irqs = { 82, 82, 82, 82 },
251 static struct platform_device scif2_device = {
255 .platform_data = &scif2_platform_data,
259 static struct plat_sci_port scif3_platform_data = {
260 .mapbase = 0xa4e30000,
261 .flags = UPF_BOOT_AUTOCONF,
263 .irqs = { 56, 56, 56, 56 },
267 static struct platform_device scif3_device = {
271 .platform_data = &scif3_platform_data,
275 static struct plat_sci_port scif4_platform_data = {
276 .mapbase = 0xa4e40000,
277 .flags = UPF_BOOT_AUTOCONF,
279 .irqs = { 88, 88, 88, 88 },
283 static struct platform_device scif4_device = {
287 .platform_data = &scif4_platform_data,
291 static struct plat_sci_port scif5_platform_data = {
292 .mapbase = 0xa4e50000,
293 .flags = UPF_BOOT_AUTOCONF,
295 .irqs = { 109, 109, 109, 109 },
299 static struct platform_device scif5_device = {
303 .platform_data = &scif5_platform_data,
308 static struct resource rtc_resources[] = {
311 .end = 0xa465fec0 + 0x58 - 1,
312 .flags = IORESOURCE_IO,
317 .flags = IORESOURCE_IRQ,
322 .flags = IORESOURCE_IRQ,
327 .flags = IORESOURCE_IRQ,
331 static struct platform_device rtc_device = {
334 .num_resources = ARRAY_SIZE(rtc_resources),
335 .resource = rtc_resources,
337 .hwblk_id = HWBLK_RTC,
342 static struct resource iic0_resources[] = {
346 .end = 0x04470018 - 1,
347 .flags = IORESOURCE_MEM,
352 .flags = IORESOURCE_IRQ,
356 static struct platform_device iic0_device = {
357 .name = "i2c-sh_mobile",
358 .id = 0, /* "i2c0" clock */
359 .num_resources = ARRAY_SIZE(iic0_resources),
360 .resource = iic0_resources,
362 .hwblk_id = HWBLK_IIC0,
367 static struct resource iic1_resources[] = {
371 .end = 0x04750018 - 1,
372 .flags = IORESOURCE_MEM,
377 .flags = IORESOURCE_IRQ,
381 static struct platform_device iic1_device = {
382 .name = "i2c-sh_mobile",
383 .id = 1, /* "i2c1" clock */
384 .num_resources = ARRAY_SIZE(iic1_resources),
385 .resource = iic1_resources,
387 .hwblk_id = HWBLK_IIC1,
392 static struct uio_info vpu_platform_data = {
398 static struct resource vpu_resources[] = {
403 .flags = IORESOURCE_MEM,
406 /* place holder for contiguous memory */
410 static struct platform_device vpu_device = {
411 .name = "uio_pdrv_genirq",
414 .platform_data = &vpu_platform_data,
416 .resource = vpu_resources,
417 .num_resources = ARRAY_SIZE(vpu_resources),
419 .hwblk_id = HWBLK_VPU,
424 static struct uio_info veu0_platform_data = {
430 static struct resource veu0_resources[] = {
435 .flags = IORESOURCE_MEM,
438 /* place holder for contiguous memory */
442 static struct platform_device veu0_device = {
443 .name = "uio_pdrv_genirq",
446 .platform_data = &veu0_platform_data,
448 .resource = veu0_resources,
449 .num_resources = ARRAY_SIZE(veu0_resources),
451 .hwblk_id = HWBLK_VEU0,
456 static struct uio_info veu1_platform_data = {
462 static struct resource veu1_resources[] = {
467 .flags = IORESOURCE_MEM,
470 /* place holder for contiguous memory */
474 static struct platform_device veu1_device = {
475 .name = "uio_pdrv_genirq",
478 .platform_data = &veu1_platform_data,
480 .resource = veu1_resources,
481 .num_resources = ARRAY_SIZE(veu1_resources),
483 .hwblk_id = HWBLK_VEU1,
487 static struct sh_timer_config cmt_platform_data = {
489 .channel_offset = 0x60,
492 .clockevent_rating = 125,
493 .clocksource_rating = 200,
496 static struct resource cmt_resources[] = {
501 .flags = IORESOURCE_MEM,
505 .flags = IORESOURCE_IRQ,
509 static struct platform_device cmt_device = {
513 .platform_data = &cmt_platform_data,
515 .resource = cmt_resources,
516 .num_resources = ARRAY_SIZE(cmt_resources),
518 .hwblk_id = HWBLK_CMT,
522 static struct sh_timer_config tmu0_platform_data = {
524 .channel_offset = 0x04,
527 .clockevent_rating = 200,
530 static struct resource tmu0_resources[] = {
535 .flags = IORESOURCE_MEM,
539 .flags = IORESOURCE_IRQ,
543 static struct platform_device tmu0_device = {
547 .platform_data = &tmu0_platform_data,
549 .resource = tmu0_resources,
550 .num_resources = ARRAY_SIZE(tmu0_resources),
552 .hwblk_id = HWBLK_TMU0,
556 static struct sh_timer_config tmu1_platform_data = {
558 .channel_offset = 0x10,
561 .clocksource_rating = 200,
564 static struct resource tmu1_resources[] = {
569 .flags = IORESOURCE_MEM,
573 .flags = IORESOURCE_IRQ,
577 static struct platform_device tmu1_device = {
581 .platform_data = &tmu1_platform_data,
583 .resource = tmu1_resources,
584 .num_resources = ARRAY_SIZE(tmu1_resources),
586 .hwblk_id = HWBLK_TMU0,
590 static struct sh_timer_config tmu2_platform_data = {
592 .channel_offset = 0x1c,
597 static struct resource tmu2_resources[] = {
602 .flags = IORESOURCE_MEM,
606 .flags = IORESOURCE_IRQ,
610 static struct platform_device tmu2_device = {
614 .platform_data = &tmu2_platform_data,
616 .resource = tmu2_resources,
617 .num_resources = ARRAY_SIZE(tmu2_resources),
619 .hwblk_id = HWBLK_TMU0,
624 static struct sh_timer_config tmu3_platform_data = {
626 .channel_offset = 0x04,
631 static struct resource tmu3_resources[] = {
636 .flags = IORESOURCE_MEM,
640 .flags = IORESOURCE_IRQ,
644 static struct platform_device tmu3_device = {
648 .platform_data = &tmu3_platform_data,
650 .resource = tmu3_resources,
651 .num_resources = ARRAY_SIZE(tmu3_resources),
653 .hwblk_id = HWBLK_TMU1,
657 static struct sh_timer_config tmu4_platform_data = {
659 .channel_offset = 0x10,
664 static struct resource tmu4_resources[] = {
669 .flags = IORESOURCE_MEM,
673 .flags = IORESOURCE_IRQ,
677 static struct platform_device tmu4_device = {
681 .platform_data = &tmu4_platform_data,
683 .resource = tmu4_resources,
684 .num_resources = ARRAY_SIZE(tmu4_resources),
686 .hwblk_id = HWBLK_TMU1,
690 static struct sh_timer_config tmu5_platform_data = {
692 .channel_offset = 0x1c,
697 static struct resource tmu5_resources[] = {
702 .flags = IORESOURCE_MEM,
706 .flags = IORESOURCE_IRQ,
710 static struct platform_device tmu5_device = {
714 .platform_data = &tmu5_platform_data,
716 .resource = tmu5_resources,
717 .num_resources = ARRAY_SIZE(tmu5_resources),
719 .hwblk_id = HWBLK_TMU1,
724 static struct uio_info jpu_platform_data = {
730 static struct resource jpu_resources[] = {
735 .flags = IORESOURCE_MEM,
738 /* place holder for contiguous memory */
742 static struct platform_device jpu_device = {
743 .name = "uio_pdrv_genirq",
746 .platform_data = &jpu_platform_data,
748 .resource = jpu_resources,
749 .num_resources = ARRAY_SIZE(jpu_resources),
751 .hwblk_id = HWBLK_JPU,
756 static struct uio_info spu0_platform_data = {
762 static struct resource spu0_resources[] = {
767 .flags = IORESOURCE_MEM,
770 /* place holder for contiguous memory */
774 static struct platform_device spu0_device = {
775 .name = "uio_pdrv_genirq",
778 .platform_data = &spu0_platform_data,
780 .resource = spu0_resources,
781 .num_resources = ARRAY_SIZE(spu0_resources),
783 .hwblk_id = HWBLK_SPU,
788 static struct uio_info spu1_platform_data = {
794 static struct resource spu1_resources[] = {
799 .flags = IORESOURCE_MEM,
802 /* place holder for contiguous memory */
806 static struct platform_device spu1_device = {
807 .name = "uio_pdrv_genirq",
810 .platform_data = &spu1_platform_data,
812 .resource = spu1_resources,
813 .num_resources = ARRAY_SIZE(spu1_resources),
815 .hwblk_id = HWBLK_SPU,
819 static struct platform_device *sh7724_devices[] __initdata = {
846 static int __init sh7724_devices_setup(void)
848 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
849 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
850 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
851 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
852 platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20);
853 platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20);
855 return platform_add_devices(sh7724_devices,
856 ARRAY_SIZE(sh7724_devices));
858 arch_initcall(sh7724_devices_setup);
860 static struct platform_device *sh7724_early_devices[] __initdata = {
876 void __init plat_early_device_setup(void)
878 early_platform_add_devices(sh7724_early_devices,
879 ARRAY_SIZE(sh7724_early_devices));
882 #define RAMCR_CACHE_L2FC 0x0002
883 #define RAMCR_CACHE_L2E 0x0001
884 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
886 void l2_cache_init(void)
888 /* Enable L2 cache */
889 __raw_writel(L2_CACHE_ENABLE, RAMCR);
897 /* interrupt sources */
898 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
900 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
901 _2DG_TRI, _2DG_INI, _2DG_CEI,
902 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
903 VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU,
911 RTC_ATI, RTC_PRI, RTC_CUI,
912 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
913 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
915 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
917 MSIOF_MSIOFI0, MSIOF_MSIOFI1,
918 SPU_SPUI0, SPU_SPUI1,
922 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
923 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
928 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
932 MMC_MMC2I, MMC_MMC3I,
934 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
936 /* interrupt groups */
937 DMAC1A, _2DG, DMAC0A, VIO, USB, RTC,
938 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF,
941 static struct intc_vect vectors[] __initdata = {
942 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
943 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
944 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
945 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
947 INTC_VECT(DMAC1A_DEI0, 0x700),
948 INTC_VECT(DMAC1A_DEI1, 0x720),
949 INTC_VECT(DMAC1A_DEI2, 0x740),
950 INTC_VECT(DMAC1A_DEI3, 0x760),
952 INTC_VECT(_2DG_TRI, 0x780),
953 INTC_VECT(_2DG_INI, 0x7A0),
954 INTC_VECT(_2DG_CEI, 0x7C0),
956 INTC_VECT(DMAC0A_DEI0, 0x800),
957 INTC_VECT(DMAC0A_DEI1, 0x820),
958 INTC_VECT(DMAC0A_DEI2, 0x840),
959 INTC_VECT(DMAC0A_DEI3, 0x860),
961 INTC_VECT(VIO_CEU0, 0x880),
962 INTC_VECT(VIO_BEU0, 0x8A0),
963 INTC_VECT(VIO_VEU1, 0x8C0),
964 INTC_VECT(VIO_VOU, 0x8E0),
966 INTC_VECT(SCIFA3, 0x900),
967 INTC_VECT(VPU, 0x980),
968 INTC_VECT(TPU, 0x9A0),
969 INTC_VECT(CEU1, 0x9E0),
970 INTC_VECT(BEU1, 0xA00),
971 INTC_VECT(USB0, 0xA20),
972 INTC_VECT(USB1, 0xA40),
973 INTC_VECT(ATAPI, 0xA60),
975 INTC_VECT(RTC_ATI, 0xA80),
976 INTC_VECT(RTC_PRI, 0xAA0),
977 INTC_VECT(RTC_CUI, 0xAC0),
979 INTC_VECT(DMAC1B_DEI4, 0xB00),
980 INTC_VECT(DMAC1B_DEI5, 0xB20),
981 INTC_VECT(DMAC1B_DADERR, 0xB40),
983 INTC_VECT(DMAC0B_DEI4, 0xB80),
984 INTC_VECT(DMAC0B_DEI5, 0xBA0),
985 INTC_VECT(DMAC0B_DADERR, 0xBC0),
987 INTC_VECT(KEYSC, 0xBE0),
988 INTC_VECT(SCIF_SCIF0, 0xC00),
989 INTC_VECT(SCIF_SCIF1, 0xC20),
990 INTC_VECT(SCIF_SCIF2, 0xC40),
991 INTC_VECT(VEU0, 0xC60),
992 INTC_VECT(MSIOF_MSIOFI0, 0xC80),
993 INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
994 INTC_VECT(SPU_SPUI0, 0xCC0),
995 INTC_VECT(SPU_SPUI1, 0xCE0),
996 INTC_VECT(SCIFA4, 0xD00),
998 INTC_VECT(ICB, 0xD20),
999 INTC_VECT(ETHI, 0xD60),
1001 INTC_VECT(I2C1_ALI, 0xD80),
1002 INTC_VECT(I2C1_TACKI, 0xDA0),
1003 INTC_VECT(I2C1_WAITI, 0xDC0),
1004 INTC_VECT(I2C1_DTEI, 0xDE0),
1006 INTC_VECT(I2C0_ALI, 0xE00),
1007 INTC_VECT(I2C0_TACKI, 0xE20),
1008 INTC_VECT(I2C0_WAITI, 0xE40),
1009 INTC_VECT(I2C0_DTEI, 0xE60),
1011 INTC_VECT(SDHI0, 0xE80),
1012 INTC_VECT(SDHI0, 0xEA0),
1013 INTC_VECT(SDHI0, 0xEC0),
1014 INTC_VECT(SDHI0, 0xEE0),
1016 INTC_VECT(CMT, 0xF00),
1017 INTC_VECT(TSIF, 0xF20),
1018 INTC_VECT(FSI, 0xF80),
1019 INTC_VECT(SCIFA5, 0xFA0),
1021 INTC_VECT(TMU0_TUNI0, 0x400),
1022 INTC_VECT(TMU0_TUNI1, 0x420),
1023 INTC_VECT(TMU0_TUNI2, 0x440),
1025 INTC_VECT(IRDA, 0x480),
1027 INTC_VECT(SDHI1, 0x4E0),
1028 INTC_VECT(SDHI1, 0x500),
1029 INTC_VECT(SDHI1, 0x520),
1031 INTC_VECT(JPU, 0x560),
1032 INTC_VECT(_2DDMAC, 0x4A0),
1034 INTC_VECT(MMC_MMC2I, 0x5A0),
1035 INTC_VECT(MMC_MMC3I, 0x5C0),
1037 INTC_VECT(LCDC, 0xF40),
1039 INTC_VECT(TMU1_TUNI0, 0x920),
1040 INTC_VECT(TMU1_TUNI1, 0x940),
1041 INTC_VECT(TMU1_TUNI2, 0x960),
1044 static struct intc_group groups[] __initdata = {
1045 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
1046 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI),
1047 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
1048 INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU),
1049 INTC_GROUP(USB, USB0, USB1),
1050 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
1051 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
1052 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
1053 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
1054 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
1055 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
1056 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
1059 static struct intc_mask_reg mask_registers[] __initdata = {
1060 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
1061 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
1062 0, DISABLED, ENABLED, ENABLED } },
1063 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
1064 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
1065 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
1066 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
1067 { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } },
1068 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
1069 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
1070 SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } },
1071 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
1072 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
1073 JPU, 0, 0, LCDC } },
1074 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
1075 { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
1076 VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
1077 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
1078 { 0, 0, ICB, SCIFA4,
1079 CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
1080 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
1081 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
1082 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
1083 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
1084 { DISABLED, DISABLED, ENABLED, ENABLED,
1085 0, 0, SCIFA5, FSI } },
1086 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
1087 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
1088 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
1089 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
1090 0, RTC_CUI, RTC_PRI, RTC_ATI } },
1091 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
1092 { 0, _2DG_CEI, _2DG_INI, _2DG_TRI,
1093 0, TPU, 0, TSIF } },
1094 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
1095 { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } },
1096 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
1097 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1100 static struct intc_prio_reg prio_registers[] __initdata = {
1101 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
1102 TMU0_TUNI2, IRDA } },
1103 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },
1104 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
1105 TMU1_TUNI2, SPU } },
1106 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } },
1107 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } },
1108 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } },
1109 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
1110 SCIF_SCIF2, VEU0 } },
1111 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
1113 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } },
1114 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } },
1115 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } },
1116 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } },
1117 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
1118 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1121 static struct intc_sense_reg sense_registers[] __initdata = {
1122 { 0xa414001c, 16, 2, /* ICR1 */
1123 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1126 static struct intc_mask_reg ack_registers[] __initdata = {
1127 { 0xa4140024, 0, 8, /* INTREQ00 */
1128 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1131 static struct intc_desc intc_desc __initdata = {
1133 .force_enable = ENABLED,
1134 .force_disable = DISABLED,
1135 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
1136 prio_registers, sense_registers, ack_registers),
1139 void __init plat_irq_setup(void)
1141 register_intc_controller(&intc_desc);
1146 unsigned long mmselr;
1147 unsigned long cs0bcr;
1148 unsigned long cs4bcr;
1149 unsigned long cs5abcr;
1150 unsigned long cs5bbcr;
1151 unsigned long cs6abcr;
1152 unsigned long cs6bbcr;
1153 unsigned long cs4wcr;
1154 unsigned long cs5awcr;
1155 unsigned long cs5bwcr;
1156 unsigned long cs6awcr;
1157 unsigned long cs6bwcr;
1159 unsigned short ipra;
1160 unsigned short iprb;
1161 unsigned short iprc;
1162 unsigned short iprd;
1163 unsigned short ipre;
1164 unsigned short iprf;
1165 unsigned short iprg;
1166 unsigned short iprh;
1167 unsigned short ipri;
1168 unsigned short iprj;
1169 unsigned short iprk;
1170 unsigned short iprl;
1181 unsigned char imr10;
1182 unsigned char imr11;
1183 unsigned char imr12;
1185 unsigned short rwtcnt;
1186 unsigned short rwtcsr;
1188 unsigned long irdaclk;
1189 unsigned long spuclk;
1190 } sh7724_rstandby_state;
1192 static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb,
1193 unsigned long flags, void *unused)
1195 if (!(flags & SUSP_SH_RSTANDBY))
1199 sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */
1200 sh7724_rstandby_state.mmselr |= 0xa5a50000;
1201 sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */
1202 sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */
1203 sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */
1204 sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */
1205 sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */
1206 sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */
1207 sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */
1208 sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */
1209 sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */
1210 sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */
1211 sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */
1214 sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */
1215 sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */
1216 sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */
1217 sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */
1218 sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */
1219 sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */
1220 sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */
1221 sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */
1222 sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */
1223 sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */
1224 sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */
1225 sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */
1226 sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */
1227 sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */
1228 sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */
1229 sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */
1230 sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */
1231 sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */
1232 sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */
1233 sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */
1234 sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */
1235 sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */
1236 sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */
1237 sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */
1238 sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */
1241 sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */
1242 sh7724_rstandby_state.rwtcnt |= 0x5a00;
1243 sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */
1244 sh7724_rstandby_state.rwtcsr |= 0xa500;
1245 __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004);
1248 sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */
1249 sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */
1254 static int sh7724_post_sleep_notifier_call(struct notifier_block *nb,
1255 unsigned long flags, void *unused)
1257 if (!(flags & SUSP_SH_RSTANDBY))
1261 __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */
1262 __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */
1263 __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */
1264 __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */
1265 __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */
1266 __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */
1267 __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */
1268 __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */
1269 __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */
1270 __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */
1271 __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */
1272 __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */
1275 __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */
1276 __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */
1277 __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */
1278 __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */
1279 __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */
1280 __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */
1281 __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */
1282 __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */
1283 __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */
1284 __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */
1285 __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */
1286 __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */
1287 __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */
1288 __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */
1289 __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */
1290 __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */
1291 __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */
1292 __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */
1293 __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */
1294 __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */
1295 __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */
1296 __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */
1297 __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */
1298 __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */
1299 __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */
1302 __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */
1303 __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */
1306 __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */
1307 __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */
1312 static struct notifier_block sh7724_pre_sleep_notifier = {
1313 .notifier_call = sh7724_pre_sleep_notifier_call,
1314 .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU),
1317 static struct notifier_block sh7724_post_sleep_notifier = {
1318 .notifier_call = sh7724_post_sleep_notifier_call,
1319 .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU),
1322 static int __init sh7724_sleep_setup(void)
1324 atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list,
1325 &sh7724_pre_sleep_notifier);
1327 atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list,
1328 &sh7724_post_sleep_notifier);
1331 arch_initcall(sh7724_sleep_setup);