arch/sh/kernel/cpu/sh4a/setup-sh7724.c

   1 /*
   2  * SH7724 Setup
   3  *
   4  * Copyright (C) 2009 Renesas Solutions Corp.
   5  *
   6  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
   7  *
   8  * Based on SH7723 Setup
   9  * Copyright (C) 2008  Paul Mundt
  10  *
  11  * This file is subject to the terms and conditions of the GNU General Public
  12  * License.  See the file "COPYING" in the main directory of this archive
  13  * for more details.
  14  */
  15 #include <linux/platform_device.h>
  16 #include <linux/init.h>
  17 #include <linux/serial.h>
  18 #include <linux/mm.h>
  19 #include <linux/serial_sci.h>
  20 #include <linux/uio_driver.h>
  21 #include <linux/sh_cmt.h>
  22 #include <linux/io.h>
  23 #include <asm/clock.h>
  24 #include <asm/mmzone.h>
  25
  26 /* Serial */
  27 static struct plat_sci_port sci_platform_data[] = {
  28         {
  29                 .mapbase        = 0xffe00000,
  30                 .flags          = UPF_BOOT_AUTOCONF,
  31                 .type           = PORT_SCIF,
  32                 .irqs           = { 80, 80, 80, 80 },
  33         }, {
  34                 .mapbase        = 0xffe10000,
  35                 .flags          = UPF_BOOT_AUTOCONF,
  36                 .type           = PORT_SCIF,
  37                 .irqs           = { 81, 81, 81, 81 },
  38         }, {
  39                 .mapbase        = 0xffe20000,
  40                 .flags          = UPF_BOOT_AUTOCONF,
  41                 .type           = PORT_SCIF,
  42                 .irqs           = { 82, 82, 82, 82 },
  43         }, {
  44                 .mapbase        = 0xa4e30000,
  45                 .flags          = UPF_BOOT_AUTOCONF,
  46                 .type           = PORT_SCIFA,
  47                 .irqs           = { 56, 56, 56, 56 },
  48         }, {
  49                 .mapbase        = 0xa4e40000,
  50                 .flags          = UPF_BOOT_AUTOCONF,
  51                 .type           = PORT_SCIFA,
  52                 .irqs           = { 88, 88, 88, 88 },
  53         }, {
  54                 .mapbase        = 0xa4e50000,
  55                 .flags          = UPF_BOOT_AUTOCONF,
  56                 .type           = PORT_SCIFA,
  57                 .irqs           = { 109, 109, 109, 109 },
  58         }, {
  59                 .flags = 0,
  60         }
  61 };
  62
  63 static struct platform_device sci_device = {
  64         .name           = "sh-sci",
  65         .id             = -1,
  66         .dev            = {
  67                 .platform_data  = sci_platform_data,
  68         },
  69 };
  70
  71 /* RTC */
  72 static struct resource rtc_resources[] = {
  73         [0] = {
  74                 .start  = 0xa465fec0,
  75                 .end    = 0xa465fec0 + 0x58 - 1,
  76                 .flags  = IORESOURCE_IO,
  77         },
  78         [1] = {
  79                 /* Period IRQ */
  80                 .start  = 69,
  81                 .flags  = IORESOURCE_IRQ,
  82         },
  83         [2] = {
  84                 /* Carry IRQ */
  85                 .start  = 70,
  86                 .flags  = IORESOURCE_IRQ,
  87         },
  88         [3] = {
  89                 /* Alarm IRQ */
  90                 .start  = 68,
  91                 .flags  = IORESOURCE_IRQ,
  92         },
  93 };
  94
  95 static struct platform_device rtc_device = {
  96         .name           = "sh-rtc",
  97         .id             = -1,
  98         .num_resources  = ARRAY_SIZE(rtc_resources),
  99         .resource       = rtc_resources,
 100 };
 101
 102 /* I2C0 */
 103 static struct resource iic0_resources[] = {
 104         [0] = {
 105                 .name   = "IIC0",
 106                 .start  = 0x04470000,
 107                 .end    = 0x04470018 - 1,
 108                 .flags  = IORESOURCE_MEM,
 109         },
 110         [1] = {
 111                 .start  = 96,
 112                 .end    = 99,
 113                 .flags  = IORESOURCE_IRQ,
 114         },
 115 };
 116
 117 static struct platform_device iic0_device = {
 118         .name           = "i2c-sh_mobile",
 119         .id             = 0, /* "i2c0" clock */
 120         .num_resources  = ARRAY_SIZE(iic0_resources),
 121         .resource       = iic0_resources,
 122 };
 123
 124 /* I2C1 */
 125 static struct resource iic1_resources[] = {
 126         [0] = {
 127                 .name   = "IIC1",
 128                 .start  = 0x04750000,
 129                 .end    = 0x04750018 - 1,
 130                 .flags  = IORESOURCE_MEM,
 131         },
 132         [1] = {
 133                 .start  = 92,
 134                 .end    = 95,
 135                 .flags  = IORESOURCE_IRQ,
 136         },
 137 };
 138
 139 static struct platform_device iic1_device = {
 140         .name           = "i2c-sh_mobile",
 141         .id             = 1, /* "i2c1" clock */
 142         .num_resources  = ARRAY_SIZE(iic1_resources),
 143         .resource       = iic1_resources,
 144 };
 145
 146 /* VPU */
 147 static struct uio_info vpu_platform_data = {
 148         .name = "VPU5F",
 149         .version = "0",
 150         .irq = 60,
 151 };
 152
 153 static struct resource vpu_resources[] = {
 154         [0] = {
 155                 .name   = "VPU",
 156                 .start  = 0xfe900000,
 157                 .end    = 0xfe902807,
 158                 .flags  = IORESOURCE_MEM,
 159         },
 160         [1] = {
 161                 /* place holder for contiguous memory */
 162         },
 163 };
 164
 165 static struct platform_device vpu_device = {
 166         .name           = "uio_pdrv_genirq",
 167         .id             = 0,
 168         .dev = {
 169                 .platform_data  = &vpu_platform_data,
 170         },
 171         .resource       = vpu_resources,
 172         .num_resources  = ARRAY_SIZE(vpu_resources),
 173 };
 174
 175 /* VEU0 */
 176 static struct uio_info veu0_platform_data = {
 177         .name = "VEU3F0",
 178         .version = "0",
 179         .irq = 83,
 180 };
 181
 182 static struct resource veu0_resources[] = {
 183         [0] = {
 184                 .name   = "VEU3F0",
 185                 .start  = 0xfe920000,
 186                 .end    = 0xfe9200cb - 1,
 187                 .flags  = IORESOURCE_MEM,
 188         },
 189         [1] = {
 190                 /* place holder for contiguous memory */
 191         },
 192 };
 193
 194 static struct platform_device veu0_device = {
 195         .name           = "uio_pdrv_genirq",
 196         .id             = 1,
 197         .dev = {
 198                 .platform_data  = &veu0_platform_data,
 199         },
 200         .resource       = veu0_resources,
 201         .num_resources  = ARRAY_SIZE(veu0_resources),
 202 };
 203
 204 /* VEU1 */
 205 static struct uio_info veu1_platform_data = {
 206         .name = "VEU3F1",
 207         .version = "0",
 208         .irq = 54,
 209 };
 210
 211 static struct resource veu1_resources[] = {
 212         [0] = {
 213                 .name   = "VEU3F1",
 214                 .start  = 0xfe924000,
 215                 .end    = 0xfe9240cb - 1,
 216                 .flags  = IORESOURCE_MEM,
 217         },
 218         [1] = {
 219                 /* place holder for contiguous memory */
 220         },
 221 };
 222
 223 static struct platform_device veu1_device = {
 224         .name           = "uio_pdrv_genirq",
 225         .id             = 2,
 226         .dev = {
 227                 .platform_data  = &veu1_platform_data,
 228         },
 229         .resource       = veu1_resources,
 230         .num_resources  = ARRAY_SIZE(veu1_resources),
 231 };
 232
 233 static struct sh_cmt_config cmt_platform_data = {
 234         .name = "CMT",
 235         .channel_offset = 0x60,
 236         .timer_bit = 5,
 237         .clk = "cmt0",
 238         .clockevent_rating = 125,
 239         .clocksource_rating = 200,
 240 };
 241
 242 static struct resource cmt_resources[] = {
 243         [0] = {
 244                 .name   = "CMT",
 245                 .start  = 0x044a0060,
 246                 .end    = 0x044a006b,
 247                 .flags  = IORESOURCE_MEM,
 248         },
 249         [1] = {
 250                 .start  = 104,
 251                 .flags  = IORESOURCE_IRQ,
 252         },
 253 };
 254
 255 static struct platform_device cmt_device = {
 256         .name           = "sh_cmt",
 257         .id             = 0,
 258         .dev = {
 259                 .platform_data  = &cmt_platform_data,
 260         },
 261         .resource       = cmt_resources,
 262         .num_resources  = ARRAY_SIZE(cmt_resources),
 263 };
 264
 265 static struct platform_device *sh7724_devices[] __initdata = {
 266         &cmt_device,
 267         &sci_device,
 268         &rtc_device,
 269         &iic0_device,
 270         &iic1_device,
 271         &vpu_device,
 272         &veu0_device,
 273         &veu1_device,
 274 };
 275
 276 static int __init sh7724_devices_setup(void)
 277 {
 278         clk_always_enable("rtc0");   /* RTC */
 279         clk_always_enable("vpu0");   /* VPU */
 280         clk_always_enable("veu1");   /* VEU3F1 */
 281         clk_always_enable("veu0");   /* VEU3F0 */
 282
 283         platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
 284         platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
 285         platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
 286
 287         return platform_add_devices(sh7724_devices,
 288                                     ARRAY_SIZE(sh7724_devices));
 289 }
 290 device_initcall(sh7724_devices_setup);
 291
 292 enum {
 293         UNUSED = 0,
 294
 295         /* interrupt sources */
 296         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 297         HUDI,
 298         DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
 299         _2DG_TRI, _2DG_INI, _2DG_CEI, _2DG_BRK,
 300         DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
 301         VIO_CEU20I, VIO_BEU20I, VIO_VEU3F1, VIO_VOUI,
 302         SCIFA_SCIFA0,
 303         VPU_VPUI,
 304         TPU_TPUI,
 305         CEU21I,
 306         BEU21I,
 307         USB_USI0,
 308         ATAPI,
 309         RTC_ATI, RTC_PRI, RTC_CUI,
 310         DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
 311         DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
 312         KEYSC_KEYI,
 313         SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
 314         VEU3F0I,
 315         MSIOF_MSIOFI0, MSIOF_MSIOFI1,
 316         SPU_SPUI0, SPU_SPUI1,
 317         SCIFA_SCIFA1,
 318 /*      ICB_ICBI, */
 319         ETHI,
 320         I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
 321         I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
 322         SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2,
 323         CMT_CMTI,
 324         TSIF_TSIFI,
 325 /*      ICB_LMBI, */
 326         FSI_FSI,
 327         SCIFA_SCIFA2,
 328         TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
 329         IRDA_IRDAI,
 330         SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2,
 331         JPU_JPUI,
 332         MMC_MMCI0, MMC_MMCI1, MMC_MMCI2,
 333         LCDC_LCDCI,
 334         TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
 335
 336         /* interrupt groups */
 337         DMAC1A, _2DG, DMAC0A, VIO, RTC,
 338         DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMC,
 339 };
 340
 341 static struct intc_vect vectors[] __initdata = {
 342         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 343         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 344         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 345         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 346
 347         INTC_VECT(DMAC1A_DEI0, 0x700),
 348         INTC_VECT(DMAC1A_DEI1, 0x720),
 349         INTC_VECT(DMAC1A_DEI2, 0x740),
 350         INTC_VECT(DMAC1A_DEI3, 0x760),
 351
 352         INTC_VECT(_2DG_TRI, 0x780),
 353         INTC_VECT(_2DG_INI, 0x7A0),
 354         INTC_VECT(_2DG_CEI, 0x7C0),
 355         INTC_VECT(_2DG_BRK, 0x7E0),
 356
 357         INTC_VECT(DMAC0A_DEI0, 0x800),
 358         INTC_VECT(DMAC0A_DEI1, 0x820),
 359         INTC_VECT(DMAC0A_DEI2, 0x840),
 360         INTC_VECT(DMAC0A_DEI3, 0x860),
 361
 362         INTC_VECT(VIO_CEU20I, 0x880),
 363         INTC_VECT(VIO_BEU20I, 0x8A0),
 364         INTC_VECT(VIO_VEU3F1, 0x8C0),
 365         INTC_VECT(VIO_VOUI, 0x8E0),
 366
 367         INTC_VECT(SCIFA_SCIFA0, 0x900),
 368         INTC_VECT(VPU_VPUI, 0x980),
 369         INTC_VECT(TPU_TPUI, 0x9A0),
 370         INTC_VECT(CEU21I, 0x9E0),
 371         INTC_VECT(BEU21I, 0xA00),
 372         INTC_VECT(USB_USI0, 0xA20),
 373         INTC_VECT(ATAPI, 0xA60),
 374
 375         INTC_VECT(RTC_ATI, 0xA80),
 376         INTC_VECT(RTC_PRI, 0xAA0),
 377         INTC_VECT(RTC_CUI, 0xAC0),
 378
 379         INTC_VECT(DMAC1B_DEI4, 0xB00),
 380         INTC_VECT(DMAC1B_DEI5, 0xB20),
 381         INTC_VECT(DMAC1B_DADERR, 0xB40),
 382
 383         INTC_VECT(DMAC0B_DEI4, 0xB80),
 384         INTC_VECT(DMAC0B_DEI5, 0xBA0),
 385         INTC_VECT(DMAC0B_DADERR, 0xBC0),
 386
 387         INTC_VECT(KEYSC_KEYI, 0xBE0),
 388         INTC_VECT(SCIF_SCIF0, 0xC00),
 389         INTC_VECT(SCIF_SCIF1, 0xC20),
 390         INTC_VECT(SCIF_SCIF2, 0xC40),
 391         INTC_VECT(VEU3F0I, 0xC60),
 392         INTC_VECT(MSIOF_MSIOFI0, 0xC80),
 393         INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
 394         INTC_VECT(SPU_SPUI0, 0xCC0),
 395         INTC_VECT(SPU_SPUI1, 0xCE0),
 396         INTC_VECT(SCIFA_SCIFA1, 0xD00),
 397
 398 /*      INTC_VECT(ICB_ICBI, 0xD20), */
 399         INTC_VECT(ETHI, 0xD60),
 400
 401         INTC_VECT(I2C1_ALI, 0xD80),
 402         INTC_VECT(I2C1_TACKI, 0xDA0),
 403         INTC_VECT(I2C1_WAITI, 0xDC0),
 404         INTC_VECT(I2C1_DTEI, 0xDE0),
 405
 406         INTC_VECT(I2C0_ALI, 0xE00),
 407         INTC_VECT(I2C0_TACKI, 0xE20),
 408         INTC_VECT(I2C0_WAITI, 0xE40),
 409         INTC_VECT(I2C0_DTEI, 0xE60),
 410
 411         INTC_VECT(SDHI0_SDHII0, 0xE80),
 412         INTC_VECT(SDHI0_SDHII1, 0xEA0),
 413         INTC_VECT(SDHI0_SDHII2, 0xEC0),
 414
 415         INTC_VECT(CMT_CMTI, 0xF00),
 416         INTC_VECT(TSIF_TSIFI, 0xF20),
 417 /*      INTC_VECT(ICB_LMBI, 0xF60), */
 418         INTC_VECT(FSI_FSI, 0xF80),
 419         INTC_VECT(SCIFA_SCIFA2, 0xFA0),
 420
 421         INTC_VECT(TMU0_TUNI0, 0x400),
 422         INTC_VECT(TMU0_TUNI1, 0x420),
 423         INTC_VECT(TMU0_TUNI2, 0x440),
 424
 425         INTC_VECT(IRDA_IRDAI, 0x480),
 426
 427         INTC_VECT(SDHI1_SDHII0, 0x4E0),
 428         INTC_VECT(SDHI1_SDHII1, 0x500),
 429         INTC_VECT(SDHI1_SDHII2, 0x520),
 430
 431         INTC_VECT(JPU_JPUI, 0x560),
 432
 433         INTC_VECT(MMC_MMCI0, 0x580),
 434         INTC_VECT(MMC_MMCI1, 0x5A0),
 435         INTC_VECT(MMC_MMCI2, 0x5C0),
 436
 437         INTC_VECT(LCDC_LCDCI, 0xF40),
 438
 439         INTC_VECT(TMU1_TUNI0, 0x920),
 440         INTC_VECT(TMU1_TUNI1, 0x940),
 441         INTC_VECT(TMU1_TUNI2, 0x960),
 442 };
 443
 444 static struct intc_group groups[] __initdata = {
 445         INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
 446         INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI, _2DG_BRK),
 447         INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
 448         INTC_GROUP(VIO, VIO_CEU20I, VIO_BEU20I, VIO_VEU3F1, VIO_VOUI),
 449         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
 450         INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
 451         INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
 452         INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
 453         INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
 454         INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2),
 455         INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2),
 456         INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
 457         INTC_GROUP(MMC, MMC_MMCI0, MMC_MMCI1, MMC_MMCI2),
 458 };
 459
 460 /* FIXMEEEEEEEEEEEEEEEEEEE !!!!! */
 461 /* very bad manual !! */
 462 static struct intc_mask_reg mask_registers[] __initdata = {
 463         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
 464           { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
 465             /*SDHII3?*/0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } },
 466         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 467           { VIO_VOUI, VIO_VEU3F1, VIO_BEU20I, VIO_CEU20I,
 468             DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
 469         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 470           { 0, 0, 0, VPU_VPUI, ATAPI, ETHI, 0, /*SCIFA3*/SCIFA_SCIFA0 } },
 471         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 472           { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
 473             SPU_SPUI1, SPU_SPUI0, BEU21I, IRDA_IRDAI } },
 474         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 475           { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
 476             JPU_JPUI, 0, 0, LCDC_LCDCI } },
 477         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 478           { KEYSC_KEYI, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
 479             VEU3F0I, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
 480         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 481           { 0, 0, /*ICB_ICBI*/0, /*SCIFA4*/SCIFA_SCIFA1,
 482             CEU21I, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
 483         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 484           { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
 485             I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
 486         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 487           { /*SDHII3*/0, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0,
 488             0, 0, /*SCIFA5*/SCIFA_SCIFA2, FSI_FSI } },
 489         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 490           { 0, 0, 0, CMT_CMTI, 0, /*USB1*/0, USB_USI0, 0 } },
 491         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 492           { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
 493             0, RTC_ATI, RTC_PRI, RTC_CUI } },
 494         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 495           { _2DG_BRK, _2DG_CEI, _2DG_INI, _2DG_TRI,
 496             0, TPU_TPUI, /*ICB_LMBI*/0, TSIF_TSIFI } },
 497         { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
 498           { 0, 0, 0, 0, 0, 0, 0, 0/*2DDMAC*/ } },
 499         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 500           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 501 };
 502
 503 static struct intc_prio_reg prio_registers[] __initdata = {
 504         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
 505                                              TMU0_TUNI2, IRDA_IRDAI } },
 506         { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU_JPUI, LCDC_LCDCI,
 507                                              DMAC1A, BEU21I } },
 508         { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
 509                                              TMU1_TUNI2, SPU } },
 510         { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMC, 0, ATAPI } },
 511         { 0xa4080010, 0, 16, 4, /* IPRE */
 512           { DMAC0A, /*BEU?VEU?*/VIO, /*SCIFA3*/SCIFA_SCIFA0, /*VPU5F*/
 513             VPU_VPUI } },
 514         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B,
 515                                              USB_USI0, CMT_CMTI } },
 516         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
 517                                              SCIF_SCIF2, VEU3F0I } },
 518         { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
 519                                              I2C1, I2C0 } },
 520         { 0xa4080020, 0, 16, 4, /* IPRI */ { /*SCIFA4*/SCIFA_SCIFA1, /*ICB*/0,
 521                                              TSIF_TSIFI, _2DG/*ICB?*/ } },
 522         { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU21I, ETHI, FSI_FSI, SDHI1 } },
 523         { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, /*ICB?*/0, SDHI0 } },
 524         { 0xa408002c, 0, 16, 4, /* IPRL */ { /*SCIFA5*/SCIFA_SCIFA2, 0,
 525                                              TPU_TPUI, /*2DDMAC*/0 } },
 526         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 527           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 528 };
 529
 530 static struct intc_sense_reg sense_registers[] __initdata = {
 531         { 0xa414001c, 16, 2, /* ICR1 */
 532           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 533 };
 534
 535 static struct intc_mask_reg ack_registers[] __initdata = {
 536         { 0xa4140024, 0, 8, /* INTREQ00 */
 537           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 538 };
 539
 540 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups,
 541                              mask_registers, prio_registers, sense_registers,
 542                              ack_registers);
 543
 544 void __init plat_irq_setup(void)
 545 {
 546         register_intc_controller(&intc_desc);
 547 }