4 * Copyright (C) 2008 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
14 #include <linux/serial_sci.h>
15 #include <linux/uio_driver.h>
16 #include <linux/usb/r8a66597.h>
17 #include <linux/sh_timer.h>
19 #include <asm/clock.h>
20 #include <asm/mmzone.h>
22 static struct uio_info vpu_platform_data = {
28 static struct resource vpu_resources[] = {
33 .flags = IORESOURCE_MEM,
36 /* place holder for contiguous memory */
40 static struct platform_device vpu_device = {
41 .name = "uio_pdrv_genirq",
44 .platform_data = &vpu_platform_data,
46 .resource = vpu_resources,
47 .num_resources = ARRAY_SIZE(vpu_resources),
50 static struct uio_info veu0_platform_data = {
56 static struct resource veu0_resources[] = {
61 .flags = IORESOURCE_MEM,
64 /* place holder for contiguous memory */
68 static struct platform_device veu0_device = {
69 .name = "uio_pdrv_genirq",
72 .platform_data = &veu0_platform_data,
74 .resource = veu0_resources,
75 .num_resources = ARRAY_SIZE(veu0_resources),
78 static struct uio_info veu1_platform_data = {
84 static struct resource veu1_resources[] = {
89 .flags = IORESOURCE_MEM,
92 /* place holder for contiguous memory */
96 static struct platform_device veu1_device = {
97 .name = "uio_pdrv_genirq",
100 .platform_data = &veu1_platform_data,
102 .resource = veu1_resources,
103 .num_resources = ARRAY_SIZE(veu1_resources),
106 static struct sh_timer_config cmt_platform_data = {
108 .channel_offset = 0x60,
111 .clockevent_rating = 125,
112 .clocksource_rating = 125,
115 static struct resource cmt_resources[] = {
120 .flags = IORESOURCE_MEM,
124 .flags = IORESOURCE_IRQ,
128 static struct platform_device cmt_device = {
132 .platform_data = &cmt_platform_data,
134 .resource = cmt_resources,
135 .num_resources = ARRAY_SIZE(cmt_resources),
138 static struct sh_timer_config tmu0_platform_data = {
140 .channel_offset = 0x04,
143 .clockevent_rating = 200,
146 static struct resource tmu0_resources[] = {
151 .flags = IORESOURCE_MEM,
155 .flags = IORESOURCE_IRQ,
159 static struct platform_device tmu0_device = {
163 .platform_data = &tmu0_platform_data,
165 .resource = tmu0_resources,
166 .num_resources = ARRAY_SIZE(tmu0_resources),
169 static struct sh_timer_config tmu1_platform_data = {
171 .channel_offset = 0x10,
174 .clocksource_rating = 200,
177 static struct resource tmu1_resources[] = {
182 .flags = IORESOURCE_MEM,
186 .flags = IORESOURCE_IRQ,
190 static struct platform_device tmu1_device = {
194 .platform_data = &tmu1_platform_data,
196 .resource = tmu1_resources,
197 .num_resources = ARRAY_SIZE(tmu1_resources),
200 static struct sh_timer_config tmu2_platform_data = {
202 .channel_offset = 0x1c,
207 static struct resource tmu2_resources[] = {
212 .flags = IORESOURCE_MEM,
216 .flags = IORESOURCE_IRQ,
220 static struct platform_device tmu2_device = {
224 .platform_data = &tmu2_platform_data,
226 .resource = tmu2_resources,
227 .num_resources = ARRAY_SIZE(tmu2_resources),
230 static struct sh_timer_config tmu3_platform_data = {
232 .channel_offset = 0x04,
237 static struct resource tmu3_resources[] = {
242 .flags = IORESOURCE_MEM,
246 .flags = IORESOURCE_IRQ,
250 static struct platform_device tmu3_device = {
254 .platform_data = &tmu3_platform_data,
256 .resource = tmu3_resources,
257 .num_resources = ARRAY_SIZE(tmu3_resources),
260 static struct sh_timer_config tmu4_platform_data = {
262 .channel_offset = 0x10,
267 static struct resource tmu4_resources[] = {
272 .flags = IORESOURCE_MEM,
276 .flags = IORESOURCE_IRQ,
280 static struct platform_device tmu4_device = {
284 .platform_data = &tmu4_platform_data,
286 .resource = tmu4_resources,
287 .num_resources = ARRAY_SIZE(tmu4_resources),
290 static struct sh_timer_config tmu5_platform_data = {
292 .channel_offset = 0x1c,
297 static struct resource tmu5_resources[] = {
302 .flags = IORESOURCE_MEM,
306 .flags = IORESOURCE_IRQ,
310 static struct platform_device tmu5_device = {
314 .platform_data = &tmu5_platform_data,
316 .resource = tmu5_resources,
317 .num_resources = ARRAY_SIZE(tmu5_resources),
320 static struct plat_sci_port sci_platform_data[] = {
322 .mapbase = 0xffe00000,
323 .flags = UPF_BOOT_AUTOCONF,
324 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
325 .scbrr_algo_id = SCBRR_ALGO_2,
327 .irqs = { 80, 80, 80, 80 },
330 .mapbase = 0xffe10000,
331 .flags = UPF_BOOT_AUTOCONF,
332 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
333 .scbrr_algo_id = SCBRR_ALGO_2,
335 .irqs = { 81, 81, 81, 81 },
338 .mapbase = 0xffe20000,
339 .flags = UPF_BOOT_AUTOCONF,
340 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
341 .scbrr_algo_id = SCBRR_ALGO_2,
343 .irqs = { 82, 82, 82, 82 },
346 .mapbase = 0xa4e30000,
347 .flags = UPF_BOOT_AUTOCONF,
348 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
349 .scbrr_algo_id = SCBRR_ALGO_3,
351 .irqs = { 56, 56, 56, 56 },
354 .mapbase = 0xa4e40000,
355 .flags = UPF_BOOT_AUTOCONF,
356 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
357 .scbrr_algo_id = SCBRR_ALGO_3,
359 .irqs = { 88, 88, 88, 88 },
362 .mapbase = 0xa4e50000,
363 .flags = UPF_BOOT_AUTOCONF,
364 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
365 .scbrr_algo_id = SCBRR_ALGO_3,
367 .irqs = { 109, 109, 109, 109 },
374 static struct platform_device sci_device = {
378 .platform_data = sci_platform_data,
382 static struct resource rtc_resources[] = {
385 .end = 0xa465fec0 + 0x58 - 1,
386 .flags = IORESOURCE_IO,
391 .flags = IORESOURCE_IRQ,
396 .flags = IORESOURCE_IRQ,
401 .flags = IORESOURCE_IRQ,
405 static struct platform_device rtc_device = {
408 .num_resources = ARRAY_SIZE(rtc_resources),
409 .resource = rtc_resources,
412 static struct r8a66597_platdata r8a66597_data = {
413 /* This set zero to all members */
416 static struct resource sh7723_usb_host_resources[] = {
420 .flags = IORESOURCE_MEM,
425 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
429 static struct platform_device sh7723_usb_host_device = {
430 .name = "r8a66597_hcd",
433 .dma_mask = NULL, /* not use dma */
434 .coherent_dma_mask = 0xffffffff,
435 .platform_data = &r8a66597_data,
437 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources),
438 .resource = sh7723_usb_host_resources,
441 static struct resource iic_resources[] = {
446 .flags = IORESOURCE_MEM,
451 .flags = IORESOURCE_IRQ,
455 static struct platform_device iic_device = {
456 .name = "i2c-sh_mobile",
457 .id = 0, /* "i2c0" clock */
458 .num_resources = ARRAY_SIZE(iic_resources),
459 .resource = iic_resources,
462 static struct platform_device *sh7723_devices[] __initdata = {
473 &sh7723_usb_host_device,
479 static int __init sh7723_devices_setup(void)
481 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
482 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
483 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
485 return platform_add_devices(sh7723_devices,
486 ARRAY_SIZE(sh7723_devices));
488 __initcall(sh7723_devices_setup);
490 static struct platform_device *sh7723_early_devices[] __initdata = {
500 void __init plat_early_device_setup(void)
502 early_platform_add_devices(sh7723_early_devices,
503 ARRAY_SIZE(sh7723_early_devices));
506 #define RAMCR_CACHE_L2FC 0x0002
507 #define RAMCR_CACHE_L2E 0x0001
508 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
509 void __uses_jump_to_uncached l2_cache_init(void)
511 /* Enable L2 cache */
512 ctrl_outl(L2_CACHE_ENABLE, RAMCR);
518 /* interrupt sources */
519 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
521 DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
522 _2DG_TRI,_2DG_INI,_2DG_CEI,
523 DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
524 VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
530 RTC_ATI,RTC_PRI,RTC_CUI,
531 DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
532 DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
534 SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
535 MSIOF_MSIOFI0,MSIOF_MSIOFI1,
537 FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
538 I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
539 SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
544 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
547 SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
550 TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
552 /* interrupt groups */
553 DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
554 SDHI1, RTC, DMAC1B, SDHI0,
557 static struct intc_vect vectors[] __initdata = {
558 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
559 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
560 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
561 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
563 INTC_VECT(DMAC1A_DEI0,0x700),
564 INTC_VECT(DMAC1A_DEI1,0x720),
565 INTC_VECT(DMAC1A_DEI2,0x740),
566 INTC_VECT(DMAC1A_DEI3,0x760),
568 INTC_VECT(_2DG_TRI, 0x780),
569 INTC_VECT(_2DG_INI, 0x7A0),
570 INTC_VECT(_2DG_CEI, 0x7C0),
572 INTC_VECT(DMAC0A_DEI0,0x800),
573 INTC_VECT(DMAC0A_DEI1,0x820),
574 INTC_VECT(DMAC0A_DEI2,0x840),
575 INTC_VECT(DMAC0A_DEI3,0x860),
577 INTC_VECT(VIO_CEUI,0x880),
578 INTC_VECT(VIO_BEUI,0x8A0),
579 INTC_VECT(VIO_VEU2HI,0x8C0),
580 INTC_VECT(VIO_VOUI,0x8E0),
582 INTC_VECT(SCIFA_SCIFA0,0x900),
583 INTC_VECT(VPU_VPUI,0x980),
584 INTC_VECT(TPU_TPUI,0x9A0),
585 INTC_VECT(ADC_ADI,0x9E0),
586 INTC_VECT(USB_USI0,0xA20),
588 INTC_VECT(RTC_ATI,0xA80),
589 INTC_VECT(RTC_PRI,0xAA0),
590 INTC_VECT(RTC_CUI,0xAC0),
592 INTC_VECT(DMAC1B_DEI4,0xB00),
593 INTC_VECT(DMAC1B_DEI5,0xB20),
594 INTC_VECT(DMAC1B_DADERR,0xB40),
596 INTC_VECT(DMAC0B_DEI4,0xB80),
597 INTC_VECT(DMAC0B_DEI5,0xBA0),
598 INTC_VECT(DMAC0B_DADERR,0xBC0),
600 INTC_VECT(KEYSC_KEYI,0xBE0),
601 INTC_VECT(SCIF_SCIF0,0xC00),
602 INTC_VECT(SCIF_SCIF1,0xC20),
603 INTC_VECT(SCIF_SCIF2,0xC40),
604 INTC_VECT(MSIOF_MSIOFI0,0xC80),
605 INTC_VECT(MSIOF_MSIOFI1,0xCA0),
606 INTC_VECT(SCIFA_SCIFA1,0xD00),
608 INTC_VECT(FLCTL_FLSTEI,0xD80),
609 INTC_VECT(FLCTL_FLTENDI,0xDA0),
610 INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
611 INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
613 INTC_VECT(I2C_ALI,0xE00),
614 INTC_VECT(I2C_TACKI,0xE20),
615 INTC_VECT(I2C_WAITI,0xE40),
616 INTC_VECT(I2C_DTEI,0xE60),
618 INTC_VECT(SDHI0_SDHII0,0xE80),
619 INTC_VECT(SDHI0_SDHII1,0xEA0),
620 INTC_VECT(SDHI0_SDHII2,0xEC0),
622 INTC_VECT(CMT_CMTI,0xF00),
623 INTC_VECT(TSIF_TSIFI,0xF20),
624 INTC_VECT(SIU_SIUI,0xF80),
625 INTC_VECT(SCIFA_SCIFA2,0xFA0),
627 INTC_VECT(TMU0_TUNI0,0x400),
628 INTC_VECT(TMU0_TUNI1,0x420),
629 INTC_VECT(TMU0_TUNI2,0x440),
631 INTC_VECT(IRDA_IRDAI,0x480),
632 INTC_VECT(ATAPI_ATAPII,0x4A0),
634 INTC_VECT(SDHI1_SDHII0,0x4E0),
635 INTC_VECT(SDHI1_SDHII1,0x500),
636 INTC_VECT(SDHI1_SDHII2,0x520),
638 INTC_VECT(VEU2H1_VEU2HI,0x560),
639 INTC_VECT(LCDC_LCDCI,0x580),
641 INTC_VECT(TMU1_TUNI0,0x920),
642 INTC_VECT(TMU1_TUNI1,0x940),
643 INTC_VECT(TMU1_TUNI2,0x960),
647 static struct intc_group groups[] __initdata = {
648 INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
649 INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
650 INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
651 INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
652 INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
653 INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
654 INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
655 INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
656 INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
657 INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
658 INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
661 static struct intc_mask_reg mask_registers[] __initdata = {
662 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
663 { 0, TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} },
664 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
665 { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
666 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
667 { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
668 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
669 { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
670 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
671 { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
672 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
673 { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
674 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
675 { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
676 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
677 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
678 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
679 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
680 { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } },
681 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
682 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
683 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
684 { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
685 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
686 { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
687 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
688 { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
689 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
690 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
693 static struct intc_prio_reg prio_registers[] __initdata = {
694 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
695 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
696 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
697 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
698 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
699 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
700 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
701 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
702 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
703 { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
704 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
705 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
706 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
707 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
710 static struct intc_sense_reg sense_registers[] __initdata = {
711 { 0xa414001c, 16, 2, /* ICR1 */
712 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
715 static struct intc_mask_reg ack_registers[] __initdata = {
716 { 0xa4140024, 0, 8, /* INTREQ00 */
717 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
720 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7723", vectors, groups,
721 mask_registers, prio_registers, sense_registers,
724 void __init plat_irq_setup(void)
726 register_intc_controller(&intc_desc);