4 * Copyright (C) 2006 - 2008 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/init.h>
12 #include <linux/platform_device.h>
13 #include <linux/serial.h>
14 #include <linux/serial_sci.h>
15 #include <linux/sh_timer.h>
16 #include <linux/uio_driver.h>
17 #include <linux/usb/m66592.h>
19 #include <asm/clock.h>
20 #include <asm/dmaengine.h>
21 #include <asm/mmzone.h>
24 #include <cpu/dma-register.h>
25 #include <cpu/sh7722.h>
27 static struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
29 .slave_id = SHDMA_SLAVE_SCIF0_TX,
31 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
34 .slave_id = SHDMA_SLAVE_SCIF0_RX,
36 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
39 .slave_id = SHDMA_SLAVE_SCIF1_TX,
41 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
44 .slave_id = SHDMA_SLAVE_SCIF1_RX,
46 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
49 .slave_id = SHDMA_SLAVE_SCIF2_TX,
51 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
54 .slave_id = SHDMA_SLAVE_SCIF2_RX,
56 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
59 .slave_id = SHDMA_SLAVE_SIUA_TX,
61 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
64 .slave_id = SHDMA_SLAVE_SIUA_RX,
66 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
69 .slave_id = SHDMA_SLAVE_SIUB_TX,
71 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
74 .slave_id = SHDMA_SLAVE_SIUB_RX,
76 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
81 static struct sh_dmae_channel sh7722_dmae_channels[] = {
109 static unsigned int ts_shift[] = TS_SHIFT;
111 static struct sh_dmae_pdata dma_platform_data = {
112 .slave = sh7722_dmae_slaves,
113 .slave_num = ARRAY_SIZE(sh7722_dmae_slaves),
114 .channel = sh7722_dmae_channels,
115 .channel_num = ARRAY_SIZE(sh7722_dmae_channels),
116 .ts_low_shift = CHCR_TS_LOW_SHIFT,
117 .ts_low_mask = CHCR_TS_LOW_MASK,
118 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
119 .ts_high_mask = CHCR_TS_HIGH_MASK,
120 .ts_shift = ts_shift,
121 .ts_shift_num = ARRAY_SIZE(ts_shift),
122 .dmaor_init = DMAOR_INIT,
125 static struct resource sh7722_dmae_resources[] = {
127 /* Channel registers and DMAOR */
130 .flags = IORESOURCE_MEM,
136 .flags = IORESOURCE_MEM,
142 .flags = IORESOURCE_IRQ,
145 /* IRQ for channels 0-3 */
148 .flags = IORESOURCE_IRQ,
151 /* IRQ for channels 4-5 */
154 .flags = IORESOURCE_IRQ,
158 struct platform_device dma_device = {
159 .name = "sh-dma-engine",
161 .resource = sh7722_dmae_resources,
162 .num_resources = ARRAY_SIZE(sh7722_dmae_resources),
164 .platform_data = &dma_platform_data,
167 .hwblk_id = HWBLK_DMAC,
172 static struct plat_sci_port scif0_platform_data = {
173 .mapbase = 0xffe00000,
174 .flags = UPF_BOOT_AUTOCONF,
176 .irqs = { 80, 80, 80, 80 },
180 static struct platform_device scif0_device = {
184 .platform_data = &scif0_platform_data,
188 static struct plat_sci_port scif1_platform_data = {
189 .mapbase = 0xffe10000,
190 .flags = UPF_BOOT_AUTOCONF,
192 .irqs = { 81, 81, 81, 81 },
196 static struct platform_device scif1_device = {
200 .platform_data = &scif1_platform_data,
204 static struct plat_sci_port scif2_platform_data = {
205 .mapbase = 0xffe20000,
206 .flags = UPF_BOOT_AUTOCONF,
208 .irqs = { 82, 82, 82, 82 },
212 static struct platform_device scif2_device = {
216 .platform_data = &scif2_platform_data,
220 static struct resource rtc_resources[] = {
223 .end = 0xa465fec0 + 0x58 - 1,
224 .flags = IORESOURCE_IO,
229 .flags = IORESOURCE_IRQ,
234 .flags = IORESOURCE_IRQ,
239 .flags = IORESOURCE_IRQ,
243 static struct platform_device rtc_device = {
246 .num_resources = ARRAY_SIZE(rtc_resources),
247 .resource = rtc_resources,
249 .hwblk_id = HWBLK_RTC,
253 static struct m66592_platdata usbf_platdata = {
257 static struct resource usbf_resources[] = {
262 .flags = IORESOURCE_MEM,
267 .flags = IORESOURCE_IRQ,
271 static struct platform_device usbf_device = {
272 .name = "m66592_udc",
273 .id = 0, /* "usbf0" clock */
276 .coherent_dma_mask = 0xffffffff,
277 .platform_data = &usbf_platdata,
279 .num_resources = ARRAY_SIZE(usbf_resources),
280 .resource = usbf_resources,
282 .hwblk_id = HWBLK_USBF,
286 static struct resource iic_resources[] = {
291 .flags = IORESOURCE_MEM,
296 .flags = IORESOURCE_IRQ,
300 static struct platform_device iic_device = {
301 .name = "i2c-sh_mobile",
302 .id = 0, /* "i2c0" clock */
303 .num_resources = ARRAY_SIZE(iic_resources),
304 .resource = iic_resources,
306 .hwblk_id = HWBLK_IIC,
310 static struct uio_info vpu_platform_data = {
316 static struct resource vpu_resources[] = {
321 .flags = IORESOURCE_MEM,
324 /* place holder for contiguous memory */
328 static struct platform_device vpu_device = {
329 .name = "uio_pdrv_genirq",
332 .platform_data = &vpu_platform_data,
334 .resource = vpu_resources,
335 .num_resources = ARRAY_SIZE(vpu_resources),
337 .hwblk_id = HWBLK_VPU,
341 static struct uio_info veu_platform_data = {
347 static struct resource veu_resources[] = {
352 .flags = IORESOURCE_MEM,
355 /* place holder for contiguous memory */
359 static struct platform_device veu_device = {
360 .name = "uio_pdrv_genirq",
363 .platform_data = &veu_platform_data,
365 .resource = veu_resources,
366 .num_resources = ARRAY_SIZE(veu_resources),
368 .hwblk_id = HWBLK_VEU,
372 static struct uio_info jpu_platform_data = {
378 static struct resource jpu_resources[] = {
383 .flags = IORESOURCE_MEM,
386 /* place holder for contiguous memory */
390 static struct platform_device jpu_device = {
391 .name = "uio_pdrv_genirq",
394 .platform_data = &jpu_platform_data,
396 .resource = jpu_resources,
397 .num_resources = ARRAY_SIZE(jpu_resources),
399 .hwblk_id = HWBLK_JPU,
403 static struct sh_timer_config cmt_platform_data = {
405 .channel_offset = 0x60,
408 .clockevent_rating = 125,
409 .clocksource_rating = 125,
412 static struct resource cmt_resources[] = {
417 .flags = IORESOURCE_MEM,
421 .flags = IORESOURCE_IRQ,
425 static struct platform_device cmt_device = {
429 .platform_data = &cmt_platform_data,
431 .resource = cmt_resources,
432 .num_resources = ARRAY_SIZE(cmt_resources),
434 .hwblk_id = HWBLK_CMT,
438 static struct sh_timer_config tmu0_platform_data = {
440 .channel_offset = 0x04,
443 .clockevent_rating = 200,
446 static struct resource tmu0_resources[] = {
451 .flags = IORESOURCE_MEM,
455 .flags = IORESOURCE_IRQ,
459 static struct platform_device tmu0_device = {
463 .platform_data = &tmu0_platform_data,
465 .resource = tmu0_resources,
466 .num_resources = ARRAY_SIZE(tmu0_resources),
468 .hwblk_id = HWBLK_TMU,
472 static struct sh_timer_config tmu1_platform_data = {
474 .channel_offset = 0x10,
477 .clocksource_rating = 200,
480 static struct resource tmu1_resources[] = {
485 .flags = IORESOURCE_MEM,
489 .flags = IORESOURCE_IRQ,
493 static struct platform_device tmu1_device = {
497 .platform_data = &tmu1_platform_data,
499 .resource = tmu1_resources,
500 .num_resources = ARRAY_SIZE(tmu1_resources),
502 .hwblk_id = HWBLK_TMU,
506 static struct sh_timer_config tmu2_platform_data = {
508 .channel_offset = 0x1c,
513 static struct resource tmu2_resources[] = {
518 .flags = IORESOURCE_MEM,
522 .flags = IORESOURCE_IRQ,
526 static struct platform_device tmu2_device = {
530 .platform_data = &tmu2_platform_data,
532 .resource = tmu2_resources,
533 .num_resources = ARRAY_SIZE(tmu2_resources),
535 .hwblk_id = HWBLK_TMU,
539 static struct siu_platform siu_platform_data = {
540 .dma_dev = &dma_device.dev,
541 .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX,
542 .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX,
543 .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX,
544 .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX,
547 static struct resource siu_resources[] = {
551 .flags = IORESOURCE_MEM,
555 .flags = IORESOURCE_IRQ,
559 static struct platform_device siu_device = {
563 .platform_data = &siu_platform_data,
565 .resource = siu_resources,
566 .num_resources = ARRAY_SIZE(siu_resources),
568 .hwblk_id = HWBLK_SIU,
572 static struct platform_device *sh7722_devices[] __initdata = {
590 static int __init sh7722_devices_setup(void)
592 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
593 platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
594 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
596 return platform_add_devices(sh7722_devices,
597 ARRAY_SIZE(sh7722_devices));
599 arch_initcall(sh7722_devices_setup);
601 static struct platform_device *sh7722_early_devices[] __initdata = {
611 void __init plat_early_device_setup(void)
613 early_platform_add_devices(sh7722_early_devices,
614 ARRAY_SIZE(sh7722_early_devices));
622 /* interrupt sources */
623 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
625 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
626 RTC_ATI, RTC_PRI, RTC_CUI,
627 DMAC0, DMAC1, DMAC2, DMAC3,
628 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
630 USB_USBI0, USB_USBI1,
631 DMAC4, DMAC5, DMAC_DADERR,
633 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
634 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
635 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
636 CMT, TSIF, SIU, TWODG,
640 /* interrupt groups */
641 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
644 static struct intc_vect vectors[] __initdata = {
645 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
646 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
647 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
648 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
649 INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
650 INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
651 INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
652 INTC_VECT(RTC_CUI, 0x7c0),
653 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
654 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
655 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
656 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
657 INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
658 INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
659 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
660 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
661 INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
662 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
663 INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
664 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
665 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
666 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
667 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
668 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
669 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
670 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
671 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
672 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
673 INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
674 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
677 static struct intc_group groups[] __initdata = {
678 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
679 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
680 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
681 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
682 INTC_GROUP(USB, USB_USBI0, USB_USBI1),
683 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
684 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
685 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
686 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
689 static struct intc_mask_reg mask_registers[] __initdata = {
690 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
692 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
693 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
694 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
696 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
697 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
698 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
699 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
700 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
701 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
702 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
703 { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
704 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
705 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
706 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
707 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
708 { DISABLED, DISABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
709 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
710 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
711 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
713 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
714 { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
715 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
716 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
719 static struct intc_prio_reg prio_registers[] __initdata = {
720 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
721 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
722 { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
723 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
724 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
725 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
726 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
727 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
728 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
729 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
730 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
731 { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
732 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
733 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
736 static struct intc_sense_reg sense_registers[] __initdata = {
737 { 0xa414001c, 16, 2, /* ICR1 */
738 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
741 static struct intc_mask_reg ack_registers[] __initdata = {
742 { 0xa4140024, 0, 8, /* INTREQ00 */
743 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
746 static struct intc_desc intc_desc __initdata = {
748 .force_enable = ENABLED,
749 .force_disable = DISABLED,
750 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
751 prio_registers, sense_registers, ack_registers),
754 void __init plat_irq_setup(void)
756 register_intc_controller(&intc_desc);
759 void __init plat_mem_setup(void)
761 /* Register the URAM space as Node 1 */
762 setup_bootmem_node(1, 0x055f0000, 0x05610000);