arch/sh/kernel/cpu/sh4a/setup-sh7722.c

   1 /*
   2  * SH7722 Setup
   3  *
   4  *  Copyright (C) 2006 - 2008  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/init.h>
  11 #include <linux/mm.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/serial.h>
  14 #include <linux/serial_sci.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/uio_driver.h>
  17 #include <linux/usb/m66592.h>
  18
  19 #include <asm/clock.h>
  20 #include <asm/mmzone.h>
  21 #include <asm/siu.h>
  22
  23 #include <cpu/dma-register.h>
  24 #include <cpu/sh7722.h>
  25
  26 static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
  27         {
  28                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
  29                 .addr           = 0xffe0000c,
  30                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  31                 .mid_rid        = 0x21,
  32         }, {
  33                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
  34                 .addr           = 0xffe00014,
  35                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  36                 .mid_rid        = 0x22,
  37         }, {
  38                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
  39                 .addr           = 0xffe1000c,
  40                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  41                 .mid_rid        = 0x25,
  42         }, {
  43                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
  44                 .addr           = 0xffe10014,
  45                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  46                 .mid_rid        = 0x26,
  47         }, {
  48                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
  49                 .addr           = 0xffe2000c,
  50                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  51                 .mid_rid        = 0x29,
  52         }, {
  53                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
  54                 .addr           = 0xffe20014,
  55                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  56                 .mid_rid        = 0x2a,
  57         }, {
  58                 .slave_id       = SHDMA_SLAVE_SIUA_TX,
  59                 .addr           = 0xa454c098,
  60                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
  61                 .mid_rid        = 0xb1,
  62         }, {
  63                 .slave_id       = SHDMA_SLAVE_SIUA_RX,
  64                 .addr           = 0xa454c090,
  65                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
  66                 .mid_rid        = 0xb2,
  67         }, {
  68                 .slave_id       = SHDMA_SLAVE_SIUB_TX,
  69                 .addr           = 0xa454c09c,
  70                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
  71                 .mid_rid        = 0xb5,
  72         }, {
  73                 .slave_id       = SHDMA_SLAVE_SIUB_RX,
  74                 .addr           = 0xa454c094,
  75                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
  76                 .mid_rid        = 0xb6,
  77         },
  78 };
  79
  80 static const struct sh_dmae_channel sh7722_dmae_channels[] = {
  81         {
  82                 .offset = 0,
  83                 .dmars = 0,
  84                 .dmars_bit = 0,
  85         }, {
  86                 .offset = 0x10,
  87                 .dmars = 0,
  88                 .dmars_bit = 8,
  89         }, {
  90                 .offset = 0x20,
  91                 .dmars = 4,
  92                 .dmars_bit = 0,
  93         }, {
  94                 .offset = 0x30,
  95                 .dmars = 4,
  96                 .dmars_bit = 8,
  97         }, {
  98                 .offset = 0x50,
  99                 .dmars = 8,
 100                 .dmars_bit = 0,
 101         }, {
 102                 .offset = 0x60,
 103                 .dmars = 8,
 104                 .dmars_bit = 8,
 105         }
 106 };
 107
 108 static const unsigned int ts_shift[] = TS_SHIFT;
 109
 110 static struct sh_dmae_pdata dma_platform_data = {
 111         .slave          = sh7722_dmae_slaves,
 112         .slave_num      = ARRAY_SIZE(sh7722_dmae_slaves),
 113         .channel        = sh7722_dmae_channels,
 114         .channel_num    = ARRAY_SIZE(sh7722_dmae_channels),
 115         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 116         .ts_low_mask    = CHCR_TS_LOW_MASK,
 117         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 118         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 119         .ts_shift       = ts_shift,
 120         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 121         .dmaor_init     = DMAOR_INIT,
 122 };
 123
 124 static struct resource sh7722_dmae_resources[] = {
 125         [0] = {
 126                 /* Channel registers and DMAOR */
 127                 .start  = 0xfe008020,
 128                 .end    = 0xfe00808f,
 129                 .flags  = IORESOURCE_MEM,
 130         },
 131         [1] = {
 132                 /* DMARSx */
 133                 .start  = 0xfe009000,
 134                 .end    = 0xfe00900b,
 135                 .flags  = IORESOURCE_MEM,
 136         },
 137         {
 138                 /* DMA error IRQ */
 139                 .start  = 78,
 140                 .end    = 78,
 141                 .flags  = IORESOURCE_IRQ,
 142         },
 143         {
 144                 /* IRQ for channels 0-3 */
 145                 .start  = 48,
 146                 .end    = 51,
 147                 .flags  = IORESOURCE_IRQ,
 148         },
 149         {
 150                 /* IRQ for channels 4-5 */
 151                 .start  = 76,
 152                 .end    = 77,
 153                 .flags  = IORESOURCE_IRQ,
 154         },
 155 };
 156
 157 struct platform_device dma_device = {
 158         .name           = "sh-dma-engine",
 159         .id             = -1,
 160         .resource       = sh7722_dmae_resources,
 161         .num_resources  = ARRAY_SIZE(sh7722_dmae_resources),
 162         .dev            = {
 163                 .platform_data  = &dma_platform_data,
 164         },
 165         .archdata = {
 166                 .hwblk_id = HWBLK_DMAC,
 167         },
 168 };
 169
 170 /* Serial */
 171 static struct plat_sci_port scif0_platform_data = {
 172         .mapbase        = 0xffe00000,
 173         .flags          = UPF_BOOT_AUTOCONF,
 174         .type           = PORT_SCIF,
 175         .irqs           = { 80, 80, 80, 80 },
 176 };
 177
 178 static struct platform_device scif0_device = {
 179         .name           = "sh-sci",
 180         .id             = 0,
 181         .dev            = {
 182                 .platform_data  = &scif0_platform_data,
 183         },
 184 };
 185
 186 static struct plat_sci_port scif1_platform_data = {
 187         .mapbase        = 0xffe10000,
 188         .flags          = UPF_BOOT_AUTOCONF,
 189         .type           = PORT_SCIF,
 190         .irqs           = { 81, 81, 81, 81 },
 191 };
 192
 193 static struct platform_device scif1_device = {
 194         .name           = "sh-sci",
 195         .id             = 1,
 196         .dev            = {
 197                 .platform_data  = &scif1_platform_data,
 198         },
 199 };
 200
 201 static struct plat_sci_port scif2_platform_data = {
 202         .mapbase        = 0xffe20000,
 203         .flags          = UPF_BOOT_AUTOCONF,
 204         .type           = PORT_SCIF,
 205         .irqs           = { 82, 82, 82, 82 },
 206 };
 207
 208 static struct platform_device scif2_device = {
 209         .name           = "sh-sci",
 210         .id             = 2,
 211         .dev            = {
 212                 .platform_data  = &scif2_platform_data,
 213         },
 214 };
 215
 216 static struct resource rtc_resources[] = {
 217         [0] = {
 218                 .start  = 0xa465fec0,
 219                 .end    = 0xa465fec0 + 0x58 - 1,
 220                 .flags  = IORESOURCE_IO,
 221         },
 222         [1] = {
 223                 /* Period IRQ */
 224                 .start  = 45,
 225                 .flags  = IORESOURCE_IRQ,
 226         },
 227         [2] = {
 228                 /* Carry IRQ */
 229                 .start  = 46,
 230                 .flags  = IORESOURCE_IRQ,
 231         },
 232         [3] = {
 233                 /* Alarm IRQ */
 234                 .start  = 44,
 235                 .flags  = IORESOURCE_IRQ,
 236         },
 237 };
 238
 239 static struct platform_device rtc_device = {
 240         .name           = "sh-rtc",
 241         .id             = -1,
 242         .num_resources  = ARRAY_SIZE(rtc_resources),
 243         .resource       = rtc_resources,
 244         .archdata = {
 245                 .hwblk_id = HWBLK_RTC,
 246         },
 247 };
 248
 249 static struct m66592_platdata usbf_platdata = {
 250         .on_chip = 1,
 251 };
 252
 253 static struct resource usbf_resources[] = {
 254         [0] = {
 255                 .name   = "USBF",
 256                 .start  = 0x04480000,
 257                 .end    = 0x044800FF,
 258                 .flags  = IORESOURCE_MEM,
 259         },
 260         [1] = {
 261                 .start  = 65,
 262                 .end    = 65,
 263                 .flags  = IORESOURCE_IRQ,
 264         },
 265 };
 266
 267 static struct platform_device usbf_device = {
 268         .name           = "m66592_udc",
 269         .id             = 0, /* "usbf0" clock */
 270         .dev = {
 271                 .dma_mask               = NULL,
 272                 .coherent_dma_mask      = 0xffffffff,
 273                 .platform_data          = &usbf_platdata,
 274         },
 275         .num_resources  = ARRAY_SIZE(usbf_resources),
 276         .resource       = usbf_resources,
 277         .archdata = {
 278                 .hwblk_id = HWBLK_USBF,
 279         },
 280 };
 281
 282 static struct resource iic_resources[] = {
 283         [0] = {
 284                 .name   = "IIC",
 285                 .start  = 0x04470000,
 286                 .end    = 0x04470017,
 287                 .flags  = IORESOURCE_MEM,
 288         },
 289         [1] = {
 290                 .start  = 96,
 291                 .end    = 99,
 292                 .flags  = IORESOURCE_IRQ,
 293        },
 294 };
 295
 296 static struct platform_device iic_device = {
 297         .name           = "i2c-sh_mobile",
 298         .id             = 0, /* "i2c0" clock */
 299         .num_resources  = ARRAY_SIZE(iic_resources),
 300         .resource       = iic_resources,
 301         .archdata = {
 302                 .hwblk_id = HWBLK_IIC,
 303         },
 304 };
 305
 306 static struct uio_info vpu_platform_data = {
 307         .name = "VPU4",
 308         .version = "0",
 309         .irq = 60,
 310 };
 311
 312 static struct resource vpu_resources[] = {
 313         [0] = {
 314                 .name   = "VPU",
 315                 .start  = 0xfe900000,
 316                 .end    = 0xfe9022eb,
 317                 .flags  = IORESOURCE_MEM,
 318         },
 319         [1] = {
 320                 /* place holder for contiguous memory */
 321         },
 322 };
 323
 324 static struct platform_device vpu_device = {
 325         .name           = "uio_pdrv_genirq",
 326         .id             = 0,
 327         .dev = {
 328                 .platform_data  = &vpu_platform_data,
 329         },
 330         .resource       = vpu_resources,
 331         .num_resources  = ARRAY_SIZE(vpu_resources),
 332         .archdata = {
 333                 .hwblk_id = HWBLK_VPU,
 334         },
 335 };
 336
 337 static struct uio_info veu_platform_data = {
 338         .name = "VEU",
 339         .version = "0",
 340         .irq = 54,
 341 };
 342
 343 static struct resource veu_resources[] = {
 344         [0] = {
 345                 .name   = "VEU",
 346                 .start  = 0xfe920000,
 347                 .end    = 0xfe9200b7,
 348                 .flags  = IORESOURCE_MEM,
 349         },
 350         [1] = {
 351                 /* place holder for contiguous memory */
 352         },
 353 };
 354
 355 static struct platform_device veu_device = {
 356         .name           = "uio_pdrv_genirq",
 357         .id             = 1,
 358         .dev = {
 359                 .platform_data  = &veu_platform_data,
 360         },
 361         .resource       = veu_resources,
 362         .num_resources  = ARRAY_SIZE(veu_resources),
 363         .archdata = {
 364                 .hwblk_id = HWBLK_VEU,
 365         },
 366 };
 367
 368 static struct uio_info jpu_platform_data = {
 369         .name = "JPU",
 370         .version = "0",
 371         .irq = 27,
 372 };
 373
 374 static struct resource jpu_resources[] = {
 375         [0] = {
 376                 .name   = "JPU",
 377                 .start  = 0xfea00000,
 378                 .end    = 0xfea102d3,
 379                 .flags  = IORESOURCE_MEM,
 380         },
 381         [1] = {
 382                 /* place holder for contiguous memory */
 383         },
 384 };
 385
 386 static struct platform_device jpu_device = {
 387         .name           = "uio_pdrv_genirq",
 388         .id             = 2,
 389         .dev = {
 390                 .platform_data  = &jpu_platform_data,
 391         },
 392         .resource       = jpu_resources,
 393         .num_resources  = ARRAY_SIZE(jpu_resources),
 394         .archdata = {
 395                 .hwblk_id = HWBLK_JPU,
 396         },
 397 };
 398
 399 static struct sh_timer_config cmt_platform_data = {
 400         .channel_offset = 0x60,
 401         .timer_bit = 5,
 402         .clockevent_rating = 125,
 403         .clocksource_rating = 125,
 404 };
 405
 406 static struct resource cmt_resources[] = {
 407         [0] = {
 408                 .start  = 0x044a0060,
 409                 .end    = 0x044a006b,
 410                 .flags  = IORESOURCE_MEM,
 411         },
 412         [1] = {
 413                 .start  = 104,
 414                 .flags  = IORESOURCE_IRQ,
 415         },
 416 };
 417
 418 static struct platform_device cmt_device = {
 419         .name           = "sh_cmt",
 420         .id             = 0,
 421         .dev = {
 422                 .platform_data  = &cmt_platform_data,
 423         },
 424         .resource       = cmt_resources,
 425         .num_resources  = ARRAY_SIZE(cmt_resources),
 426         .archdata = {
 427                 .hwblk_id = HWBLK_CMT,
 428         },
 429 };
 430
 431 static struct sh_timer_config tmu0_platform_data = {
 432         .channel_offset = 0x04,
 433         .timer_bit = 0,
 434         .clockevent_rating = 200,
 435 };
 436
 437 static struct resource tmu0_resources[] = {
 438         [0] = {
 439                 .start  = 0xffd80008,
 440                 .end    = 0xffd80013,
 441                 .flags  = IORESOURCE_MEM,
 442         },
 443         [1] = {
 444                 .start  = 16,
 445                 .flags  = IORESOURCE_IRQ,
 446         },
 447 };
 448
 449 static struct platform_device tmu0_device = {
 450         .name           = "sh_tmu",
 451         .id             = 0,
 452         .dev = {
 453                 .platform_data  = &tmu0_platform_data,
 454         },
 455         .resource       = tmu0_resources,
 456         .num_resources  = ARRAY_SIZE(tmu0_resources),
 457         .archdata = {
 458                 .hwblk_id = HWBLK_TMU,
 459         },
 460 };
 461
 462 static struct sh_timer_config tmu1_platform_data = {
 463         .channel_offset = 0x10,
 464         .timer_bit = 1,
 465         .clocksource_rating = 200,
 466 };
 467
 468 static struct resource tmu1_resources[] = {
 469         [0] = {
 470                 .start  = 0xffd80014,
 471                 .end    = 0xffd8001f,
 472                 .flags  = IORESOURCE_MEM,
 473         },
 474         [1] = {
 475                 .start  = 17,
 476                 .flags  = IORESOURCE_IRQ,
 477         },
 478 };
 479
 480 static struct platform_device tmu1_device = {
 481         .name           = "sh_tmu",
 482         .id             = 1,
 483         .dev = {
 484                 .platform_data  = &tmu1_platform_data,
 485         },
 486         .resource       = tmu1_resources,
 487         .num_resources  = ARRAY_SIZE(tmu1_resources),
 488         .archdata = {
 489                 .hwblk_id = HWBLK_TMU,
 490         },
 491 };
 492
 493 static struct sh_timer_config tmu2_platform_data = {
 494         .channel_offset = 0x1c,
 495         .timer_bit = 2,
 496 };
 497
 498 static struct resource tmu2_resources[] = {
 499         [0] = {
 500                 .start  = 0xffd80020,
 501                 .end    = 0xffd8002b,
 502                 .flags  = IORESOURCE_MEM,
 503         },
 504         [1] = {
 505                 .start  = 18,
 506                 .flags  = IORESOURCE_IRQ,
 507         },
 508 };
 509
 510 static struct platform_device tmu2_device = {
 511         .name           = "sh_tmu",
 512         .id             = 2,
 513         .dev = {
 514                 .platform_data  = &tmu2_platform_data,
 515         },
 516         .resource       = tmu2_resources,
 517         .num_resources  = ARRAY_SIZE(tmu2_resources),
 518         .archdata = {
 519                 .hwblk_id = HWBLK_TMU,
 520         },
 521 };
 522
 523 static struct siu_platform siu_platform_data = {
 524         .dma_dev        = &dma_device.dev,
 525         .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX,
 526         .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX,
 527         .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX,
 528         .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX,
 529 };
 530
 531 static struct resource siu_resources[] = {
 532         [0] = {
 533                 .start  = 0xa4540000,
 534                 .end    = 0xa454c10f,
 535                 .flags  = IORESOURCE_MEM,
 536         },
 537         [1] = {
 538                 .start  = 108,
 539                 .flags  = IORESOURCE_IRQ,
 540         },
 541 };
 542
 543 static struct platform_device siu_device = {
 544         .name           = "sh_siu",
 545         .id             = -1,
 546         .dev = {
 547                 .platform_data  = &siu_platform_data,
 548         },
 549         .resource       = siu_resources,
 550         .num_resources  = ARRAY_SIZE(siu_resources),
 551         .archdata = {
 552                 .hwblk_id = HWBLK_SIU,
 553         },
 554 };
 555
 556 static struct platform_device *sh7722_devices[] __initdata = {
 557         &scif0_device,
 558         &scif1_device,
 559         &scif2_device,
 560         &cmt_device,
 561         &tmu0_device,
 562         &tmu1_device,
 563         &tmu2_device,
 564         &rtc_device,
 565         &usbf_device,
 566         &iic_device,
 567         &vpu_device,
 568         &veu_device,
 569         &jpu_device,
 570         &siu_device,
 571         &dma_device,
 572 };
 573
 574 static int __init sh7722_devices_setup(void)
 575 {
 576         platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
 577         platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
 578         platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
 579
 580         return platform_add_devices(sh7722_devices,
 581                                     ARRAY_SIZE(sh7722_devices));
 582 }
 583 arch_initcall(sh7722_devices_setup);
 584
 585 static struct platform_device *sh7722_early_devices[] __initdata = {
 586         &scif0_device,
 587         &scif1_device,
 588         &scif2_device,
 589         &cmt_device,
 590         &tmu0_device,
 591         &tmu1_device,
 592         &tmu2_device,
 593 };
 594
 595 void __init plat_early_device_setup(void)
 596 {
 597         early_platform_add_devices(sh7722_early_devices,
 598                                    ARRAY_SIZE(sh7722_early_devices));
 599 }
 600
 601 enum {
 602         UNUSED=0,
 603         ENABLED,
 604         DISABLED,
 605
 606         /* interrupt sources */
 607         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 608         HUDI,
 609         SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
 610         RTC_ATI, RTC_PRI, RTC_CUI,
 611         DMAC0, DMAC1, DMAC2, DMAC3,
 612         VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
 613         VPU, TPU,
 614         USB_USBI0, USB_USBI1,
 615         DMAC4, DMAC5, DMAC_DADERR,
 616         KEYSC,
 617         SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
 618         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
 619         I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
 620         CMT, TSIF, SIU, TWODG,
 621         TMU0, TMU1, TMU2,
 622         IRDA, JPU, LCDC,
 623
 624         /* interrupt groups */
 625         SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
 626 };
 627
 628 static struct intc_vect vectors[] __initdata = {
 629         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 630         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 631         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 632         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 633         INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
 634         INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
 635         INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
 636         INTC_VECT(RTC_CUI, 0x7c0),
 637         INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
 638         INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
 639         INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
 640         INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
 641         INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
 642         INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
 643         INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
 644         INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
 645         INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
 646         INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
 647         INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
 648         INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
 649         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
 650         INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
 651         INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
 652         INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
 653         INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
 654         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
 655         INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
 656         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 657         INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
 658         INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
 659 };
 660
 661 static struct intc_group groups[] __initdata = {
 662         INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
 663         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
 664         INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
 665         INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
 666         INTC_GROUP(USB, USB_USBI0, USB_USBI1),
 667         INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
 668         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
 669                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
 670         INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
 671 };
 672
 673 static struct intc_mask_reg mask_registers[] __initdata = {
 674         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
 675           { } },
 676         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 677           { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
 678         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 679           { 0, 0, 0, VPU, } },
 680         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 681           { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
 682         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 683           { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
 684         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 685           { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
 686         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 687           { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
 688         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 689           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
 690             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
 691         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 692           { DISABLED, DISABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
 693         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 694           { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
 695         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 696           { } },
 697         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 698           { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
 699         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 700           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 701 };
 702
 703 static struct intc_prio_reg prio_registers[] __initdata = {
 704         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
 705         { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
 706         { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
 707         { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
 708         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
 709         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
 710         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
 711         { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
 712         { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
 713         { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
 714         { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
 715         { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
 716         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 717           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 718 };
 719
 720 static struct intc_sense_reg sense_registers[] __initdata = {
 721         { 0xa414001c, 16, 2, /* ICR1 */
 722           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 723 };
 724
 725 static struct intc_mask_reg ack_registers[] __initdata = {
 726         { 0xa4140024, 0, 8, /* INTREQ00 */
 727           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 728 };
 729
 730 static struct intc_desc intc_desc __initdata = {
 731         .name = "sh7722",
 732         .force_enable = ENABLED,
 733         .force_disable = DISABLED,
 734         .hw = INTC_HW_DESC(vectors, groups, mask_registers,
 735                            prio_registers, sense_registers, ack_registers),
 736 };
 737
 738 void __init plat_irq_setup(void)
 739 {
 740         register_intc_controller(&intc_desc);
 741 }
 742
 743 void __init plat_mem_setup(void)
 744 {
 745         /* Register the URAM space as Node 1 */
 746         setup_bootmem_node(1, 0x055f0000, 0x05610000);
 747 }