arch/sh/kernel/cpu/sh4a/setup-sh7722.c

   1 /*
   2  * SH7722 Setup
   3  *
   4  *  Copyright (C) 2006 - 2008  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/mm.h>
  15 #include <linux/uio_driver.h>
  16 #include <linux/usb/m66592.h>
  17 #include <linux/sh_timer.h>
  18 #include <asm/clock.h>
  19 #include <asm/mmzone.h>
  20 #include <asm/dma-sh.h>
  21 #include <cpu/sh7722.h>
  22
  23 /* Serial */
  24 static struct plat_sci_port scif0_platform_data = {
  25         .mapbase        = 0xffe00000,
  26         .flags          = UPF_BOOT_AUTOCONF,
  27         .type           = PORT_SCIF,
  28         .irqs           = { 80, 80, 80, 80 },
  29         .clk            = "scif0",
  30 };
  31
  32 static struct platform_device scif0_device = {
  33         .name           = "sh-sci",
  34         .id             = 0,
  35         .dev            = {
  36                 .platform_data  = &scif0_platform_data,
  37         },
  38 };
  39
  40 static struct plat_sci_port scif1_platform_data = {
  41         .mapbase        = 0xffe10000,
  42         .flags          = UPF_BOOT_AUTOCONF,
  43         .type           = PORT_SCIF,
  44         .irqs           = { 81, 81, 81, 81 },
  45         .clk            = "scif1",
  46 };
  47
  48 static struct platform_device scif1_device = {
  49         .name           = "sh-sci",
  50         .id             = 1,
  51         .dev            = {
  52                 .platform_data  = &scif1_platform_data,
  53         },
  54 };
  55
  56 static struct plat_sci_port scif2_platform_data = {
  57         .mapbase        = 0xffe20000,
  58         .flags          = UPF_BOOT_AUTOCONF,
  59         .type           = PORT_SCIF,
  60         .irqs           = { 82, 82, 82, 82 },
  61         .clk            = "scif2",
  62 };
  63
  64 static struct platform_device scif2_device = {
  65         .name           = "sh-sci",
  66         .id             = 2,
  67         .dev            = {
  68                 .platform_data  = &scif2_platform_data,
  69         },
  70 };
  71
  72 static struct resource rtc_resources[] = {
  73         [0] = {
  74                 .start  = 0xa465fec0,
  75                 .end    = 0xa465fec0 + 0x58 - 1,
  76                 .flags  = IORESOURCE_IO,
  77         },
  78         [1] = {
  79                 /* Period IRQ */
  80                 .start  = 45,
  81                 .flags  = IORESOURCE_IRQ,
  82         },
  83         [2] = {
  84                 /* Carry IRQ */
  85                 .start  = 46,
  86                 .flags  = IORESOURCE_IRQ,
  87         },
  88         [3] = {
  89                 /* Alarm IRQ */
  90                 .start  = 44,
  91                 .flags  = IORESOURCE_IRQ,
  92         },
  93 };
  94
  95 static struct platform_device rtc_device = {
  96         .name           = "sh-rtc",
  97         .id             = -1,
  98         .num_resources  = ARRAY_SIZE(rtc_resources),
  99         .resource       = rtc_resources,
 100         .archdata = {
 101                 .hwblk_id = HWBLK_RTC,
 102         },
 103 };
 104
 105 static struct m66592_platdata usbf_platdata = {
 106         .on_chip = 1,
 107 };
 108
 109 static struct resource usbf_resources[] = {
 110         [0] = {
 111                 .name   = "USBF",
 112                 .start  = 0x04480000,
 113                 .end    = 0x044800FF,
 114                 .flags  = IORESOURCE_MEM,
 115         },
 116         [1] = {
 117                 .start  = 65,
 118                 .end    = 65,
 119                 .flags  = IORESOURCE_IRQ,
 120         },
 121 };
 122
 123 static struct platform_device usbf_device = {
 124         .name           = "m66592_udc",
 125         .id             = 0, /* "usbf0" clock */
 126         .dev = {
 127                 .dma_mask               = NULL,
 128                 .coherent_dma_mask      = 0xffffffff,
 129                 .platform_data          = &usbf_platdata,
 130         },
 131         .num_resources  = ARRAY_SIZE(usbf_resources),
 132         .resource       = usbf_resources,
 133         .archdata = {
 134                 .hwblk_id = HWBLK_USBF,
 135         },
 136 };
 137
 138 static struct resource iic_resources[] = {
 139         [0] = {
 140                 .name   = "IIC",
 141                 .start  = 0x04470000,
 142                 .end    = 0x04470017,
 143                 .flags  = IORESOURCE_MEM,
 144         },
 145         [1] = {
 146                 .start  = 96,
 147                 .end    = 99,
 148                 .flags  = IORESOURCE_IRQ,
 149        },
 150 };
 151
 152 static struct platform_device iic_device = {
 153         .name           = "i2c-sh_mobile",
 154         .id             = 0, /* "i2c0" clock */
 155         .num_resources  = ARRAY_SIZE(iic_resources),
 156         .resource       = iic_resources,
 157         .archdata = {
 158                 .hwblk_id = HWBLK_IIC,
 159         },
 160 };
 161
 162 static struct uio_info vpu_platform_data = {
 163         .name = "VPU4",
 164         .version = "0",
 165         .irq = 60,
 166 };
 167
 168 static struct resource vpu_resources[] = {
 169         [0] = {
 170                 .name   = "VPU",
 171                 .start  = 0xfe900000,
 172                 .end    = 0xfe9022eb,
 173                 .flags  = IORESOURCE_MEM,
 174         },
 175         [1] = {
 176                 /* place holder for contiguous memory */
 177         },
 178 };
 179
 180 static struct platform_device vpu_device = {
 181         .name           = "uio_pdrv_genirq",
 182         .id             = 0,
 183         .dev = {
 184                 .platform_data  = &vpu_platform_data,
 185         },
 186         .resource       = vpu_resources,
 187         .num_resources  = ARRAY_SIZE(vpu_resources),
 188         .archdata = {
 189                 .hwblk_id = HWBLK_VPU,
 190         },
 191 };
 192
 193 static struct uio_info veu_platform_data = {
 194         .name = "VEU",
 195         .version = "0",
 196         .irq = 54,
 197 };
 198
 199 static struct resource veu_resources[] = {
 200         [0] = {
 201                 .name   = "VEU",
 202                 .start  = 0xfe920000,
 203                 .end    = 0xfe9200b7,
 204                 .flags  = IORESOURCE_MEM,
 205         },
 206         [1] = {
 207                 /* place holder for contiguous memory */
 208         },
 209 };
 210
 211 static struct platform_device veu_device = {
 212         .name           = "uio_pdrv_genirq",
 213         .id             = 1,
 214         .dev = {
 215                 .platform_data  = &veu_platform_data,
 216         },
 217         .resource       = veu_resources,
 218         .num_resources  = ARRAY_SIZE(veu_resources),
 219         .archdata = {
 220                 .hwblk_id = HWBLK_VEU,
 221         },
 222 };
 223
 224 static struct uio_info jpu_platform_data = {
 225         .name = "JPU",
 226         .version = "0",
 227         .irq = 27,
 228 };
 229
 230 static struct resource jpu_resources[] = {
 231         [0] = {
 232                 .name   = "JPU",
 233                 .start  = 0xfea00000,
 234                 .end    = 0xfea102d3,
 235                 .flags  = IORESOURCE_MEM,
 236         },
 237         [1] = {
 238                 /* place holder for contiguous memory */
 239         },
 240 };
 241
 242 static struct platform_device jpu_device = {
 243         .name           = "uio_pdrv_genirq",
 244         .id             = 2,
 245         .dev = {
 246                 .platform_data  = &jpu_platform_data,
 247         },
 248         .resource       = jpu_resources,
 249         .num_resources  = ARRAY_SIZE(jpu_resources),
 250         .archdata = {
 251                 .hwblk_id = HWBLK_JPU,
 252         },
 253 };
 254
 255 static struct sh_timer_config cmt_platform_data = {
 256         .name = "CMT",
 257         .channel_offset = 0x60,
 258         .timer_bit = 5,
 259         .clk = "cmt0",
 260         .clockevent_rating = 125,
 261         .clocksource_rating = 125,
 262 };
 263
 264 static struct resource cmt_resources[] = {
 265         [0] = {
 266                 .name   = "CMT",
 267                 .start  = 0x044a0060,
 268                 .end    = 0x044a006b,
 269                 .flags  = IORESOURCE_MEM,
 270         },
 271         [1] = {
 272                 .start  = 104,
 273                 .flags  = IORESOURCE_IRQ,
 274         },
 275 };
 276
 277 static struct platform_device cmt_device = {
 278         .name           = "sh_cmt",
 279         .id             = 0,
 280         .dev = {
 281                 .platform_data  = &cmt_platform_data,
 282         },
 283         .resource       = cmt_resources,
 284         .num_resources  = ARRAY_SIZE(cmt_resources),
 285         .archdata = {
 286                 .hwblk_id = HWBLK_CMT,
 287         },
 288 };
 289
 290 static struct sh_timer_config tmu0_platform_data = {
 291         .name = "TMU0",
 292         .channel_offset = 0x04,
 293         .timer_bit = 0,
 294         .clk = "tmu0",
 295         .clockevent_rating = 200,
 296 };
 297
 298 static struct resource tmu0_resources[] = {
 299         [0] = {
 300                 .name   = "TMU0",
 301                 .start  = 0xffd80008,
 302                 .end    = 0xffd80013,
 303                 .flags  = IORESOURCE_MEM,
 304         },
 305         [1] = {
 306                 .start  = 16,
 307                 .flags  = IORESOURCE_IRQ,
 308         },
 309 };
 310
 311 static struct platform_device tmu0_device = {
 312         .name           = "sh_tmu",
 313         .id             = 0,
 314         .dev = {
 315                 .platform_data  = &tmu0_platform_data,
 316         },
 317         .resource       = tmu0_resources,
 318         .num_resources  = ARRAY_SIZE(tmu0_resources),
 319         .archdata = {
 320                 .hwblk_id = HWBLK_TMU,
 321         },
 322 };
 323
 324 static struct sh_timer_config tmu1_platform_data = {
 325         .name = "TMU1",
 326         .channel_offset = 0x10,
 327         .timer_bit = 1,
 328         .clk = "tmu0",
 329         .clocksource_rating = 200,
 330 };
 331
 332 static struct resource tmu1_resources[] = {
 333         [0] = {
 334                 .name   = "TMU1",
 335                 .start  = 0xffd80014,
 336                 .end    = 0xffd8001f,
 337                 .flags  = IORESOURCE_MEM,
 338         },
 339         [1] = {
 340                 .start  = 17,
 341                 .flags  = IORESOURCE_IRQ,
 342         },
 343 };
 344
 345 static struct platform_device tmu1_device = {
 346         .name           = "sh_tmu",
 347         .id             = 1,
 348         .dev = {
 349                 .platform_data  = &tmu1_platform_data,
 350         },
 351         .resource       = tmu1_resources,
 352         .num_resources  = ARRAY_SIZE(tmu1_resources),
 353         .archdata = {
 354                 .hwblk_id = HWBLK_TMU,
 355         },
 356 };
 357
 358 static struct sh_timer_config tmu2_platform_data = {
 359         .name = "TMU2",
 360         .channel_offset = 0x1c,
 361         .timer_bit = 2,
 362         .clk = "tmu0",
 363 };
 364
 365 static struct resource tmu2_resources[] = {
 366         [0] = {
 367                 .name   = "TMU2",
 368                 .start  = 0xffd80020,
 369                 .end    = 0xffd8002b,
 370                 .flags  = IORESOURCE_MEM,
 371         },
 372         [1] = {
 373                 .start  = 18,
 374                 .flags  = IORESOURCE_IRQ,
 375         },
 376 };
 377
 378 static struct platform_device tmu2_device = {
 379         .name           = "sh_tmu",
 380         .id             = 2,
 381         .dev = {
 382                 .platform_data  = &tmu2_platform_data,
 383         },
 384         .resource       = tmu2_resources,
 385         .num_resources  = ARRAY_SIZE(tmu2_resources),
 386         .archdata = {
 387                 .hwblk_id = HWBLK_TMU,
 388         },
 389 };
 390
 391 static struct sh_dmae_pdata dma_platform_data = {
 392         .mode = 0,
 393 };
 394
 395 static struct platform_device dma_device = {
 396         .name           = "sh-dma-engine",
 397         .id             = -1,
 398         .dev            = {
 399                 .platform_data  = &dma_platform_data,
 400         },
 401 };
 402
 403 static struct platform_device *sh7722_devices[] __initdata = {
 404         &scif0_device,
 405         &scif1_device,
 406         &scif2_device,
 407         &cmt_device,
 408         &tmu0_device,
 409         &tmu1_device,
 410         &tmu2_device,
 411         &rtc_device,
 412         &usbf_device,
 413         &iic_device,
 414         &vpu_device,
 415         &veu_device,
 416         &jpu_device,
 417         &dma_device,
 418 };
 419
 420 static int __init sh7722_devices_setup(void)
 421 {
 422         platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
 423         platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
 424         platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
 425
 426         return platform_add_devices(sh7722_devices,
 427                                     ARRAY_SIZE(sh7722_devices));
 428 }
 429 arch_initcall(sh7722_devices_setup);
 430
 431 static struct platform_device *sh7722_early_devices[] __initdata = {
 432         &scif0_device,
 433         &scif1_device,
 434         &scif2_device,
 435         &cmt_device,
 436         &tmu0_device,
 437         &tmu1_device,
 438         &tmu2_device,
 439 };
 440
 441 void __init plat_early_device_setup(void)
 442 {
 443         early_platform_add_devices(sh7722_early_devices,
 444                                    ARRAY_SIZE(sh7722_early_devices));
 445 }
 446
 447 enum {
 448         UNUSED=0,
 449         ENABLED,
 450         DISABLED,
 451
 452         /* interrupt sources */
 453         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 454         HUDI,
 455         SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
 456         RTC_ATI, RTC_PRI, RTC_CUI,
 457         DMAC0, DMAC1, DMAC2, DMAC3,
 458         VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
 459         VPU, TPU,
 460         USB_USBI0, USB_USBI1,
 461         DMAC4, DMAC5, DMAC_DADERR,
 462         KEYSC,
 463         SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
 464         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
 465         I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
 466         CMT, TSIF, SIU, TWODG,
 467         TMU0, TMU1, TMU2,
 468         IRDA, JPU, LCDC,
 469
 470         /* interrupt groups */
 471         SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
 472 };
 473
 474 static struct intc_vect vectors[] __initdata = {
 475         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 476         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 477         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 478         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 479         INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
 480         INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
 481         INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
 482         INTC_VECT(RTC_CUI, 0x7c0),
 483         INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
 484         INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
 485         INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
 486         INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
 487         INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
 488         INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
 489         INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
 490         INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
 491         INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
 492         INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
 493         INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
 494         INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
 495         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
 496         INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
 497         INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
 498         INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
 499         INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
 500         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
 501         INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
 502         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 503         INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
 504         INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
 505 };
 506
 507 static struct intc_group groups[] __initdata = {
 508         INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
 509         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
 510         INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
 511         INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
 512         INTC_GROUP(USB, USB_USBI0, USB_USBI1),
 513         INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
 514         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
 515                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
 516         INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
 517 };
 518
 519 static struct intc_mask_reg mask_registers[] __initdata = {
 520         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
 521           { } },
 522         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 523           { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
 524         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 525           { 0, 0, 0, VPU, } },
 526         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 527           { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
 528         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 529           { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
 530         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 531           { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
 532         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 533           { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
 534         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 535           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
 536             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
 537         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 538           { DISABLED, DISABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
 539         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 540           { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
 541         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 542           { } },
 543         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 544           { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
 545         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 546           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 547 };
 548
 549 static struct intc_prio_reg prio_registers[] __initdata = {
 550         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
 551         { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
 552         { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
 553         { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
 554         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
 555         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
 556         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
 557         { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
 558         { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
 559         { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
 560         { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
 561         { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
 562         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 563           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 564 };
 565
 566 static struct intc_sense_reg sense_registers[] __initdata = {
 567         { 0xa414001c, 16, 2, /* ICR1 */
 568           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 569 };
 570
 571 static struct intc_mask_reg ack_registers[] __initdata = {
 572         { 0xa4140024, 0, 8, /* INTREQ00 */
 573           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 574 };
 575
 576 static struct intc_desc intc_desc __initdata = {
 577         .name = "sh7722",
 578         .force_enable = ENABLED,
 579         .force_disable = DISABLED,
 580         .hw = INTC_HW_DESC(vectors, groups, mask_registers,
 581                            prio_registers, sense_registers, ack_registers),
 582 };
 583
 584 void __init plat_irq_setup(void)
 585 {
 586         register_intc_controller(&intc_desc);
 587 }
 588
 589 void __init plat_mem_setup(void)
 590 {
 591         /* Register the URAM space as Node 1 */
 592         setup_bootmem_node(1, 0x055f0000, 0x05610000);
 593 }