arch/sh/kernel/cpu/sh4a/clock-sh7786.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4a/clock-sh7786.c
   3  *
   4  * SH7786 support for the clock framework
   5  *
   6  *  Copyright (C) 2010  Paul Mundt
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/kernel.h>
  14 #include <linux/clk.h>
  15 #include <linux/io.h>
  16 #include <linux/clkdev.h>
  17 #include <asm/clock.h>
  18 #include <asm/freq.h>
  19
  20 /*
  21  * Default rate for the root input clock, reset this with clk_set_rate()
  22  * from the platform code.
  23  */
  24 static struct clk extal_clk = {
  25         .rate           = 33333333,
  26 };
  27
  28 static unsigned long pll_recalc(struct clk *clk)
  29 {
  30         int multiplier;
  31
  32         /*
  33          * Clock modes 0, 1, and 2 use an x64 multiplier against PLL1,
  34          * while modes 3, 4, and 5 use an x32.
  35          */
  36         multiplier = (sh_mv.mv_mode_pins() & 0xf) < 3 ? 64 : 32;
  37
  38         return clk->parent->rate * multiplier;
  39 }
  40
  41 static struct clk_ops pll_clk_ops = {
  42         .recalc         = pll_recalc,
  43 };
  44
  45 static struct clk pll_clk = {
  46         .ops            = &pll_clk_ops,
  47         .parent         = &extal_clk,
  48         .flags          = CLK_ENABLE_ON_INIT,
  49 };
  50
  51 static struct clk *clks[] = {
  52         &extal_clk,
  53         &pll_clk,
  54 };
  55
  56 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
  57                                24, 32, 36, 48 };
  58
  59 static struct clk_div_mult_table div4_div_mult_table = {
  60         .divisors = div2,
  61         .nr_divisors = ARRAY_SIZE(div2),
  62 };
  63
  64 static struct clk_div4_table div4_table = {
  65         .div_mult_table = &div4_div_mult_table,
  66 };
  67
  68 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
  69
  70 #define DIV4(_bit, _mask, _flags) \
  71   SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
  72
  73 struct clk div4_clks[DIV4_NR] = {
  74         [DIV4_P] = DIV4(0, 0x0b40, 0),
  75         [DIV4_DU] = DIV4(4, 0x0010, 0),
  76         [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
  77         [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
  78         [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
  79         [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
  80 };
  81
  82 #define MSTPCR0         0xffc40030
  83 #define MSTPCR1         0xffc40034
  84
  85 enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
  86        MSTP023, MSTP022, MSTP021, MSTP020, MSTP017, MSTP016,
  87        MSTP015, MSTP014, MSTP011, MSTP010, MSTP009, MSTP008,
  88        MSTP005, MSTP004, MSTP002,
  89        MSTP112, MSTP110, MSTP109, MSTP108,
  90        MSTP105, MSTP104, MSTP103, MSTP102,
  91        MSTP_NR };
  92
  93 static struct clk mstp_clks[MSTP_NR] = {
  94         /* MSTPCR0 */
  95         [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
  96         [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
  97         [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
  98         [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
  99         [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
 100         [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
 101         [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
 102         [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
 103         [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
 104         [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
 105         [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
 106         [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
 107         [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
 108         [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
 109         [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
 110         [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
 111         [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
 112         [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
 113         [MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
 114         [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
 115         [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
 116
 117         /* MSTPCR1 */
 118         [MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
 119         [MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
 120         [MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
 121         [MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
 122         [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
 123         [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
 124         [MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
 125         [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
 126 };
 127
 128 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
 129
 130 static struct clk_lookup lookups[] = {
 131         /* main clocks */
 132         CLKDEV_CON_ID("extal", &extal_clk),
 133         CLKDEV_CON_ID("pll_clk", &pll_clk),
 134
 135         /* DIV4 clocks */
 136         CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
 137         CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
 138         CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
 139         CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
 140         CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
 141         CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
 142
 143         /* MSTP32 clocks */
 144         {
 145                 /* SCIF5 */
 146                 .dev_id         = "sh-sci.5",
 147                 .con_id         = "sci_fck",
 148                 .clk            = &mstp_clks[MSTP029],
 149         }, {
 150                 /* SCIF4 */
 151                 .dev_id         = "sh-sci.4",
 152                 .con_id         = "sci_fck",
 153                 .clk            = &mstp_clks[MSTP028],
 154         }, {
 155                 /* SCIF3 */
 156                 .dev_id         = "sh-sci.3",
 157                 .con_id         = "sci_fck",
 158                 .clk            = &mstp_clks[MSTP027],
 159         }, {
 160                 /* SCIF2 */
 161                 .dev_id         = "sh-sci.2",
 162                 .con_id         = "sci_fck",
 163                 .clk            = &mstp_clks[MSTP026],
 164         }, {
 165                 /* SCIF1 */
 166                 .dev_id         = "sh-sci.1",
 167                 .con_id         = "sci_fck",
 168                 .clk            = &mstp_clks[MSTP025],
 169         }, {
 170                 /* SCIF0 */
 171                 .dev_id         = "sh-sci.0",
 172                 .con_id         = "sci_fck",
 173                 .clk            = &mstp_clks[MSTP024],
 174         },
 175         CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
 176         CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
 177         CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
 178         CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
 179         CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
 180         CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
 181         CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]),
 182         CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]),
 183         {
 184                 /* TMU0 */
 185                 .dev_id         = "sh_tmu.0",
 186                 .con_id         = "tmu_fck",
 187                 .clk            = &mstp_clks[MSTP008],
 188         }, {
 189                 /* TMU1 */
 190                 .dev_id         = "sh_tmu.1",
 191                 .con_id         = "tmu_fck",
 192                 .clk            = &mstp_clks[MSTP008],
 193         }, {
 194                 /* TMU2 */
 195                 .dev_id         = "sh_tmu.2",
 196                 .con_id         = "tmu_fck",
 197                 .clk            = &mstp_clks[MSTP008],
 198         }, {
 199                 /* TMU3 */
 200                 .dev_id         = "sh_tmu.3",
 201                 .con_id         = "tmu_fck",
 202                 .clk            = &mstp_clks[MSTP009],
 203         }, {
 204                 /* TMU4 */
 205                 .dev_id         = "sh_tmu.4",
 206                 .con_id         = "tmu_fck",
 207                 .clk            = &mstp_clks[MSTP009],
 208         }, {
 209                 /* TMU5 */
 210                 .dev_id         = "sh_tmu.5",
 211                 .con_id         = "tmu_fck",
 212                 .clk            = &mstp_clks[MSTP009],
 213         }, {
 214                 /* TMU6 */
 215                 .dev_id         = "sh_tmu.6",
 216                 .con_id         = "tmu_fck",
 217                 .clk            = &mstp_clks[MSTP010],
 218         }, {
 219                 /* TMU7 */
 220                 .dev_id         = "sh_tmu.7",
 221                 .con_id         = "tmu_fck",
 222                 .clk            = &mstp_clks[MSTP010],
 223         }, {
 224                 /* TMU8 */
 225                 .dev_id         = "sh_tmu.8",
 226                 .con_id         = "tmu_fck",
 227                 .clk            = &mstp_clks[MSTP010],
 228         }, {
 229                 /* TMU9 */
 230                 .dev_id         = "sh_tmu.9",
 231                 .con_id         = "tmu_fck",
 232                 .clk            = &mstp_clks[MSTP011],
 233         }, {
 234                 /* TMU10 */
 235                 .dev_id         = "sh_tmu.10",
 236                 .con_id         = "tmu_fck",
 237                 .clk            = &mstp_clks[MSTP011],
 238         }, {
 239                 /* TMU11 */
 240                 .dev_id         = "sh_tmu.11",
 241                 .con_id         = "tmu_fck",
 242                 .clk            = &mstp_clks[MSTP011],
 243         },
 244         CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]),
 245         CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]),
 246         CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
 247         CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP112]),
 248         CLKDEV_CON_ID("pcie2_fck", &mstp_clks[MSTP110]),
 249         CLKDEV_CON_ID("pcie1_fck", &mstp_clks[MSTP109]),
 250         CLKDEV_CON_ID("pcie0_fck", &mstp_clks[MSTP108]),
 251         CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
 252         CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
 253         CLKDEV_CON_ID("du_fck", &mstp_clks[MSTP103]),
 254         CLKDEV_CON_ID("ether_fck", &mstp_clks[MSTP102]),
 255 };
 256
 257 int __init arch_clk_init(void)
 258 {
 259         int i, ret = 0;
 260
 261         for (i = 0; i < ARRAY_SIZE(clks); i++)
 262                 ret |= clk_register(clks[i]);
 263         for (i = 0; i < ARRAY_SIZE(lookups); i++)
 264                 clkdev_add(&lookups[i]);
 265
 266         if (!ret)
 267                 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
 268                                            &div4_table);
 269         if (!ret)
 270                 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
 271
 272         return ret;
 273 }