arch/sh/kernel/cpu/sh4a/clock-sh7724.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4a/clock-sh7724.c
   3  *
   4  * SH7724 clock framework support
   5  *
   6  * Copyright (C) 2009 Magnus Damm
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <linux/clk.h>
  25 #include <asm/clkdev.h>
  26 #include <asm/clock.h>
  27 #include <asm/hwblk.h>
  28 #include <cpu/sh7724.h>
  29
  30 /* SH7724 registers */
  31 #define FRQCRA          0xa4150000
  32 #define FRQCRB          0xa4150004
  33 #define VCLKCR          0xa4150048
  34 #define FCLKACR         0xa4150008
  35 #define FCLKBCR         0xa415000c
  36 #define IRDACLKCR       0xa4150018
  37 #define PLLCR           0xa4150024
  38 #define SPUCLKCR        0xa415003c
  39 #define FLLFRQ          0xa4150050
  40 #define LSTATS          0xa4150060
  41
  42 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
  43 static struct clk r_clk = {
  44         .name           = "rclk",
  45         .id             = -1,
  46         .rate           = 32768,
  47 };
  48
  49 /*
  50  * Default rate for the root input clock, reset this with clk_set_rate()
  51  * from the platform code.
  52  */
  53 struct clk extal_clk = {
  54         .name           = "extal",
  55         .id             = -1,
  56         .rate           = 33333333,
  57 };
  58
  59 /* The fll multiplies the 32khz r_clk, may be used instead of extal */
  60 static unsigned long fll_recalc(struct clk *clk)
  61 {
  62         unsigned long mult = 0;
  63         unsigned long div = 1;
  64
  65         if (__raw_readl(PLLCR) & 0x1000)
  66                 mult = __raw_readl(FLLFRQ) & 0x3ff;
  67
  68         if (__raw_readl(FLLFRQ) & 0x4000)
  69                 div = 2;
  70
  71         return (clk->parent->rate * mult) / div;
  72 }
  73
  74 static struct clk_ops fll_clk_ops = {
  75         .recalc         = fll_recalc,
  76 };
  77
  78 static struct clk fll_clk = {
  79         .name           = "fll_clk",
  80         .id             = -1,
  81         .ops            = &fll_clk_ops,
  82         .parent         = &r_clk,
  83         .flags          = CLK_ENABLE_ON_INIT,
  84 };
  85
  86 static unsigned long pll_recalc(struct clk *clk)
  87 {
  88         unsigned long mult = 1;
  89
  90         if (__raw_readl(PLLCR) & 0x4000)
  91                 mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2;
  92
  93         return clk->parent->rate * mult;
  94 }
  95
  96 static struct clk_ops pll_clk_ops = {
  97         .recalc         = pll_recalc,
  98 };
  99
 100 static struct clk pll_clk = {
 101         .name           = "pll_clk",
 102         .id             = -1,
 103         .ops            = &pll_clk_ops,
 104         .flags          = CLK_ENABLE_ON_INIT,
 105 };
 106
 107 /* A fixed divide-by-3 block use by the div6 clocks */
 108 static unsigned long div3_recalc(struct clk *clk)
 109 {
 110         return clk->parent->rate / 3;
 111 }
 112
 113 static struct clk_ops div3_clk_ops = {
 114         .recalc         = div3_recalc,
 115 };
 116
 117 static struct clk div3_clk = {
 118         .name           = "div3_clk",
 119         .id             = -1,
 120         .ops            = &div3_clk_ops,
 121         .parent         = &pll_clk,
 122 };
 123
 124 struct clk *main_clks[] = {
 125         &r_clk,
 126         &extal_clk,
 127         &fll_clk,
 128         &pll_clk,
 129         &div3_clk,
 130 };
 131
 132 static void div4_kick(struct clk *clk)
 133 {
 134         unsigned long value;
 135
 136         /* set KICK bit in FRQCRA to update hardware setting */
 137         value = __raw_readl(FRQCRA);
 138         value |= (1 << 31);
 139         __raw_writel(value, FRQCRA);
 140 }
 141
 142 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
 143
 144 static struct clk_div_mult_table div4_div_mult_table = {
 145         .divisors = divisors,
 146         .nr_divisors = ARRAY_SIZE(divisors),
 147 };
 148
 149 static struct clk_div4_table div4_table = {
 150         .div_mult_table = &div4_div_mult_table,
 151         .kick = div4_kick,
 152 };
 153
 154 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
 155
 156 #define DIV4(_str, _reg, _bit, _mask, _flags) \
 157   SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
 158
 159 struct clk div4_clks[DIV4_NR] = {
 160         [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
 161         [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
 162         [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
 163         [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0),
 164         [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
 165 };
 166
 167 struct clk div6_clks[] = {
 168         SH_CLK_DIV6("video_clk", &div3_clk, VCLKCR, 0),
 169         SH_CLK_DIV6("fsia_clk", &div3_clk, FCLKACR, 0),
 170         SH_CLK_DIV6("fsib_clk", &div3_clk, FCLKBCR, 0),
 171         SH_CLK_DIV6("irda_clk", &div3_clk, IRDACLKCR, 0),
 172         SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
 173 };
 174
 175 #define R_CLK (&r_clk)
 176 #define P_CLK (&div4_clks[DIV4_P])
 177 #define B_CLK (&div4_clks[DIV4_B])
 178 #define I_CLK (&div4_clks[DIV4_I])
 179 #define SH_CLK (&div4_clks[DIV4_SH])
 180
 181 static struct clk mstp_clks[HWBLK_NR] = {
 182         SH_HWBLK_CLK("tlb0", -1, I_CLK, HWBLK_TLB, CLK_ENABLE_ON_INIT),
 183         SH_HWBLK_CLK("ic0", -1, I_CLK, HWBLK_IC, CLK_ENABLE_ON_INIT),
 184         SH_HWBLK_CLK("oc0", -1, I_CLK, HWBLK_OC, CLK_ENABLE_ON_INIT),
 185         SH_HWBLK_CLK("rs0", -1, B_CLK, HWBLK_RSMEM, CLK_ENABLE_ON_INIT),
 186         SH_HWBLK_CLK("ilmem0", -1, I_CLK, HWBLK_ILMEM, CLK_ENABLE_ON_INIT),
 187         SH_HWBLK_CLK("l2c0", -1, SH_CLK, HWBLK_L2C, CLK_ENABLE_ON_INIT),
 188         SH_HWBLK_CLK("fpu0", -1, I_CLK, HWBLK_FPU, CLK_ENABLE_ON_INIT),
 189         SH_HWBLK_CLK("intc0", -1, P_CLK, HWBLK_INTC, CLK_ENABLE_ON_INIT),
 190         SH_HWBLK_CLK("dmac0", -1, B_CLK, HWBLK_DMAC0, 0),
 191         SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT),
 192         SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0),
 193         SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0),
 194         SH_HWBLK_CLK("tmu012_fck", -1, P_CLK, HWBLK_TMU0, 0),
 195         SH_HWBLK_CLK("cmt_fck", -1, R_CLK, HWBLK_CMT, 0),
 196         SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
 197         SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0),
 198         SH_HWBLK_CLK("tmu345_fck", -1, P_CLK, HWBLK_TMU1, 0),
 199         SH_HWBLK_CLK("sci_fck", 0, P_CLK, HWBLK_SCIF0, 0),
 200         SH_HWBLK_CLK("sci_fck", 1, P_CLK, HWBLK_SCIF1, 0),
 201         SH_HWBLK_CLK("sci_fck", 2, P_CLK, HWBLK_SCIF2, 0),
 202         SH_HWBLK_CLK("sci_fck", 3, B_CLK, HWBLK_SCIF3, 0),
 203         SH_HWBLK_CLK("sci_fck", 4, B_CLK, HWBLK_SCIF4, 0),
 204         SH_HWBLK_CLK("sci_fck", 5, B_CLK, HWBLK_SCIF5, 0),
 205         SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0),
 206         SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0),
 207
 208         SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0),
 209         SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0),
 210         SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC0, 0),
 211         SH_HWBLK_CLK("i2c1", -1, P_CLK, HWBLK_IIC1, 0),
 212
 213         SH_HWBLK_CLK("mmc0", -1, B_CLK, HWBLK_MMC, 0),
 214         SH_HWBLK_CLK("eth0", -1, B_CLK, HWBLK_ETHER, 0),
 215         SH_HWBLK_CLK("atapi0", -1, B_CLK, HWBLK_ATAPI, 0),
 216         SH_HWBLK_CLK("tpu0", -1, B_CLK, HWBLK_TPU, 0),
 217         SH_HWBLK_CLK("irda0", -1, P_CLK, HWBLK_IRDA, 0),
 218         SH_HWBLK_CLK("tsif0", -1, B_CLK, HWBLK_TSIF, 0),
 219         SH_HWBLK_CLK("usb1", -1, B_CLK, HWBLK_USB1, 0),
 220         SH_HWBLK_CLK("usb0", -1, B_CLK, HWBLK_USB0, 0),
 221         SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0),
 222         SH_HWBLK_CLK("sdhi0", -1, B_CLK, HWBLK_SDHI0, 0),
 223         SH_HWBLK_CLK("sdhi1", -1, B_CLK, HWBLK_SDHI1, 0),
 224         SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU1, 0),
 225         SH_HWBLK_CLK("ceu1", -1, B_CLK, HWBLK_CEU1, 0),
 226         SH_HWBLK_CLK("beu1", -1, B_CLK, HWBLK_BEU1, 0),
 227         SH_HWBLK_CLK("2ddmac0", -1, SH_CLK, HWBLK_2DDMAC, 0),
 228         SH_HWBLK_CLK("spu0", -1, B_CLK, HWBLK_SPU, 0),
 229         SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, 0),
 230         SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0),
 231         SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU0, 0),
 232         SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU0, 0),
 233         SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU0, 0),
 234         SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0),
 235         SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0),
 236 };
 237
 238 static struct clk_lookup lookups[] = {
 239         {
 240                 /* TMU0 */
 241                 .dev_id         = "sh_tmu.0",
 242                 .con_id         = "tmu_fck",
 243                 .clk            = &mstp_clks[HWBLK_TMU0],
 244         }, {
 245                 /* TMU1 */
 246                 .dev_id         = "sh_tmu.1",
 247                 .con_id         = "tmu_fck",
 248                 .clk            = &mstp_clks[HWBLK_TMU0],
 249         }, {
 250                 /* TMU2 */
 251                 .dev_id         = "sh_tmu.2",
 252                 .con_id         = "tmu_fck",
 253                 .clk            = &mstp_clks[HWBLK_TMU0],
 254         }, {
 255                 /* TMU3 */
 256                 .dev_id         = "sh_tmu.3",
 257                 .con_id         = "tmu_fck",
 258                 .clk            = &mstp_clks[HWBLK_TMU1],
 259         }, {
 260                 /* TMU4 */
 261                 .dev_id         = "sh_tmu.4",
 262                 .con_id         = "tmu_fck",
 263                 .clk            = &mstp_clks[HWBLK_TMU1],
 264         }, {
 265                 /* TMU5 */
 266                 .dev_id         = "sh_tmu.5",
 267                 .con_id         = "tmu_fck",
 268                 .clk            = &mstp_clks[HWBLK_TMU1],
 269         },
 270 };
 271
 272 int __init arch_clk_init(void)
 273 {
 274         int k, ret = 0;
 275
 276         /* autodetect extal or fll configuration */
 277         if (__raw_readl(PLLCR) & 0x1000)
 278                 pll_clk.parent = &fll_clk;
 279         else
 280                 pll_clk.parent = &extal_clk;
 281
 282         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 283                 ret = clk_register(main_clks[k]);
 284
 285         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 286
 287         if (!ret)
 288                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 289
 290         if (!ret)
 291                 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
 292
 293         if (!ret)
 294                 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
 295
 296         return ret;
 297 }