arch/sh/kernel/cpu/sh4a/clock-sh7723.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4a/clock-sh7723.c
   3  *
   4  * SH7723 clock framework support
   5  *
   6  * Copyright (C) 2009 Magnus Damm
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <linux/clk.h>
  25 #include <asm/clkdev.h>
  26 #include <asm/clock.h>
  27 #include <asm/hwblk.h>
  28 #include <cpu/sh7723.h>
  29
  30 /* SH7723 registers */
  31 #define FRQCR           0xa4150000
  32 #define VCLKCR          0xa4150004
  33 #define SCLKACR         0xa4150008
  34 #define SCLKBCR         0xa415000c
  35 #define IRDACLKCR       0xa4150018
  36 #define PLLCR           0xa4150024
  37 #define DLLFRQ          0xa4150050
  38
  39 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
  40 static struct clk r_clk = {
  41         .name           = "rclk",
  42         .id             = -1,
  43         .rate           = 32768,
  44 };
  45
  46 /*
  47  * Default rate for the root input clock, reset this with clk_set_rate()
  48  * from the platform code.
  49  */
  50 struct clk extal_clk = {
  51         .name           = "extal",
  52         .id             = -1,
  53         .rate           = 33333333,
  54 };
  55
  56 /* The dll multiplies the 32khz r_clk, may be used instead of extal */
  57 static unsigned long dll_recalc(struct clk *clk)
  58 {
  59         unsigned long mult;
  60
  61         if (__raw_readl(PLLCR) & 0x1000)
  62                 mult = __raw_readl(DLLFRQ);
  63         else
  64                 mult = 0;
  65
  66         return clk->parent->rate * mult;
  67 }
  68
  69 static struct clk_ops dll_clk_ops = {
  70         .recalc         = dll_recalc,
  71 };
  72
  73 static struct clk dll_clk = {
  74         .name           = "dll_clk",
  75         .id             = -1,
  76         .ops            = &dll_clk_ops,
  77         .parent         = &r_clk,
  78         .flags          = CLK_ENABLE_ON_INIT,
  79 };
  80
  81 static unsigned long pll_recalc(struct clk *clk)
  82 {
  83         unsigned long mult = 1;
  84         unsigned long div = 1;
  85
  86         if (__raw_readl(PLLCR) & 0x4000)
  87                 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
  88         else
  89                 div = 2;
  90
  91         return (clk->parent->rate * mult) / div;
  92 }
  93
  94 static struct clk_ops pll_clk_ops = {
  95         .recalc         = pll_recalc,
  96 };
  97
  98 static struct clk pll_clk = {
  99         .name           = "pll_clk",
 100         .id             = -1,
 101         .ops            = &pll_clk_ops,
 102         .flags          = CLK_ENABLE_ON_INIT,
 103 };
 104
 105 struct clk *main_clks[] = {
 106         &r_clk,
 107         &extal_clk,
 108         &dll_clk,
 109         &pll_clk,
 110 };
 111
 112 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
 113 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
 114
 115 static struct clk_div_mult_table div4_div_mult_table = {
 116         .divisors = divisors,
 117         .nr_divisors = ARRAY_SIZE(divisors),
 118         .multipliers = multipliers,
 119         .nr_multipliers = ARRAY_SIZE(multipliers),
 120 };
 121
 122 static struct clk_div4_table div4_table = {
 123         .div_mult_table = &div4_div_mult_table,
 124 };
 125
 126 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
 127
 128 #define DIV4(_str, _reg, _bit, _mask, _flags) \
 129   SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
 130
 131 struct clk div4_clks[DIV4_NR] = {
 132         [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
 133         [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
 134         [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
 135         [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
 136         [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
 137         [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0),
 138 };
 139
 140 enum { DIV4_IRDA, DIV4_ENABLE_NR };
 141
 142 struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
 143         [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0),
 144 };
 145
 146 enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
 147
 148 struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
 149         [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0),
 150         [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0),
 151 };
 152 enum { DIV6_V, DIV6_NR };
 153
 154 struct clk div6_clks[DIV6_NR] = {
 155         [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
 156 };
 157
 158 static struct clk mstp_clks[] = {
 159         /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
 160         SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
 161         SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
 162         SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
 163         SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
 164         SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
 165         SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
 166         SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
 167         SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
 168         SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
 169         SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
 170         SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
 171         SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
 172         SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
 173         SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
 174         SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
 175         SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
 176         SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
 177         SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
 178         SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
 179         SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
 180         SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
 181         SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
 182         SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
 183         SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
 184         SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
 185         SH_HWBLK_CLK(HWBLK_MERAM, &div4_clks[DIV4_SH], 0),
 186
 187         SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
 188         SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
 189
 190         SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_SH], 0),
 191         SH_HWBLK_CLK(HWBLK_ADC, &div4_clks[DIV4_P], 0),
 192         SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
 193         SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
 194         SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
 195         SH_HWBLK_CLK(HWBLK_ICB, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
 196         SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
 197         SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
 198         SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
 199         SH_HWBLK_CLK(HWBLK_USB, &div4_clks[DIV4_B], 0),
 200         SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
 201         SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
 202         SH_HWBLK_CLK(HWBLK_VEU2H1, &div4_clks[DIV4_B], 0),
 203         SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
 204         SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
 205         SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
 206         SH_HWBLK_CLK(HWBLK_VEU2H0, &div4_clks[DIV4_B], 0),
 207         SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
 208         SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
 209 };
 210
 211 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
 212
 213 static struct clk_lookup lookups[] = {
 214         /* DIV4 clocks */
 215         CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
 216         CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
 217         CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
 218         CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
 219         CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
 220         CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
 221         CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
 222         CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
 223         CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
 224
 225         /* DIV6 clocks */
 226         CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
 227
 228         /* MSTP clocks */
 229         CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
 230         CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
 231         CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
 232         CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
 233         CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
 234         CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
 235         CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
 236         CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
 237         CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
 238         CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
 239         CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
 240         {
 241                 /* TMU0 */
 242                 .dev_id         = "sh_tmu.0",
 243                 .con_id         = "tmu_fck",
 244                 .clk            = &mstp_clks[HWBLK_TMU0],
 245         }, {
 246                 /* TMU1 */
 247                 .dev_id         = "sh_tmu.1",
 248                 .con_id         = "tmu_fck",
 249                 .clk            = &mstp_clks[HWBLK_TMU0],
 250         }, {
 251                 /* TMU2 */
 252                 .dev_id         = "sh_tmu.2",
 253                 .con_id         = "tmu_fck",
 254                 .clk            = &mstp_clks[HWBLK_TMU0],
 255         },
 256         CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
 257         CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
 258         CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
 259         {
 260                 /* TMU3 */
 261                 .dev_id         = "sh_tmu.3",
 262                 .con_id         = "tmu_fck",
 263                 .clk            = &mstp_clks[HWBLK_TMU1],
 264         }, {
 265                 /* TMU4 */
 266                 .dev_id         = "sh_tmu.4",
 267                 .con_id         = "tmu_fck",
 268                 .clk            = &mstp_clks[HWBLK_TMU1],
 269         }, {
 270                 /* TMU5 */
 271                 .dev_id         = "sh_tmu.5",
 272                 .con_id         = "tmu_fck",
 273                 .clk            = &mstp_clks[HWBLK_TMU1],
 274         },
 275         CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
 276         {
 277                 /* SCIF0 */
 278                 .dev_id         = "sh-sci.0",
 279                 .con_id         = "sci_fck",
 280                 .clk            = &mstp_clks[HWBLK_SCIF0],
 281         }, {
 282                 /* SCIF1 */
 283                 .dev_id         = "sh-sci.1",
 284                 .con_id         = "sci_fck",
 285                 .clk            = &mstp_clks[HWBLK_SCIF1],
 286         }, {
 287                 /* SCIF2 */
 288                 .dev_id         = "sh-sci.2",
 289                 .con_id         = "sci_fck",
 290                 .clk            = &mstp_clks[HWBLK_SCIF2],
 291         }, {
 292                 /* SCIF3 */
 293                 .dev_id         = "sh-sci.3",
 294                 .con_id         = "sci_fck",
 295                 .clk            = &mstp_clks[HWBLK_SCIF3],
 296         }, {
 297                 /* SCIF4 */
 298                 .dev_id         = "sh-sci.4",
 299                 .con_id         = "sci_fck",
 300                 .clk            = &mstp_clks[HWBLK_SCIF4],
 301         }, {
 302                 /* SCIF5 */
 303                 .dev_id         = "sh-sci.5",
 304                 .con_id         = "sci_fck",
 305                 .clk            = &mstp_clks[HWBLK_SCIF5],
 306         },
 307         CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
 308         CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
 309         CLKDEV_CON_ID("meram0", &mstp_clks[HWBLK_MERAM]),
 310         CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
 311         CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
 312         CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
 313         CLKDEV_CON_ID("adc0", &mstp_clks[HWBLK_ADC]),
 314         CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
 315         CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
 316         CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
 317         CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]),
 318         CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]),
 319         CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]),
 320         CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
 321         CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]),
 322         CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
 323         CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
 324         CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]),
 325         CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
 326         CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
 327         CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
 328         CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]),
 329         CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
 330         CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
 331 };
 332
 333 int __init arch_clk_init(void)
 334 {
 335         int k, ret = 0;
 336
 337         /* autodetect extal or dll configuration */
 338         if (__raw_readl(PLLCR) & 0x1000)
 339                 pll_clk.parent = &dll_clk;
 340         else
 341                 pll_clk.parent = &extal_clk;
 342
 343         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 344                 ret |= clk_register(main_clks[k]);
 345
 346         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 347
 348         if (!ret)
 349                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 350
 351         if (!ret)
 352                 ret = sh_clk_div4_enable_register(div4_enable_clks,
 353                                         DIV4_ENABLE_NR, &div4_table);
 354
 355         if (!ret)
 356                 ret = sh_clk_div4_reparent_register(div4_reparent_clks,
 357                                         DIV4_REPARENT_NR, &div4_table);
 358
 359         if (!ret)
 360                 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 361
 362         if (!ret)
 363                 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
 364
 365         return ret;
 366 }