4 * Copyright (C) 2006 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/sh_timer.h>
14 #include <linux/serial_sci.h>
20 /* interrupt sources */
21 IRL0, IRL1, IRL2, IRL3,
23 DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
24 DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
26 IRQ4, IRQ5, IRQ6, IRQ7,
32 DMABRG0, DMABRG1, DMABRG2,
33 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
34 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
35 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
36 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
38 MMCIF0, MMCIF1, MMCIF2, MMCIF3,
40 TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
44 /* interrupt groups */
45 DMAC, DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF, TMU2, REF,
48 static struct intc_vect vectors[] __initdata = {
49 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
50 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
51 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
52 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
53 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
54 INTC_VECT(DMAC_DMAE, 0x6c0),
55 INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
56 INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
57 INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
58 INTC_VECT(SSI0, 0x940), INTC_VECT(SSI1, 0x960),
59 INTC_VECT(HAC0, 0x980), INTC_VECT(HAC1, 0x9a0),
60 INTC_VECT(I2C0, 0x9c0), INTC_VECT(I2C1, 0x9e0),
61 INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),
62 INTC_VECT(DMABRG0, 0xa80), INTC_VECT(DMABRG1, 0xaa0),
63 INTC_VECT(DMABRG2, 0xac0),
64 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
65 INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
66 INTC_VECT(SCIF1_ERI, 0xb00), INTC_VECT(SCIF1_RXI, 0xb20),
67 INTC_VECT(SCIF1_BRI, 0xb40), INTC_VECT(SCIF1_TXI, 0xb60),
68 INTC_VECT(SCIF2_ERI, 0xb80), INTC_VECT(SCIF2_RXI, 0xba0),
69 INTC_VECT(SCIF2_BRI, 0xbc0), INTC_VECT(SCIF2_TXI, 0xbe0),
70 INTC_VECT(SIM_ERI, 0xc00), INTC_VECT(SIM_RXI, 0xc20),
71 INTC_VECT(SIM_TXI, 0xc40), INTC_VECT(SIM_TEI, 0xc60),
72 INTC_VECT(HSPI, 0xc80),
73 INTC_VECT(MMCIF0, 0xd00), INTC_VECT(MMCIF1, 0xd20),
74 INTC_VECT(MMCIF2, 0xd40), INTC_VECT(MMCIF3, 0xd60),
75 INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */
76 INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0),
77 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
78 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
79 INTC_VECT(WDT, 0x560),
80 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
83 static struct intc_group groups[] __initdata = {
84 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
85 DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
86 DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
87 INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2),
88 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
89 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
90 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
91 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
92 INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3),
93 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
94 INTC_GROUP(REF, REF_RCMI, REF_ROVI),
97 static struct intc_mask_reg mask_registers[] __initdata = {
98 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
99 { IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21,
100 SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
101 0, DMABRG0, DMABRG1, DMABRG2,
102 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
103 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
104 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, } },
105 { 0xfe080044, 0xfe080064, 32, /* INTMSK04 / INTMSKCLR04 */
106 { 0, 0, 0, 0, 0, 0, 0, 0,
107 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
108 HSPI, MMCIF0, MMCIF1, MMCIF2,
109 MMCIF3, 0, 0, 0, 0, 0, 0, 0,
110 0, MFI, 0, 0, 0, 0, ADC, CMT, } },
113 static struct intc_prio_reg prio_registers[] __initdata = {
114 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
115 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
116 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } },
117 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
118 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
119 { 0xfe080004, 0, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1,
120 HAC0, HAC1, I2C0, I2C1 } },
121 { 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,
122 SCIF1, SCIF2, SIM, HSPI } },
123 { 0xfe08000c, 0, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0,
124 MFI, 0, ADC, CMT } },
127 static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups,
128 mask_registers, prio_registers, NULL);
130 static struct intc_vect vectors_irq[] __initdata = {
131 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
132 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
135 static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
136 mask_registers, prio_registers, NULL);
138 static struct plat_sci_port sci_platform_data[] = {
140 .mapbase = 0xfe600000,
141 .flags = UPF_BOOT_AUTOCONF,
143 .irqs = { 52, 53, 55, 54 },
145 .mapbase = 0xfe610000,
146 .flags = UPF_BOOT_AUTOCONF,
148 .irqs = { 72, 73, 75, 74 },
150 .mapbase = 0xfe620000,
151 .flags = UPF_BOOT_AUTOCONF,
153 .irqs = { 76, 77, 79, 78 },
155 .mapbase = 0xfe480000,
156 .flags = UPF_BOOT_AUTOCONF,
158 .irqs = { 80, 81, 82, 0 },
164 static struct platform_device sci_device = {
168 .platform_data = sci_platform_data,
172 static struct sh_timer_config tmu0_platform_data = {
174 .channel_offset = 0x04,
177 .clockevent_rating = 200,
180 static struct resource tmu0_resources[] = {
185 .flags = IORESOURCE_MEM,
189 .flags = IORESOURCE_IRQ,
193 static struct platform_device tmu0_device = {
197 .platform_data = &tmu0_platform_data,
199 .resource = tmu0_resources,
200 .num_resources = ARRAY_SIZE(tmu0_resources),
203 static struct sh_timer_config tmu1_platform_data = {
205 .channel_offset = 0x10,
208 .clocksource_rating = 200,
211 static struct resource tmu1_resources[] = {
216 .flags = IORESOURCE_MEM,
220 .flags = IORESOURCE_IRQ,
224 static struct platform_device tmu1_device = {
228 .platform_data = &tmu1_platform_data,
230 .resource = tmu1_resources,
231 .num_resources = ARRAY_SIZE(tmu1_resources),
234 static struct sh_timer_config tmu2_platform_data = {
236 .channel_offset = 0x1c,
241 static struct resource tmu2_resources[] = {
246 .flags = IORESOURCE_MEM,
250 .flags = IORESOURCE_IRQ,
254 static struct platform_device tmu2_device = {
258 .platform_data = &tmu2_platform_data,
260 .resource = tmu2_resources,
261 .num_resources = ARRAY_SIZE(tmu2_resources),
265 static struct platform_device *sh7760_devices[] __initdata = {
272 static int __init sh7760_devices_setup(void)
274 return platform_add_devices(sh7760_devices,
275 ARRAY_SIZE(sh7760_devices));
277 __initcall(sh7760_devices_setup);
279 static struct platform_device *sh7760_early_devices[] __initdata = {
285 void __init plat_early_device_setup(void)
287 early_platform_add_devices(sh7760_early_devices,
288 ARRAY_SIZE(sh7760_early_devices));
291 #define INTC_ICR 0xffd00000UL
292 #define INTC_ICR_IRLM (1 << 7)
294 void __init plat_irq_setup_pins(int mode)
298 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
299 register_intc_controller(&intc_desc_irq);
306 void __init plat_irq_setup(void)
308 register_intc_controller(&intc_desc);