arch/sh/kernel/cpu/sh4/setup-sh7750.c

   1 /*
   2  * SH7750/SH7751 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *  Copyright (C) 2006  Jamie Lenehan
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #include <linux/platform_device.h>
  12 #include <linux/init.h>
  13 #include <linux/serial.h>
  14 #include <linux/io.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/serial_sci.h>
  17
  18 static struct resource rtc_resources[] = {
  19         [0] = {
  20                 .start  = 0xffc80000,
  21                 .end    = 0xffc80000 + 0x58 - 1,
  22                 .flags  = IORESOURCE_IO,
  23         },
  24         [1] = {
  25                 /* Shared Period/Carry/Alarm IRQ */
  26                 .start  = 20,
  27                 .flags  = IORESOURCE_IRQ,
  28         },
  29 };
  30
  31 static struct platform_device rtc_device = {
  32         .name           = "sh-rtc",
  33         .id             = -1,
  34         .num_resources  = ARRAY_SIZE(rtc_resources),
  35         .resource       = rtc_resources,
  36 };
  37
  38 static struct plat_sci_port scif0_platform_data = {
  39         .mapbase        = 0xffe00000,
  40         .flags          = UPF_BOOT_AUTOCONF,
  41         .type           = PORT_SCI,
  42         .irqs           = { 23, 23, 23, 0 },
  43 };
  44
  45 static struct platform_device scif0_device = {
  46         .name           = "sh-sci",
  47         .id             = 0,
  48         .dev            = {
  49                 .platform_data  = &scif0_platform_data,
  50         },
  51 };
  52
  53 static struct plat_sci_port scif1_platform_data = {
  54         .mapbase        = 0xffe80000,
  55         .flags          = UPF_BOOT_AUTOCONF,
  56         .type           = PORT_SCIF,
  57         .irqs           = { 40, 40, 40, 40 },
  58 };
  59
  60 static struct platform_device scif1_device = {
  61         .name           = "sh-sci",
  62         .id             = 1,
  63         .dev            = {
  64                 .platform_data  = &scif1_platform_data,
  65         },
  66 };
  67
  68 static struct sh_timer_config tmu0_platform_data = {
  69         .channel_offset = 0x04,
  70         .timer_bit = 0,
  71         .clk = "peripheral_clk",
  72         .clockevent_rating = 200,
  73 };
  74
  75 static struct resource tmu0_resources[] = {
  76         [0] = {
  77                 .start  = 0xffd80008,
  78                 .end    = 0xffd80013,
  79                 .flags  = IORESOURCE_MEM,
  80         },
  81         [1] = {
  82                 .start  = 16,
  83                 .flags  = IORESOURCE_IRQ,
  84         },
  85 };
  86
  87 static struct platform_device tmu0_device = {
  88         .name           = "sh_tmu",
  89         .id             = 0,
  90         .dev = {
  91                 .platform_data  = &tmu0_platform_data,
  92         },
  93         .resource       = tmu0_resources,
  94         .num_resources  = ARRAY_SIZE(tmu0_resources),
  95 };
  96
  97 static struct sh_timer_config tmu1_platform_data = {
  98         .channel_offset = 0x10,
  99         .timer_bit = 1,
 100         .clk = "peripheral_clk",
 101         .clocksource_rating = 200,
 102 };
 103
 104 static struct resource tmu1_resources[] = {
 105         [0] = {
 106                 .start  = 0xffd80014,
 107                 .end    = 0xffd8001f,
 108                 .flags  = IORESOURCE_MEM,
 109         },
 110         [1] = {
 111                 .start  = 17,
 112                 .flags  = IORESOURCE_IRQ,
 113         },
 114 };
 115
 116 static struct platform_device tmu1_device = {
 117         .name           = "sh_tmu",
 118         .id             = 1,
 119         .dev = {
 120                 .platform_data  = &tmu1_platform_data,
 121         },
 122         .resource       = tmu1_resources,
 123         .num_resources  = ARRAY_SIZE(tmu1_resources),
 124 };
 125
 126 static struct sh_timer_config tmu2_platform_data = {
 127         .channel_offset = 0x1c,
 128         .timer_bit = 2,
 129         .clk = "peripheral_clk",
 130 };
 131
 132 static struct resource tmu2_resources[] = {
 133         [0] = {
 134                 .start  = 0xffd80020,
 135                 .end    = 0xffd8002f,
 136                 .flags  = IORESOURCE_MEM,
 137         },
 138         [1] = {
 139                 .start  = 18,
 140                 .flags  = IORESOURCE_IRQ,
 141         },
 142 };
 143
 144 static struct platform_device tmu2_device = {
 145         .name           = "sh_tmu",
 146         .id             = 2,
 147         .dev = {
 148                 .platform_data  = &tmu2_platform_data,
 149         },
 150         .resource       = tmu2_resources,
 151         .num_resources  = ARRAY_SIZE(tmu2_resources),
 152 };
 153
 154 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
 155 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 156         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 157         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 158
 159 static struct sh_timer_config tmu3_platform_data = {
 160         .channel_offset = 0x04,
 161         .timer_bit = 0,
 162         .clk = "peripheral_clk",
 163 };
 164
 165 static struct resource tmu3_resources[] = {
 166         [0] = {
 167                 .start  = 0xfe100008,
 168                 .end    = 0xfe100013,
 169                 .flags  = IORESOURCE_MEM,
 170         },
 171         [1] = {
 172                 .start  = 72,
 173                 .flags  = IORESOURCE_IRQ,
 174         },
 175 };
 176
 177 static struct platform_device tmu3_device = {
 178         .name           = "sh_tmu",
 179         .id             = 3,
 180         .dev = {
 181                 .platform_data  = &tmu3_platform_data,
 182         },
 183         .resource       = tmu3_resources,
 184         .num_resources  = ARRAY_SIZE(tmu3_resources),
 185 };
 186
 187 static struct sh_timer_config tmu4_platform_data = {
 188         .channel_offset = 0x10,
 189         .timer_bit = 1,
 190         .clk = "peripheral_clk",
 191 };
 192
 193 static struct resource tmu4_resources[] = {
 194         [0] = {
 195                 .start  = 0xfe100014,
 196                 .end    = 0xfe10001f,
 197                 .flags  = IORESOURCE_MEM,
 198         },
 199         [1] = {
 200                 .start  = 76,
 201                 .flags  = IORESOURCE_IRQ,
 202         },
 203 };
 204
 205 static struct platform_device tmu4_device = {
 206         .name           = "sh_tmu",
 207         .id             = 4,
 208         .dev = {
 209                 .platform_data  = &tmu4_platform_data,
 210         },
 211         .resource       = tmu4_resources,
 212         .num_resources  = ARRAY_SIZE(tmu4_resources),
 213 };
 214
 215 #endif
 216
 217 static struct platform_device *sh7750_devices[] __initdata = {
 218         &scif0_device,
 219         &scif1_device,
 220         &rtc_device,
 221         &tmu0_device,
 222         &tmu1_device,
 223         &tmu2_device,
 224 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 225         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 226         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 227         &tmu3_device,
 228         &tmu4_device,
 229 #endif
 230 };
 231
 232 static int __init sh7750_devices_setup(void)
 233 {
 234         return platform_add_devices(sh7750_devices,
 235                                     ARRAY_SIZE(sh7750_devices));
 236 }
 237 arch_initcall(sh7750_devices_setup);
 238
 239 static struct platform_device *sh7750_early_devices[] __initdata = {
 240         &scif0_device,
 241         &scif1_device,
 242         &tmu0_device,
 243         &tmu1_device,
 244         &tmu2_device,
 245 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 246         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 247         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 248         &tmu3_device,
 249         &tmu4_device,
 250 #endif
 251 };
 252
 253 void __init plat_early_device_setup(void)
 254 {
 255         early_platform_add_devices(sh7750_early_devices,
 256                                    ARRAY_SIZE(sh7750_early_devices));
 257 }
 258
 259 enum {
 260         UNUSED = 0,
 261
 262         /* interrupt sources */
 263         IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
 264         HUDI, GPIOI, DMAC,
 265         PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 266         PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
 267         TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
 268
 269         /* interrupt groups */
 270         PCIC1,
 271 };
 272
 273 static struct intc_vect vectors[] __initdata = {
 274         INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
 275         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 276         INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
 277         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
 278         INTC_VECT(RTC, 0x4c0),
 279         INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
 280         INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
 281         INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
 282         INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
 283         INTC_VECT(WDT, 0x560),
 284         INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
 285 };
 286
 287 static struct intc_prio_reg prio_registers[] __initdata = {
 288         { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
 289         { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
 290         { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
 291         { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
 292         { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
 293                                                  TMU4, TMU3,
 294                                                  PCIC1, PCIC0_PCISERR } },
 295 };
 296
 297 static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
 298                          NULL, prio_registers, NULL);
 299
 300 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
 301 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
 302         defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 303         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 304         defined(CONFIG_CPU_SUBTYPE_SH7091)
 305 static struct intc_vect vectors_dma4[] __initdata = {
 306         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 307         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 308         INTC_VECT(DMAC, 0x6c0),
 309 };
 310
 311 static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
 312                          vectors_dma4, NULL,
 313                          NULL, prio_registers, NULL);
 314 #endif
 315
 316 /* SH7750R and SH7751R both have 8-channel DMA controllers */
 317 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
 318 static struct intc_vect vectors_dma8[] __initdata = {
 319         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 320         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 321         INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
 322         INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
 323         INTC_VECT(DMAC, 0x6c0),
 324 };
 325
 326 static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
 327                          vectors_dma8, NULL,
 328                          NULL, prio_registers, NULL);
 329 #endif
 330
 331 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
 332 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 333         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 334         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 335 static struct intc_vect vectors_tmu34[] __initdata = {
 336         INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
 337 };
 338
 339 static struct intc_mask_reg mask_registers[] __initdata = {
 340         { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
 341           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 342             0, 0, 0, 0, 0, 0, TMU4, TMU3,
 343             PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 344             PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
 345             PCIC1_PCIDMA3, PCIC0_PCISERR } },
 346 };
 347
 348 static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
 349                          vectors_tmu34, NULL,
 350                          mask_registers, prio_registers, NULL);
 351 #endif
 352
 353 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
 354 static struct intc_vect vectors_irlm[] __initdata = {
 355         INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
 356         INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
 357 };
 358
 359 static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
 360                          NULL, prio_registers, NULL);
 361
 362 /* SH7751 and SH7751R both have PCI */
 363 #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
 364 static struct intc_vect vectors_pci[] __initdata = {
 365         INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
 366         INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
 367         INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
 368         INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
 369 };
 370
 371 static struct intc_group groups_pci[] __initdata = {
 372         INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 373                    PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
 374 };
 375
 376 static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
 377                          mask_registers, prio_registers, NULL);
 378 #endif
 379
 380 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
 381         defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 382         defined(CONFIG_CPU_SUBTYPE_SH7091)
 383 void __init plat_irq_setup(void)
 384 {
 385         /*
 386          * same vectors for SH7750, SH7750S and SH7091 except for IRLM,
 387          * see below..
 388          */
 389         register_intc_controller(&intc_desc);
 390         register_intc_controller(&intc_desc_dma4);
 391 }
 392 #endif
 393
 394 #if defined(CONFIG_CPU_SUBTYPE_SH7750R)
 395 void __init plat_irq_setup(void)
 396 {
 397         register_intc_controller(&intc_desc);
 398         register_intc_controller(&intc_desc_dma8);
 399         register_intc_controller(&intc_desc_tmu34);
 400 }
 401 #endif
 402
 403 #if defined(CONFIG_CPU_SUBTYPE_SH7751)
 404 void __init plat_irq_setup(void)
 405 {
 406         register_intc_controller(&intc_desc);
 407         register_intc_controller(&intc_desc_dma4);
 408         register_intc_controller(&intc_desc_tmu34);
 409         register_intc_controller(&intc_desc_pci);
 410 }
 411 #endif
 412
 413 #if defined(CONFIG_CPU_SUBTYPE_SH7751R)
 414 void __init plat_irq_setup(void)
 415 {
 416         register_intc_controller(&intc_desc);
 417         register_intc_controller(&intc_desc_dma8);
 418         register_intc_controller(&intc_desc_tmu34);
 419         register_intc_controller(&intc_desc_pci);
 420 }
 421 #endif
 422
 423 #define INTC_ICR        0xffd00000UL
 424 #define INTC_ICR_IRLM   (1<<7)
 425
 426 void __init plat_irq_setup_pins(int mode)
 427 {
 428 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
 429         BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
 430         return;
 431 #endif
 432
 433         switch (mode) {
 434         case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
 435                 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
 436                 register_intc_controller(&intc_desc_irlm);
 437                 break;
 438         default:
 439                 BUG();
 440         }
 441 }