4 * Copyright (C) 2006 Paul Mundt
5 * Copyright (C) 2006 Jamie Lenehan
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/platform_device.h>
12 #include <linux/init.h>
13 #include <linux/serial.h>
15 #include <linux/sh_timer.h>
16 #include <linux/serial_sci.h>
17 #include <asm/machtypes.h>
19 static struct resource rtc_resources[] = {
22 .end = 0xffc80000 + 0x58 - 1,
23 .flags = IORESOURCE_IO,
26 /* Shared Period/Carry/Alarm IRQ */
28 .flags = IORESOURCE_IRQ,
32 static struct platform_device rtc_device = {
35 .num_resources = ARRAY_SIZE(rtc_resources),
36 .resource = rtc_resources,
39 static struct plat_sci_port sci_platform_data = {
40 .mapbase = 0xffe00000,
41 .flags = UPF_BOOT_AUTOCONF,
43 .scscr = SCSCR_TE | SCSCR_RE,
44 .scbrr_algo_id = SCBRR_ALGO_2,
45 .irqs = { 23, 23, 23, 0 },
48 static struct platform_device sci_device = {
51 .platform_data = sci_platform_data,
55 static struct plat_sci_port scif_platform_data = {
56 .mapbase = 0xffe80000,
57 .flags = UPF_BOOT_AUTOCONF,
58 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
59 .scbrr_algo_id = SCBRR_ALGO_2,
61 .irqs = { 40, 40, 40, 40 },
64 static struct platform_device scif_device = {
67 .platform_data = scif_platform_data,
71 static struct sh_timer_config tmu0_platform_data = {
73 .channel_offset = 0x04,
75 .clk = "peripheral_clk",
76 .clockevent_rating = 200,
79 static struct resource tmu0_resources[] = {
84 .flags = IORESOURCE_MEM,
88 .flags = IORESOURCE_IRQ,
92 static struct platform_device tmu0_device = {
96 .platform_data = &tmu0_platform_data,
98 .resource = tmu0_resources,
99 .num_resources = ARRAY_SIZE(tmu0_resources),
102 static struct sh_timer_config tmu1_platform_data = {
104 .channel_offset = 0x10,
106 .clk = "peripheral_clk",
107 .clocksource_rating = 200,
110 static struct resource tmu1_resources[] = {
115 .flags = IORESOURCE_MEM,
119 .flags = IORESOURCE_IRQ,
123 static struct platform_device tmu1_device = {
127 .platform_data = &tmu1_platform_data,
129 .resource = tmu1_resources,
130 .num_resources = ARRAY_SIZE(tmu1_resources),
133 static struct sh_timer_config tmu2_platform_data = {
135 .channel_offset = 0x1c,
137 .clk = "peripheral_clk",
140 static struct resource tmu2_resources[] = {
145 .flags = IORESOURCE_MEM,
149 .flags = IORESOURCE_IRQ,
153 static struct platform_device tmu2_device = {
157 .platform_data = &tmu2_platform_data,
159 .resource = tmu2_resources,
160 .num_resources = ARRAY_SIZE(tmu2_resources),
163 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
164 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
165 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
166 defined(CONFIG_CPU_SUBTYPE_SH7751R)
168 static struct sh_timer_config tmu3_platform_data = {
170 .channel_offset = 0x04,
172 .clk = "peripheral_clk",
175 static struct resource tmu3_resources[] = {
180 .flags = IORESOURCE_MEM,
184 .flags = IORESOURCE_IRQ,
188 static struct platform_device tmu3_device = {
192 .platform_data = &tmu3_platform_data,
194 .resource = tmu3_resources,
195 .num_resources = ARRAY_SIZE(tmu3_resources),
198 static struct sh_timer_config tmu4_platform_data = {
200 .channel_offset = 0x10,
202 .clk = "peripheral_clk",
205 static struct resource tmu4_resources[] = {
210 .flags = IORESOURCE_MEM,
214 .flags = IORESOURCE_IRQ,
218 static struct platform_device tmu4_device = {
222 .platform_data = &tmu4_platform_data,
224 .resource = tmu4_resources,
225 .num_resources = ARRAY_SIZE(tmu4_resources),
230 static struct platform_device *sh7750_devices[] __initdata = {
235 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
236 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
237 defined(CONFIG_CPU_SUBTYPE_SH7751R)
243 static int __init sh7750_devices_setup(void)
245 if (mach_is_rts7751r2d()) {
246 scif_platform_data.scscr |= SCSCR_CKE1;
247 platform_register_device(&scif_device);
249 platform_register_device(&sci_device);
250 platform_register_device(&scif_device);
253 return platform_add_devices(sh7750_devices,
254 ARRAY_SIZE(sh7750_devices));
256 __initcall(sh7750_devices_setup);
258 static struct platform_device *sh7750_early_devices[] __initdata = {
262 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
263 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
264 defined(CONFIG_CPU_SUBTYPE_SH7751R)
270 void __init plat_early_device_setup(void)
272 early_platform_add_devices(sh7750_early_devices,
273 ARRAY_SIZE(sh7750_early_devices));
279 /* interrupt sources */
280 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
282 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
283 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
284 TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
286 /* interrupt groups */
290 static struct intc_vect vectors[] __initdata = {
291 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
292 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
293 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
294 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
295 INTC_VECT(RTC, 0x4c0),
296 INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
297 INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
298 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
299 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
300 INTC_VECT(WDT, 0x560),
301 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
304 static struct intc_prio_reg prio_registers[] __initdata = {
305 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
306 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
307 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
308 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
309 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
311 PCIC1, PCIC0_PCISERR } },
314 static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
315 NULL, prio_registers, NULL);
317 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
318 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
319 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
320 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
321 defined(CONFIG_CPU_SUBTYPE_SH7091)
322 static struct intc_vect vectors_dma4[] __initdata = {
323 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
324 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
325 INTC_VECT(DMAC, 0x6c0),
328 static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
330 NULL, prio_registers, NULL);
333 /* SH7750R and SH7751R both have 8-channel DMA controllers */
334 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
335 static struct intc_vect vectors_dma8[] __initdata = {
336 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
337 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
338 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
339 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
340 INTC_VECT(DMAC, 0x6c0),
343 static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
345 NULL, prio_registers, NULL);
348 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
349 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
350 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
351 defined(CONFIG_CPU_SUBTYPE_SH7751R)
352 static struct intc_vect vectors_tmu34[] __initdata = {
353 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
356 static struct intc_mask_reg mask_registers[] __initdata = {
357 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
358 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
359 0, 0, 0, 0, 0, 0, TMU4, TMU3,
360 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
361 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
362 PCIC1_PCIDMA3, PCIC0_PCISERR } },
365 static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
367 mask_registers, prio_registers, NULL);
370 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
371 static struct intc_vect vectors_irlm[] __initdata = {
372 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
373 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
376 static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
377 NULL, prio_registers, NULL);
379 /* SH7751 and SH7751R both have PCI */
380 #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
381 static struct intc_vect vectors_pci[] __initdata = {
382 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
383 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
384 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
385 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
388 static struct intc_group groups_pci[] __initdata = {
389 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
390 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
393 static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
394 mask_registers, prio_registers, NULL);
397 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
398 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
399 defined(CONFIG_CPU_SUBTYPE_SH7091)
400 void __init plat_irq_setup(void)
403 * same vectors for SH7750, SH7750S and SH7091 except for IRLM,
406 register_intc_controller(&intc_desc);
407 register_intc_controller(&intc_desc_dma4);
411 #if defined(CONFIG_CPU_SUBTYPE_SH7750R)
412 void __init plat_irq_setup(void)
414 register_intc_controller(&intc_desc);
415 register_intc_controller(&intc_desc_dma8);
416 register_intc_controller(&intc_desc_tmu34);
420 #if defined(CONFIG_CPU_SUBTYPE_SH7751)
421 void __init plat_irq_setup(void)
423 register_intc_controller(&intc_desc);
424 register_intc_controller(&intc_desc_dma4);
425 register_intc_controller(&intc_desc_tmu34);
426 register_intc_controller(&intc_desc_pci);
430 #if defined(CONFIG_CPU_SUBTYPE_SH7751R)
431 void __init plat_irq_setup(void)
433 register_intc_controller(&intc_desc);
434 register_intc_controller(&intc_desc_dma8);
435 register_intc_controller(&intc_desc_tmu34);
436 register_intc_controller(&intc_desc_pci);
440 #define INTC_ICR 0xffd00000UL
441 #define INTC_ICR_IRLM (1<<7)
443 void __init plat_irq_setup_pins(int mode)
445 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
446 BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
451 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
452 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
453 register_intc_controller(&intc_desc_irlm);