arch/sh/include/cpu-sh4/cpu/dma-sh4a.h

   1 #ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
   2 #define __ASM_SH_CPU_SH4_DMA_SH7780_H
   3
   4 #if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
   5         defined(CONFIG_CPU_SUBTYPE_SH7730)
   6 #define DMTE0_IRQ       48
   7 #define DMTE4_IRQ       76
   8 #define DMAE0_IRQ       78      /* DMA Error IRQ*/
   9 #define SH_DMAC_BASE0   0xFE008020
  10 #define SH_DMARS_BASE0  0xFE009000
  11 #define CHCR_TS_LOW_MASK        0x00000018
  12 #define CHCR_TS_LOW_SHIFT       3
  13 #define CHCR_TS_HIGH_MASK       0
  14 #define CHCR_TS_HIGH_SHIFT      0
  15 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
  16 #define DMTE0_IRQ       48
  17 #define DMTE4_IRQ       76
  18 #define DMAE0_IRQ       78      /* DMA Error IRQ*/
  19 #define SH_DMAC_BASE0   0xFE008020
  20 #define SH_DMARS_BASE0  0xFE009000
  21 #define CHCR_TS_LOW_MASK        0x00000018
  22 #define CHCR_TS_LOW_SHIFT       3
  23 #define CHCR_TS_HIGH_MASK       0x00300000
  24 #define CHCR_TS_HIGH_SHIFT      20
  25 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
  26         defined(CONFIG_CPU_SUBTYPE_SH7764)
  27 #define DMTE0_IRQ       34
  28 #define DMTE4_IRQ       44
  29 #define DMAE0_IRQ       38
  30 #define SH_DMAC_BASE0   0xFF608020
  31 #define SH_DMARS_BASE0  0xFF609000
  32 #define CHCR_TS_LOW_MASK        0x00000018
  33 #define CHCR_TS_LOW_SHIFT       3
  34 #define CHCR_TS_HIGH_MASK       0
  35 #define CHCR_TS_HIGH_SHIFT      0
  36 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
  37 #define DMTE0_IRQ       48      /* DMAC0A*/
  38 #define DMTE4_IRQ       76      /* DMAC0B */
  39 #define DMTE6_IRQ       40
  40 #define DMTE8_IRQ       42      /* DMAC1A */
  41 #define DMTE9_IRQ       43
  42 #define DMTE10_IRQ      72      /* DMAC1B */
  43 #define DMTE11_IRQ      73
  44 #define DMAE0_IRQ       78      /* DMA Error IRQ*/
  45 #define DMAE1_IRQ       74      /* DMA Error IRQ*/
  46 #define SH_DMAC_BASE0   0xFE008020
  47 #define SH_DMAC_BASE1   0xFDC08020
  48 #define SH_DMARS_BASE0  0xFDC09000
  49 #define CHCR_TS_LOW_MASK        0x00000018
  50 #define CHCR_TS_LOW_SHIFT       3
  51 #define CHCR_TS_HIGH_MASK       0
  52 #define CHCR_TS_HIGH_SHIFT      0
  53 #elif defined(CONFIG_CPU_SUBTYPE_SH7724)
  54 #define DMTE0_IRQ       48      /* DMAC0A*/
  55 #define DMTE4_IRQ       76      /* DMAC0B */
  56 #define DMTE6_IRQ       40
  57 #define DMTE8_IRQ       42      /* DMAC1A */
  58 #define DMTE9_IRQ       43
  59 #define DMTE10_IRQ      72      /* DMAC1B */
  60 #define DMTE11_IRQ      73
  61 #define DMAE0_IRQ       78      /* DMA Error IRQ*/
  62 #define DMAE1_IRQ       74      /* DMA Error IRQ*/
  63 #define SH_DMAC_BASE0   0xFE008020
  64 #define SH_DMAC_BASE1   0xFDC08020
  65 #define SH_DMARS_BASE0  0xFE009000
  66 #define SH_DMARS_BASE1  0xFDC09000
  67 #define CHCR_TS_LOW_MASK        0x00000018
  68 #define CHCR_TS_LOW_SHIFT       3
  69 #define CHCR_TS_HIGH_MASK       0x00600000
  70 #define CHCR_TS_HIGH_SHIFT      21
  71 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
  72 #define DMTE0_IRQ       34
  73 #define DMTE4_IRQ       44
  74 #define DMTE6_IRQ       46
  75 #define DMTE8_IRQ       92
  76 #define DMTE9_IRQ       93
  77 #define DMTE10_IRQ      94
  78 #define DMTE11_IRQ      95
  79 #define DMAE0_IRQ       38      /* DMA Error IRQ */
  80 #define SH_DMAC_BASE0   0xFC808020
  81 #define SH_DMAC_BASE1   0xFC818020
  82 #define SH_DMARS_BASE0  0xFC809000
  83 #define CHCR_TS_LOW_MASK        0x00000018
  84 #define CHCR_TS_LOW_SHIFT       3
  85 #define CHCR_TS_HIGH_MASK       0
  86 #define CHCR_TS_HIGH_SHIFT      0
  87 #else /* SH7785 */
  88 #define DMTE0_IRQ       33
  89 #define DMTE4_IRQ       37
  90 #define DMTE6_IRQ       52
  91 #define DMTE8_IRQ       54
  92 #define DMTE9_IRQ       55
  93 #define DMTE10_IRQ      56
  94 #define DMTE11_IRQ      57
  95 #define DMAE0_IRQ       39      /* DMA Error IRQ0 */
  96 #define DMAE1_IRQ       58      /* DMA Error IRQ1 */
  97 #define SH_DMAC_BASE0   0xFC808020
  98 #define SH_DMAC_BASE1   0xFCC08020
  99 #define SH_DMARS_BASE0  0xFC809000
 100 #define CHCR_TS_LOW_MASK        0x00000018
 101 #define CHCR_TS_LOW_SHIFT       3
 102 #define CHCR_TS_HIGH_MASK       0
 103 #define CHCR_TS_HIGH_SHIFT      0
 104 #endif
 105
 106 #define REQ_HE          0x000000C0
 107 #define REQ_H           0x00000080
 108 #define REQ_LE          0x00000040
 109 #define TM_BURST        0x00000020
 110
 111 /*
 112  * The SuperH DMAC supports a number of transmit sizes, we list them here,
 113  * with their respective values as they appear in the CHCR registers.
 114  *
 115  * Defaults to a 64-bit transfer size.
 116  */
 117 enum {
 118         XMIT_SZ_8BIT            = 0,
 119         XMIT_SZ_16BIT           = 1,
 120         XMIT_SZ_32BIT           = 2,
 121         XMIT_SZ_64BIT           = 7,
 122         XMIT_SZ_128BIT          = 3,
 123         XMIT_SZ_256BIT          = 4,
 124         XMIT_SZ_128BIT_BLK      = 0xb,
 125         XMIT_SZ_256BIT_BLK      = 0xc,
 126 };
 127
 128 /*
 129  * The DMA count is defined as the number of bytes to transfer.
 130  */
 131 #define TS_SHIFT {                      \
 132         [XMIT_SZ_8BIT]          = 0,    \
 133         [XMIT_SZ_16BIT]         = 1,    \
 134         [XMIT_SZ_32BIT]         = 2,    \
 135         [XMIT_SZ_64BIT]         = 3,    \
 136         [XMIT_SZ_128BIT]        = 4,    \
 137         [XMIT_SZ_256BIT]        = 5,    \
 138         [XMIT_SZ_128BIT_BLK]    = 4,    \
 139         [XMIT_SZ_256BIT_BLK]    = 5,    \
 140 }
 141
 142 #define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \
 143                          ((((i) >> 2) & 3) << CHCR_TS_HIGH_SHIFT))
 144
 145 #endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */