4 * Copyright (c) 2004 - 2009 Paul Mundt
5 * Copyright (c) 2002 M. R. Brown
7 * Modelled after arch/mips/pci/pci.c:
8 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/init.h>
18 #include <linux/types.h>
19 #include <linux/dma-debug.h>
21 #include <linux/mutex.h>
23 unsigned long PCIBIOS_MIN_IO = 0x0000;
24 unsigned long PCIBIOS_MIN_MEM = 0;
27 * The PCI controller list.
29 static struct pci_channel *hose_head, **hose_tail = &hose_head;
31 static int pci_initialized;
33 static void __devinit pcibios_scanbus(struct pci_channel *hose)
35 static int next_busno;
36 static int need_domain_info;
39 bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
42 need_domain_info = need_domain_info || hose->index;
43 hose->need_domain_info = need_domain_info;
45 next_busno = bus->subordinate + 1;
46 /* Don't allow 8-bit bus number overflow inside the hose -
47 reserve some space for bridges. */
48 if (next_busno > 224) {
53 pci_bus_size_bridges(bus);
54 pci_bus_assign_resources(bus);
55 pci_enable_bridges(bus);
59 static DEFINE_MUTEX(pci_scan_mutex);
61 int __devinit register_pci_controller(struct pci_channel *hose)
65 for (i = 0; i < hose->nr_resources; i++) {
66 struct resource *res = hose->resources + i;
68 if (res->flags & IORESOURCE_IO) {
69 if (request_resource(&ioport_resource, res) < 0)
72 if (request_resource(&iomem_resource, res) < 0)
78 hose_tail = &hose->next;
81 * Do not panic here but later - this might hapen before console init.
83 if (!hose->io_map_base) {
85 "registering PCI controller with io_map_base unset\n");
89 * Setup the ERR/PERR and SERR timers, if available.
91 pcibios_enable_timers(hose);
94 * Scan the bus if it is register after the PCI subsystem
97 if (pci_initialized) {
98 mutex_lock(&pci_scan_mutex);
99 pcibios_scanbus(hose);
100 mutex_unlock(&pci_scan_mutex);
106 for (--i; i >= 0; i--)
107 release_resource(&hose->resources[i]);
109 printk(KERN_WARNING "Skipping PCI bus scan due to resource conflict\n");
113 static int __init pcibios_init(void)
115 struct pci_channel *hose;
117 /* Scan all of the recorded PCI controllers. */
118 for (hose = hose_head; hose; hose = hose->next)
119 pcibios_scanbus(hose);
121 pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq);
123 dma_debug_add_bus(&pci_bus_type);
129 subsys_initcall(pcibios_init);
131 static void pcibios_fixup_device_resources(struct pci_dev *dev,
134 /* Update device resources. */
135 struct pci_channel *hose = bus->sysdata;
136 unsigned long offset = 0;
139 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
140 if (!dev->resource[i].start)
142 if (dev->resource[i].flags & IORESOURCE_IO)
143 offset = hose->io_offset;
144 else if (dev->resource[i].flags & IORESOURCE_MEM)
145 offset = hose->mem_offset;
147 dev->resource[i].start += offset;
148 dev->resource[i].end += offset;
153 * Called after each bus is probed, but before its children
156 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
158 struct pci_dev *dev = bus->self;
159 struct list_head *ln;
160 struct pci_channel *hose = bus->sysdata;
165 for (i = 0; i < hose->nr_resources; i++)
166 bus->resource[i] = hose->resources + i;
169 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
172 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
173 pcibios_fixup_device_resources(dev, bus);
178 * We need to avoid collisions with `mirrored' VGA ports
179 * and other strange ISA hardware, so we always want the
180 * addresses to be allocated in the 0x000-0x0ff region
183 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
184 resource_size_t size, resource_size_t align)
186 struct pci_dev *dev = data;
187 struct pci_channel *hose = dev->sysdata;
188 resource_size_t start = res->start;
190 if (res->flags & IORESOURCE_IO) {
191 if (start < PCIBIOS_MIN_IO + hose->resources[0].start)
192 start = PCIBIOS_MIN_IO + hose->resources[0].start;
195 * Put everything into 0x00-0xff region modulo 0x400.
198 start = (start + 0x3ff) & ~0x3ff;
204 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
205 struct resource *res)
207 struct pci_channel *hose = dev->sysdata;
208 unsigned long offset = 0;
210 if (res->flags & IORESOURCE_IO)
211 offset = hose->io_offset;
212 else if (res->flags & IORESOURCE_MEM)
213 offset = hose->mem_offset;
215 region->start = res->start - offset;
216 region->end = res->end - offset;
219 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
220 struct pci_bus_region *region)
222 struct pci_channel *hose = dev->sysdata;
223 unsigned long offset = 0;
225 if (res->flags & IORESOURCE_IO)
226 offset = hose->io_offset;
227 else if (res->flags & IORESOURCE_MEM)
228 offset = hose->mem_offset;
230 res->start = region->start + offset;
231 res->end = region->end + offset;
234 int pcibios_enable_device(struct pci_dev *dev, int mask)
236 return pci_enable_resources(dev, mask);
240 * If we set up a device for bus mastering, we need to check and set
241 * the latency timer as it may not be properly set.
243 static unsigned int pcibios_max_latency = 255;
245 void pcibios_set_master(struct pci_dev *dev)
248 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
250 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
251 else if (lat > pcibios_max_latency)
252 lat = pcibios_max_latency;
255 printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n",
257 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
260 void __init pcibios_update_irq(struct pci_dev *dev, int irq)
262 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
265 char * __devinit pcibios_setup(char *str)
271 pcibios_bus_report_status_early(struct pci_channel *hose,
272 int top_bus, int current_bus,
273 unsigned int status_mask, int warn)
275 unsigned int pci_devfn;
279 for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
280 if (PCI_FUNC(pci_devfn))
282 ret = early_read_config_word(hose, top_bus, current_bus,
283 pci_devfn, PCI_STATUS, &status);
284 if (ret != PCIBIOS_SUCCESSFUL)
286 if (status == 0xffff)
289 early_write_config_word(hose, top_bus, current_bus,
290 pci_devfn, PCI_STATUS,
291 status & status_mask);
293 printk("(%02x:%02x: %04X) ", current_bus,
299 * We can't use pci_find_device() here since we are
300 * called from interrupt context.
302 static void __init_refok
303 pcibios_bus_report_status(struct pci_bus *bus, unsigned int status_mask,
308 list_for_each_entry(dev, &bus->devices, bus_list) {
312 * ignore host bridge - we handle
315 if (dev->bus->number == 0 && dev->devfn == 0)
318 pci_read_config_word(dev, PCI_STATUS, &status);
319 if (status == 0xffff)
322 if ((status & status_mask) == 0)
325 /* clear the status errors */
326 pci_write_config_word(dev, PCI_STATUS, status & status_mask);
329 printk("(%s: %04X) ", pci_name(dev), status);
332 list_for_each_entry(dev, &bus->devices, bus_list)
333 if (dev->subordinate)
334 pcibios_bus_report_status(dev->subordinate, status_mask, warn);
337 void __init_refok pcibios_report_status(unsigned int status_mask, int warn)
339 struct pci_channel *hose;
341 for (hose = hose_head; hose; hose = hose->next) {
342 if (unlikely(!hose->bus))
343 pcibios_bus_report_status_early(hose, hose_head->index,
344 hose->index, status_mask, warn);
346 pcibios_bus_report_status(hose->bus, status_mask, warn);
350 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
351 enum pci_mmap_state mmap_state, int write_combine)
354 * I/O space can be accessed via normal processor loads and stores on
355 * this platform but for now we elect not to do this and portable
356 * drivers should not do this anyway.
358 if (mmap_state == pci_mmap_io)
362 * Ignore write-combine; for now only return uncached mappings.
364 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
366 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
367 vma->vm_end - vma->vm_start,
371 #ifndef CONFIG_GENERIC_IOMAP
373 static void __iomem *ioport_map_pci(struct pci_dev *dev,
374 unsigned long port, unsigned int nr)
376 struct pci_channel *chan = dev->sysdata;
378 if (unlikely(!chan->io_map_base)) {
379 chan->io_map_base = generic_io_base;
381 if (pci_domains_supported)
382 panic("To avoid data corruption io_map_base MUST be "
383 "set with multiple PCI domains.");
387 return (void __iomem *)(chan->io_map_base + port);
390 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
392 resource_size_t start = pci_resource_start(dev, bar);
393 resource_size_t len = pci_resource_len(dev, bar);
394 unsigned long flags = pci_resource_flags(dev, bar);
396 if (unlikely(!len || !start))
398 if (maxlen && len > maxlen)
401 if (flags & IORESOURCE_IO)
402 return ioport_map_pci(dev, start, len);
403 if (flags & IORESOURCE_MEM) {
404 if (flags & IORESOURCE_CACHEABLE)
405 return ioremap(start, len);
406 return ioremap_nocache(start, len);
411 EXPORT_SYMBOL(pci_iomap);
413 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
417 EXPORT_SYMBOL(pci_iounmap);
419 #endif /* CONFIG_GENERIC_IOMAP */
421 #ifdef CONFIG_HOTPLUG
422 EXPORT_SYMBOL(pcibios_resource_to_bus);
423 EXPORT_SYMBOL(pcibios_bus_to_resource);
424 EXPORT_SYMBOL(PCIBIOS_MIN_IO);
425 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);