arch/sh/boards/board-urquell.c

   1 /*
   2  * Renesas Technology Corp. SH7786 Urquell Support.
   3  *
   4  * Copyright (C) 2008  Kuninori Morimoto <morimoto.kuninori@renesas.com>
   5  * Copyright (C) 2009, 2010  Paul Mundt
   6  *
   7  * Based on board-sh7785lcr.c
   8  * Copyright (C) 2008  Yoshihiro Shimoda
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/fb.h>
  17 #include <linux/smc91x.h>
  18 #include <linux/mtd/physmap.h>
  19 #include <linux/delay.h>
  20 #include <linux/gpio.h>
  21 #include <linux/irq.h>
  22 #include <linux/clk.h>
  23 #include <mach/urquell.h>
  24 #include <cpu/sh7786.h>
  25 #include <asm/heartbeat.h>
  26 #include <asm/sizes.h>
  27
  28 /*
  29  * bit  1234 5678
  30  *----------------------------
  31  * SW1  0101 0010  -> Pck 33MHz version
  32  *     (1101 0010)    Pck 66MHz version
  33  * SW2  0x1x xxxx  -> little endian
  34  *                    29bit mode
  35  * SW47 0001 1000  -> CS0 : on-board flash
  36  *                    CS1 : SRAM, registers, LAN, PCMCIA
  37  *                    38400 bps for SCIF1
  38  *
  39  * Address
  40  * 0x00000000 - 0x04000000  (CS0)     Nor Flash
  41  * 0x04000000 - 0x04200000  (CS1)     SRAM
  42  * 0x05000000 - 0x05800000  (CS1)     on board register
  43  * 0x05800000 - 0x06000000  (CS1)     LAN91C111
  44  * 0x06000000 - 0x06400000  (CS1)     PCMCIA
  45  * 0x08000000 - 0x10000000  (CS2-CS3) DDR3
  46  * 0x10000000 - 0x14000000  (CS4)     PCIe
  47  * 0x14000000 - 0x14800000  (CS5)     Core0 LRAM/URAM
  48  * 0x14800000 - 0x15000000  (CS5)     Core1 LRAM/URAM
  49  * 0x18000000 - 0x1C000000  (CS6)     ATA/NAND-Flash
  50  * 0x1C000000 -             (CS7)     SH7786 Control register
  51  */
  52
  53 /* HeartBeat */
  54 static struct resource heartbeat_resource = {
  55         .start  = BOARDREG(SLEDR),
  56         .end    = BOARDREG(SLEDR),
  57         .flags  = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
  58 };
  59
  60 static struct platform_device heartbeat_device = {
  61         .name           = "heartbeat",
  62         .id             = -1,
  63         .num_resources  = 1,
  64         .resource       = &heartbeat_resource,
  65 };
  66
  67 /* LAN91C111 */
  68 static struct smc91x_platdata smc91x_info = {
  69         .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
  70 };
  71
  72 static struct resource smc91x_eth_resources[] = {
  73         [0] = {
  74                 .name   = "SMC91C111" ,
  75                 .start  = 0x05800300,
  76                 .end    = 0x0580030f,
  77                 .flags  = IORESOURCE_MEM,
  78         },
  79         [1] = {
  80                 .start  = 11,
  81                 .flags  = IORESOURCE_IRQ,
  82         },
  83 };
  84
  85 static struct platform_device smc91x_eth_device = {
  86         .name           = "smc91x",
  87         .num_resources  = ARRAY_SIZE(smc91x_eth_resources),
  88         .resource       = smc91x_eth_resources,
  89         .dev    = {
  90                 .platform_data  = &smc91x_info,
  91         },
  92 };
  93
  94 /* Nor Flash */
  95 static struct mtd_partition nor_flash_partitions[] = {
  96         {
  97                 .name           = "loader",
  98                 .offset         = 0x00000000,
  99                 .size           = SZ_512K,
 100                 .mask_flags     = MTD_WRITEABLE,        /* Read-only */
 101         },
 102         {
 103                 .name           = "bootenv",
 104                 .offset         = MTDPART_OFS_APPEND,
 105                 .size           = SZ_512K,
 106                 .mask_flags     = MTD_WRITEABLE,        /* Read-only */
 107         },
 108         {
 109                 .name           = "kernel",
 110                 .offset         = MTDPART_OFS_APPEND,
 111                 .size           = SZ_4M,
 112         },
 113         {
 114                 .name           = "data",
 115                 .offset         = MTDPART_OFS_APPEND,
 116                 .size           = MTDPART_SIZ_FULL,
 117         },
 118 };
 119
 120 static struct physmap_flash_data nor_flash_data = {
 121         .width          = 2,
 122         .parts          = nor_flash_partitions,
 123         .nr_parts       = ARRAY_SIZE(nor_flash_partitions),
 124 };
 125
 126 static struct resource nor_flash_resources[] = {
 127         [0] = {
 128                 .start  = NOR_FLASH_ADDR,
 129                 .end    = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
 130                 .flags  = IORESOURCE_MEM,
 131         }
 132 };
 133
 134 static struct platform_device nor_flash_device = {
 135         .name           = "physmap-flash",
 136         .dev            = {
 137                 .platform_data  = &nor_flash_data,
 138         },
 139         .num_resources  = ARRAY_SIZE(nor_flash_resources),
 140         .resource       = nor_flash_resources,
 141 };
 142
 143 static struct platform_device *urquell_devices[] __initdata = {
 144         &heartbeat_device,
 145         &smc91x_eth_device,
 146         &nor_flash_device,
 147 };
 148
 149 static int __init urquell_devices_setup(void)
 150 {
 151         /* USB */
 152         gpio_request(GPIO_FN_USB_OVC0,  NULL);
 153         gpio_request(GPIO_FN_USB_PENC0, NULL);
 154
 155         /* enable LAN */
 156         __raw_writew(__raw_readw(UBOARDREG(IRL2MSKR)) & ~0x00000001,
 157                   UBOARDREG(IRL2MSKR));
 158
 159         return platform_add_devices(urquell_devices,
 160                                     ARRAY_SIZE(urquell_devices));
 161 }
 162 device_initcall(urquell_devices_setup);
 163
 164 static void urquell_power_off(void)
 165 {
 166         __raw_writew(0xa5a5, UBOARDREG(SRSTR));
 167 }
 168
 169 static void __init urquell_init_irq(void)
 170 {
 171         plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK);
 172 }
 173
 174 static int urquell_mode_pins(void)
 175 {
 176         return __raw_readw(UBOARDREG(MDSWMR));
 177 }
 178
 179 static int urquell_clk_init(void)
 180 {
 181         struct clk *clk;
 182         int ret;
 183
 184         /*
 185          * Only handle the EXTAL case, anyone interfacing a crystal
 186          * resonator will need to provide their own input clock.
 187          */
 188         if (test_mode_pin(MODE_PIN9))
 189                 return -EINVAL;
 190
 191         clk = clk_get(NULL, "extal");
 192         if (!clk || IS_ERR(clk))
 193                 return PTR_ERR(clk);
 194         ret = clk_set_rate(clk, 33333333);
 195         clk_put(clk);
 196
 197         return ret;
 198 }
 199
 200 /* Initialize the board */
 201 static void __init urquell_setup(char **cmdline_p)
 202 {
 203         printk(KERN_INFO "Renesas Technology Corp. Urquell support.\n");
 204
 205         pm_power_off = urquell_power_off;
 206 }
 207
 208 /*
 209  * The Machine Vector
 210  */
 211 static struct sh_machine_vector mv_urquell __initmv = {
 212         .mv_name        = "Urquell",
 213         .mv_setup       = urquell_setup,
 214         .mv_init_irq    = urquell_init_irq,
 215         .mv_mode_pins   = urquell_mode_pins,
 216         .mv_clk_init    = urquell_clk_init,
 217 };