2 * Renesas Technology Corp. R0P7785LC0011RL Support.
4 * Copyright (C) 2008 Yoshihiro Shimoda
5 * Copyright (C) 2009 Paul Mundt
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/init.h>
12 #include <linux/platform_device.h>
13 #include <linux/sm501.h>
14 #include <linux/sm501-regs.h>
16 #include <linux/mtd/physmap.h>
17 #include <linux/delay.h>
18 #include <linux/i2c.h>
19 #include <linux/i2c-pca-platform.h>
20 #include <linux/i2c-algo-pca.h>
21 #include <linux/irq.h>
22 #include <linux/clk.h>
23 #include <linux/errno.h>
24 #include <mach/sh7785lcr.h>
25 #include <asm/heartbeat.h>
26 #include <asm/clock.h>
27 #include <cpu/sh7785.h>
30 * NOTE: This board has 2 physical memory maps.
31 * Please look at include/asm-sh/sh7785lcr.h or hardware manual.
33 static struct resource heartbeat_resources[] = {
37 .flags = IORESOURCE_MEM,
41 static struct heartbeat_data heartbeat_data = {
45 static struct platform_device heartbeat_device = {
49 .platform_data = &heartbeat_data,
51 .num_resources = ARRAY_SIZE(heartbeat_resources),
52 .resource = heartbeat_resources,
55 static struct mtd_partition nor_flash_partitions[] = {
63 .offset = MTDPART_OFS_APPEND,
68 .offset = MTDPART_OFS_APPEND,
69 .size = 4 * 1024 * 1024,
73 .offset = MTDPART_OFS_APPEND,
74 .size = MTDPART_SIZ_FULL,
78 static struct physmap_flash_data nor_flash_data = {
80 .parts = nor_flash_partitions,
81 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
84 static struct resource nor_flash_resources[] = {
86 .start = NOR_FLASH_ADDR,
87 .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
88 .flags = IORESOURCE_MEM,
92 static struct platform_device nor_flash_device = {
93 .name = "physmap-flash",
95 .platform_data = &nor_flash_data,
97 .num_resources = ARRAY_SIZE(nor_flash_resources),
98 .resource = nor_flash_resources,
101 static struct resource r8a66597_usb_host_resources[] = {
103 .name = "r8a66597_hcd",
104 .start = R8A66597_ADDR,
105 .end = R8A66597_ADDR + R8A66597_SIZE - 1,
106 .flags = IORESOURCE_MEM,
109 .name = "r8a66597_hcd",
112 .flags = IORESOURCE_IRQ,
116 static struct platform_device r8a66597_usb_host_device = {
117 .name = "r8a66597_hcd",
121 .coherent_dma_mask = 0xffffffff,
123 .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
124 .resource = r8a66597_usb_host_resources,
127 static struct resource sm501_resources[] = {
129 .start = SM107_MEM_ADDR,
130 .end = SM107_MEM_ADDR + SM107_MEM_SIZE - 1,
131 .flags = IORESOURCE_MEM,
134 .start = SM107_REG_ADDR,
135 .end = SM107_REG_ADDR + SM107_REG_SIZE - 1,
136 .flags = IORESOURCE_MEM,
140 .flags = IORESOURCE_IRQ,
144 static struct fb_videomode sm501_default_mode_crt = {
145 .pixclock = 35714, /* 28MHz */
154 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
157 static struct fb_videomode sm501_default_mode_pnl = {
158 .pixclock = 40000, /* 25MHz */
170 static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = {
172 .def_mode = &sm501_default_mode_pnl,
173 .flags = SM501FB_FLAG_USE_INIT_MODE |
174 SM501FB_FLAG_USE_HWCURSOR |
175 SM501FB_FLAG_USE_HWACCEL |
176 SM501FB_FLAG_DISABLE_AT_EXIT |
177 SM501FB_FLAG_PANEL_NO_VBIASEN,
180 static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = {
182 .def_mode = &sm501_default_mode_crt,
183 .flags = SM501FB_FLAG_USE_INIT_MODE |
184 SM501FB_FLAG_USE_HWCURSOR |
185 SM501FB_FLAG_USE_HWACCEL |
186 SM501FB_FLAG_DISABLE_AT_EXIT,
189 static struct sm501_platdata_fb sm501_fb_pdata = {
190 .fb_route = SM501_FB_OWN,
191 .fb_crt = &sm501_pdata_fbsub_crt,
192 .fb_pnl = &sm501_pdata_fbsub_pnl,
195 static struct sm501_initdata sm501_initdata = {
201 .mclk = 84 * 1000000,
202 .m1xclk = 112 * 1000000,
205 static struct sm501_platdata sm501_platform_data = {
206 .init = &sm501_initdata,
207 .fb = &sm501_fb_pdata,
210 static struct platform_device sm501_device = {
214 .platform_data = &sm501_platform_data,
216 .num_resources = ARRAY_SIZE(sm501_resources),
217 .resource = sm501_resources,
220 static struct resource i2c_resources[] = {
222 .start = PCA9564_ADDR,
223 .end = PCA9564_ADDR + PCA9564_SIZE - 1,
224 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
229 .flags = IORESOURCE_IRQ,
233 static struct i2c_pca9564_pf_platform_data i2c_platform_data = {
235 .i2c_clock_speed = I2C_PCA_CON_330kHz,
239 static struct platform_device i2c_device = {
240 .name = "i2c-pca-platform",
243 .platform_data = &i2c_platform_data,
245 .num_resources = ARRAY_SIZE(i2c_resources),
246 .resource = i2c_resources,
249 static struct platform_device *sh7785lcr_devices[] __initdata = {
252 &r8a66597_usb_host_device,
257 static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = {
259 I2C_BOARD_INFO("r2025sd", 0x32),
263 static int __init sh7785lcr_devices_setup(void)
265 i2c_register_board_info(0, sh7785lcr_i2c_devices,
266 ARRAY_SIZE(sh7785lcr_i2c_devices));
268 return platform_add_devices(sh7785lcr_devices,
269 ARRAY_SIZE(sh7785lcr_devices));
271 __initcall(sh7785lcr_devices_setup);
273 /* Initialize IRQ setting */
274 void __init init_sh7785lcr_IRQ(void)
276 plat_irq_setup_pins(IRQ_MODE_IRQ7654);
277 plat_irq_setup_pins(IRQ_MODE_IRQ3210);
280 static int sh7785lcr_clk_init(void)
285 clk = clk_get(NULL, "extal");
286 if (!clk || IS_ERR(clk))
288 ret = clk_set_rate(clk, 33333333);
294 static void sh7785lcr_power_off(void)
298 p = ioremap(PLD_POFCR, PLD_POFCR + 1);
300 printk(KERN_ERR "%s: ioremap error.\n", __func__);
310 /* Initialize the board */
311 static void __init sh7785lcr_setup(char **cmdline_p)
313 void __iomem *sm501_reg;
315 printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n");
317 pm_power_off = sh7785lcr_power_off;
319 /* sm501 DRAM configuration */
320 sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL;
321 writel(0x000307c2, sm501_reg);
324 /* Return the board specific boot mode pin configuration */
325 static int sh7785lcr_mode_pins(void)
329 /* These are the factory default settings of S1 and S2.
330 * If you change these dip switches then you will need to
331 * adjust the values below as well.
333 value |= MODE_PIN4; /* Clock Mode 16 */
334 value |= MODE_PIN5; /* 32-bit Area0 bus width */
335 value |= MODE_PIN6; /* 32-bit Area0 bus width */
336 value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */
337 value |= MODE_PIN8; /* Little Endian */
338 value |= MODE_PIN9; /* Master Mode */
339 value |= MODE_PIN14; /* No PLL step-up */
347 static struct sh_machine_vector mv_sh7785lcr __initmv = {
348 .mv_name = "SH7785LCR",
349 .mv_setup = sh7785lcr_setup,
350 .mv_clk_init = sh7785lcr_clk_init,
351 .mv_init_irq = init_sh7785lcr_IRQ,
352 .mv_mode_pins = sh7785lcr_mode_pins,