2 * Copyright IBM Corp 2000,2009
3 * Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>,
7 #include <linux/linkage.h>
8 #include <asm/asm-offsets.h>
12 # Parameter: r2 = schid of reipl device
17 .Lpg0: lpswe .Lnewpsw-.Lpg0(%r13)
18 .Lpg1: # do store status of all registers
20 stg %r1,.Lregsave-.Lpg0(%r13)
22 stmg %r0,%r15,__LC_GPREGS_SAVE_AREA-0x1000(%r1)
23 lg %r0,.Lregsave-.Lpg0(%r13)
24 stg %r0,__LC_GPREGS_SAVE_AREA-0x1000+8(%r1)
25 stctg %c0,%c15,__LC_CREGS_SAVE_AREA-0x1000(%r1)
26 stam %a0,%a15,__LC_AREGS_SAVE_AREA-0x1000(%r1)
27 lg %r10,.Ldump_pfx-.Lpg0(%r13)
28 mvc __LC_PREFIX_SAVE_AREA-0x1000(4,%r1),0(%r10)
29 stfpc __LC_FP_CREG_SAVE_AREA-0x1000(%r1)
30 stckc .Lclkcmp-.Lpg0(%r13)
31 mvc __LC_CLOCK_COMP_SAVE_AREA-0x1000(7,%r1),.Lclkcmp-.Lpg0(%r13)
32 stpt __LC_CPU_TIMER_SAVE_AREA-0x1000(%r1)
33 stg %r13, __LC_PSW_SAVE_AREA-0x1000+8(%r1)
35 lctlg %c6,%c6,.Lall-.Lpg0(%r13)
37 mvc __LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13)
38 stsch .Lschib-.Lpg0(%r13)
39 oi .Lschib+5-.Lpg0(%r13),0x84
40 .Lecs: xi .Lschib+27-.Lpg0(%r13),0x01
41 msch .Lschib-.Lpg0(%r13)
43 .Lssch: ssch .Liplorb-.Lpg0(%r13)
46 bas %r14,.Ldisab-.Lpg0(%r13)
47 .L001: mvc __LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13)
48 .Ltpi: lpswe .Lwaitpsw-.Lpg0(%r13)
49 .Lcont: c %r1,__LC_SUBCHANNEL_ID
51 clc __LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13)
53 tsch .Liplirb-.Lpg0(%r13)
54 tm .Liplirb+9-.Lpg0(%r13),0xbf
56 bas %r14,.Ldisab-.Lpg0(%r13)
57 .L002: tm .Liplirb+8-.Lpg0(%r13),0xf3
59 bas %r14,.Ldisab-.Lpg0(%r13)
60 .L003: st %r1,__LC_SUBCHANNEL_ID
61 lhi %r1,0 # mode 0 = esa
62 slr %r0,%r0 # set cpuid to zero
63 sigp %r1,%r0,0x12 # switch to esa mode
66 srl %r14,1 # need to kill hi bit to avoid specification exceptions.
67 st %r14,.Ldispsw+12-.Lpg0(%r13)
68 lpswe .Ldispsw-.Lpg0(%r13)
70 .Lclkcmp: .quad 0x0000000000000000
71 .Lall: .quad 0x00000000ff000000
72 .Ldump_pfx: .quad dump_prefix_page
73 .Lregsave: .quad 0x0000000000000000
76 * These addresses have to be 31 bit otherwise
77 * the sigp will throw a specifcation exception
78 * when switching to ESA mode as bit 31 be set
80 * Bit 31 of the addresses has to be 0 for the
81 * 31bit lpswe instruction a fact they appear to have
82 * omitted from the pop.
84 .Lnewpsw: .quad 0x0000000080000000
86 .Lpcnew: .quad 0x0000000080000000
88 .Lionew: .quad 0x0000000080000000
90 .Lwaitpsw: .quad 0x0202000080000000
92 .Ldispsw: .quad 0x0002000080000000
93 .quad 0x0000000000000000
94 .Liplccws: .long 0x02000000,0x60000018
95 .long 0x08000008,0x20000001
96 .Liplorb: .long 0x0049504c,0x0040ff80
97 .long 0x00000000+.Liplccws
98 .Lschib: .long 0x00000000,0x00000000
99 .long 0x00000000,0x00000000
100 .long 0x00000000,0x00000000
101 .long 0x00000000,0x00000000
102 .long 0x00000000,0x00000000
103 .long 0x00000000,0x00000000
104 .Liplirb: .long 0x00000000,0x00000000
105 .long 0x00000000,0x00000000
106 .long 0x00000000,0x00000000
107 .long 0x00000000,0x00000000
108 .long 0x00000000,0x00000000
109 .long 0x00000000,0x00000000
110 .long 0x00000000,0x00000000
111 .long 0x00000000,0x00000000