arch/ppc/syslib/mv64x60.c

   1 /*
   2  * arch/ppc/syslib/mv64x60.c
   3  *
   4  * Common routines for the Marvell/Galileo Discovery line of host bridges
   5  * (gt64260, mv64360, mv64460, ...).
   6  *
   7  * Author: Mark A. Greer <mgreer@mvista.com>
   8  *
   9  * 2004 (c) MontaVista, Software, Inc.  This file is licensed under
  10  * the terms of the GNU General Public License version 2.  This program
  11  * is licensed "as is" without any warranty of any kind, whether express
  12  * or implied.
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/pci.h>
  17 #include <linux/slab.h>
  18 #include <linux/module.h>
  19 #include <linux/string.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/mv643xx.h>
  22
  23 #include <asm/byteorder.h>
  24 #include <asm/io.h>
  25 #include <asm/irq.h>
  26 #include <asm/uaccess.h>
  27 #include <asm/machdep.h>
  28 #include <asm/pci-bridge.h>
  29 #include <asm/delay.h>
  30 #include <asm/mv64x60.h>
  31
  32
  33 u8              mv64x60_pci_exclude_bridge = 1;
  34 spinlock_t      mv64x60_lock = SPIN_LOCK_UNLOCKED;
  35
  36 static phys_addr_t      mv64x60_bridge_pbase = 0;
  37 static void             *mv64x60_bridge_vbase = 0;
  38 static u32              mv64x60_bridge_type = MV64x60_TYPE_INVALID;
  39 static u32              mv64x60_bridge_rev = 0;
  40
  41 static u32 gt64260_translate_size(u32 base, u32 size, u32 num_bits);
  42 static u32 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits);
  43 static void gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus,
  44         u32 window, u32 base);
  45 static void gt64260_set_pci2regs_window(struct mv64x60_handle *bh,
  46         struct pci_controller *hose, u32 bus, u32 base);
  47 static u32 gt64260_is_enabled_32bit(struct mv64x60_handle *bh, u32 window);
  48 static void gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window);
  49 static void gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window);
  50 static void gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window);
  51 static void gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window);
  52 static void gt64260_disable_all_windows(struct mv64x60_handle *bh,
  53         struct mv64x60_setup_info *si);
  54 static void gt64260a_chip_specific_init(struct mv64x60_handle *bh,
  55         struct mv64x60_setup_info *si);
  56 static void gt64260b_chip_specific_init(struct mv64x60_handle *bh,
  57         struct mv64x60_setup_info *si);
  58
  59 static u32 mv64360_translate_size(u32 base, u32 size, u32 num_bits);
  60 static u32 mv64360_untranslate_size(u32 base, u32 size, u32 num_bits);
  61 static void mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus,
  62         u32 window, u32 base);
  63 static void mv64360_set_pci2regs_window(struct mv64x60_handle *bh,
  64         struct pci_controller *hose, u32 bus, u32 base);
  65 static u32 mv64360_is_enabled_32bit(struct mv64x60_handle *bh, u32 window);
  66 static void mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window);
  67 static void mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window);
  68 static void mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window);
  69 static void mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window);
  70 static void mv64360_disable_all_windows(struct mv64x60_handle *bh,
  71         struct mv64x60_setup_info *si);
  72 static void mv64360_config_io2mem_windows(struct mv64x60_handle *bh,
  73         struct mv64x60_setup_info *si,
  74         u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
  75 static void mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base);
  76 static void mv64360_chip_specific_init(struct mv64x60_handle *bh,
  77         struct mv64x60_setup_info *si);
  78 static void mv64460_chip_specific_init(struct mv64x60_handle *bh,
  79         struct mv64x60_setup_info *si);
  80
  81
  82 /*
  83  * Define tables that have the chip-specific info for each type of
  84  * Marvell bridge chip.
  85  */
  86 static struct mv64x60_chip_info gt64260a_ci __initdata = { /* GT64260A */
  87         .translate_size         = gt64260_translate_size,
  88         .untranslate_size       = gt64260_untranslate_size,
  89         .set_pci2mem_window     = gt64260_set_pci2mem_window,
  90         .set_pci2regs_window    = gt64260_set_pci2regs_window,
  91         .is_enabled_32bit       = gt64260_is_enabled_32bit,
  92         .enable_window_32bit    = gt64260_enable_window_32bit,
  93         .disable_window_32bit   = gt64260_disable_window_32bit,
  94         .enable_window_64bit    = gt64260_enable_window_64bit,
  95         .disable_window_64bit   = gt64260_disable_window_64bit,
  96         .disable_all_windows    = gt64260_disable_all_windows,
  97         .chip_specific_init     = gt64260a_chip_specific_init,
  98         .window_tab_32bit       = gt64260_32bit_windows,
  99         .window_tab_64bit       = gt64260_64bit_windows,
 100 };
 101
 102 static struct mv64x60_chip_info gt64260b_ci __initdata = { /* GT64260B */
 103         .translate_size         = gt64260_translate_size,
 104         .untranslate_size       = gt64260_untranslate_size,
 105         .set_pci2mem_window     = gt64260_set_pci2mem_window,
 106         .set_pci2regs_window    = gt64260_set_pci2regs_window,
 107         .is_enabled_32bit       = gt64260_is_enabled_32bit,
 108         .enable_window_32bit    = gt64260_enable_window_32bit,
 109         .disable_window_32bit   = gt64260_disable_window_32bit,
 110         .enable_window_64bit    = gt64260_enable_window_64bit,
 111         .disable_window_64bit   = gt64260_disable_window_64bit,
 112         .disable_all_windows    = gt64260_disable_all_windows,
 113         .chip_specific_init     = gt64260b_chip_specific_init,
 114         .window_tab_32bit       = gt64260_32bit_windows,
 115         .window_tab_64bit       = gt64260_64bit_windows,
 116 };
 117
 118 static struct mv64x60_chip_info mv64360_ci __initdata = { /* MV64360 */
 119         .translate_size         = mv64360_translate_size,
 120         .untranslate_size       = mv64360_untranslate_size,
 121         .set_pci2mem_window     = mv64360_set_pci2mem_window,
 122         .set_pci2regs_window    = mv64360_set_pci2regs_window,
 123         .is_enabled_32bit       = mv64360_is_enabled_32bit,
 124         .enable_window_32bit    = mv64360_enable_window_32bit,
 125         .disable_window_32bit   = mv64360_disable_window_32bit,
 126         .enable_window_64bit    = mv64360_enable_window_64bit,
 127         .disable_window_64bit   = mv64360_disable_window_64bit,
 128         .disable_all_windows    = mv64360_disable_all_windows,
 129         .config_io2mem_windows  = mv64360_config_io2mem_windows,
 130         .set_mpsc2regs_window   = mv64360_set_mpsc2regs_window,
 131         .chip_specific_init     = mv64360_chip_specific_init,
 132         .window_tab_32bit       = mv64360_32bit_windows,
 133         .window_tab_64bit       = mv64360_64bit_windows,
 134 };
 135
 136 static struct mv64x60_chip_info mv64460_ci __initdata = { /* MV64460 */
 137         .translate_size         = mv64360_translate_size,
 138         .untranslate_size       = mv64360_untranslate_size,
 139         .set_pci2mem_window     = mv64360_set_pci2mem_window,
 140         .set_pci2regs_window    = mv64360_set_pci2regs_window,
 141         .is_enabled_32bit       = mv64360_is_enabled_32bit,
 142         .enable_window_32bit    = mv64360_enable_window_32bit,
 143         .disable_window_32bit   = mv64360_disable_window_32bit,
 144         .enable_window_64bit    = mv64360_enable_window_64bit,
 145         .disable_window_64bit   = mv64360_disable_window_64bit,
 146         .disable_all_windows    = mv64360_disable_all_windows,
 147         .config_io2mem_windows  = mv64360_config_io2mem_windows,
 148         .set_mpsc2regs_window   = mv64360_set_mpsc2regs_window,
 149         .chip_specific_init     = mv64460_chip_specific_init,
 150         .window_tab_32bit       = mv64360_32bit_windows,
 151         .window_tab_64bit       = mv64360_64bit_windows,
 152 };
 153
 154 /*
 155  *****************************************************************************
 156  *
 157  *      Platform Device Definitions
 158  *
 159  *****************************************************************************
 160  */
 161 #ifdef CONFIG_SERIAL_MPSC
 162 static struct mpsc_shared_pdata mv64x60_mpsc_shared_pdata = {
 163         .mrr_val                = 0x3ffffe38,
 164         .rcrr_val               = 0,
 165         .tcrr_val               = 0,
 166         .intr_cause_val         = 0,
 167         .intr_mask_val          = 0,
 168 };
 169
 170 static struct resource mv64x60_mpsc_shared_resources[] = {
 171         /* Do not change the order of the IORESOURCE_MEM resources */
 172         [0] = {
 173                 .name   = "mpsc routing base",
 174                 .start  = MV64x60_MPSC_ROUTING_OFFSET,
 175                 .end    = MV64x60_MPSC_ROUTING_OFFSET +
 176                         MPSC_ROUTING_REG_BLOCK_SIZE - 1,
 177                 .flags  = IORESOURCE_MEM,
 178         },
 179         [1] = {
 180                 .name   = "sdma intr base",
 181                 .start  = MV64x60_SDMA_INTR_OFFSET,
 182                 .end    = MV64x60_SDMA_INTR_OFFSET +
 183                         MPSC_SDMA_INTR_REG_BLOCK_SIZE - 1,
 184                 .flags  = IORESOURCE_MEM,
 185         },
 186 };
 187
 188 static struct platform_device mpsc_shared_device = { /* Shared device */
 189         .name           = MPSC_SHARED_NAME,
 190         .id             = 0,
 191         .num_resources  = ARRAY_SIZE(mv64x60_mpsc_shared_resources),
 192         .resource       = mv64x60_mpsc_shared_resources,
 193         .dev = {
 194                 .platform_data = &mv64x60_mpsc_shared_pdata,
 195         },
 196 };
 197
 198 static struct mpsc_pdata mv64x60_mpsc0_pdata = {
 199         .mirror_regs            = 0,
 200         .cache_mgmt             = 0,
 201         .max_idle               = 0,
 202         .default_baud           = 9600,
 203         .default_bits           = 8,
 204         .default_parity         = 'n',
 205         .default_flow           = 'n',
 206         .chr_1_val              = 0x00000000,
 207         .chr_2_val              = 0x00000000,
 208         .chr_10_val             = 0x00000003,
 209         .mpcr_val               = 0,
 210         .bcr_val                = 0,
 211         .brg_can_tune           = 0,
 212         .brg_clk_src            = 8,            /* Default to TCLK */
 213         .brg_clk_freq           = 100000000,    /* Default to 100 MHz */
 214 };
 215
 216 static struct resource mv64x60_mpsc0_resources[] = {
 217         /* Do not change the order of the IORESOURCE_MEM resources */
 218         [0] = {
 219                 .name   = "mpsc 0 base",
 220                 .start  = MV64x60_MPSC_0_OFFSET,
 221                 .end    = MV64x60_MPSC_0_OFFSET + MPSC_REG_BLOCK_SIZE - 1,
 222                 .flags  = IORESOURCE_MEM,
 223         },
 224         [1] = {
 225                 .name   = "sdma 0 base",
 226                 .start  = MV64x60_SDMA_0_OFFSET,
 227                 .end    = MV64x60_SDMA_0_OFFSET + MPSC_SDMA_REG_BLOCK_SIZE - 1,
 228                 .flags  = IORESOURCE_MEM,
 229         },
 230         [2] = {
 231                 .name   = "brg 0 base",
 232                 .start  = MV64x60_BRG_0_OFFSET,
 233                 .end    = MV64x60_BRG_0_OFFSET + MPSC_BRG_REG_BLOCK_SIZE - 1,
 234                 .flags  = IORESOURCE_MEM,
 235         },
 236         [3] = {
 237                 .name   = "sdma 0 irq",
 238                 .start  = MV64x60_IRQ_SDMA_0,
 239                 .end    = MV64x60_IRQ_SDMA_0,
 240                 .flags  = IORESOURCE_IRQ,
 241         },
 242 };
 243
 244 static struct platform_device mpsc0_device = {
 245         .name           = MPSC_CTLR_NAME,
 246         .id             = 0,
 247         .num_resources  = ARRAY_SIZE(mv64x60_mpsc0_resources),
 248         .resource       = mv64x60_mpsc0_resources,
 249         .dev = {
 250                 .platform_data = &mv64x60_mpsc0_pdata,
 251         },
 252 };
 253
 254 static struct mpsc_pdata mv64x60_mpsc1_pdata = {
 255         .mirror_regs            = 0,
 256         .cache_mgmt             = 0,
 257         .max_idle               = 0,
 258         .default_baud           = 9600,
 259         .default_bits           = 8,
 260         .default_parity         = 'n',
 261         .default_flow           = 'n',
 262         .chr_1_val              = 0x00000000,
 263         .chr_1_val              = 0x00000000,
 264         .chr_2_val              = 0x00000000,
 265         .chr_10_val             = 0x00000003,
 266         .mpcr_val               = 0,
 267         .bcr_val                = 0,
 268         .brg_can_tune           = 0,
 269         .brg_clk_src            = 8,            /* Default to TCLK */
 270         .brg_clk_freq           = 100000000,    /* Default to 100 MHz */
 271 };
 272
 273 static struct resource mv64x60_mpsc1_resources[] = {
 274         /* Do not change the order of the IORESOURCE_MEM resources */
 275         [0] = {
 276                 .name   = "mpsc 1 base",
 277                 .start  = MV64x60_MPSC_1_OFFSET,
 278                 .end    = MV64x60_MPSC_1_OFFSET + MPSC_REG_BLOCK_SIZE - 1,
 279                 .flags  = IORESOURCE_MEM,
 280         },
 281         [1] = {
 282                 .name   = "sdma 1 base",
 283                 .start  = MV64x60_SDMA_1_OFFSET,
 284                 .end    = MV64x60_SDMA_1_OFFSET + MPSC_SDMA_REG_BLOCK_SIZE - 1,
 285                 .flags  = IORESOURCE_MEM,
 286         },
 287         [2] = {
 288                 .name   = "brg 1 base",
 289                 .start  = MV64x60_BRG_1_OFFSET,
 290                 .end    = MV64x60_BRG_1_OFFSET + MPSC_BRG_REG_BLOCK_SIZE - 1,
 291                 .flags  = IORESOURCE_MEM,
 292         },
 293         [3] = {
 294                 .name   = "sdma 1 irq",
 295                 .start  = MV64360_IRQ_SDMA_1,
 296                 .end    = MV64360_IRQ_SDMA_1,
 297                 .flags  = IORESOURCE_IRQ,
 298         },
 299 };
 300
 301 static struct platform_device mpsc1_device = {
 302         .name           = MPSC_CTLR_NAME,
 303         .id             = 1,
 304         .num_resources  = ARRAY_SIZE(mv64x60_mpsc1_resources),
 305         .resource       = mv64x60_mpsc1_resources,
 306         .dev = {
 307                 .platform_data = &mv64x60_mpsc1_pdata,
 308         },
 309 };
 310 #endif
 311
 312 #ifdef CONFIG_MV643XX_ETH
 313 static struct resource mv64x60_eth_shared_resources[] = {
 314         [0] = {
 315                 .name   = "ethernet shared base",
 316                 .start  = MV643XX_ETH_SHARED_REGS,
 317                 .end    = MV643XX_ETH_SHARED_REGS +
 318                                         MV643XX_ETH_SHARED_REGS_SIZE - 1,
 319                 .flags  = IORESOURCE_MEM,
 320         },
 321 };
 322
 323 static struct platform_device mv64x60_eth_shared_device = {
 324         .name           = MV643XX_ETH_SHARED_NAME,
 325         .id             = 0,
 326         .num_resources  = ARRAY_SIZE(mv64x60_eth_shared_resources),
 327         .resource       = mv64x60_eth_shared_resources,
 328 };
 329
 330 #ifdef CONFIG_MV643XX_ETH_0
 331 static struct resource mv64x60_eth0_resources[] = {
 332         [0] = {
 333                 .name   = "eth0 irq",
 334                 .start  = MV64x60_IRQ_ETH_0,
 335                 .end    = MV64x60_IRQ_ETH_0,
 336                 .flags  = IORESOURCE_IRQ,
 337         },
 338 };
 339
 340 static struct mv643xx_eth_platform_data eth0_pd;
 341
 342 static struct platform_device eth0_device = {
 343         .name           = MV643XX_ETH_NAME,
 344         .id             = 0,
 345         .num_resources  = ARRAY_SIZE(mv64x60_eth0_resources),
 346         .resource       = mv64x60_eth0_resources,
 347         .dev = {
 348                 .platform_data = &eth0_pd,
 349         },
 350 };
 351 #endif
 352
 353 #ifdef CONFIG_MV643XX_ETH_1
 354 static struct resource mv64x60_eth1_resources[] = {
 355         [0] = {
 356                 .name   = "eth1 irq",
 357                 .start  = MV64x60_IRQ_ETH_1,
 358                 .end    = MV64x60_IRQ_ETH_1,
 359                 .flags  = IORESOURCE_IRQ,
 360         },
 361 };
 362
 363 static struct mv643xx_eth_platform_data eth1_pd;
 364
 365 static struct platform_device eth1_device = {
 366         .name           = MV643XX_ETH_NAME,
 367         .id             = 1,
 368         .num_resources  = ARRAY_SIZE(mv64x60_eth1_resources),
 369         .resource       = mv64x60_eth1_resources,
 370         .dev = {
 371                 .platform_data = &eth1_pd,
 372         },
 373 };
 374 #endif
 375
 376 #ifdef CONFIG_MV643XX_ETH_2
 377 static struct resource mv64x60_eth2_resources[] = {
 378         [0] = {
 379                 .name   = "eth2 irq",
 380                 .start  = MV64x60_IRQ_ETH_2,
 381                 .end    = MV64x60_IRQ_ETH_2,
 382                 .flags  = IORESOURCE_IRQ,
 383         },
 384 };
 385
 386 static struct mv643xx_eth_platform_data eth2_pd;
 387
 388 static struct platform_device eth2_device = {
 389         .name           = MV643XX_ETH_NAME,
 390         .id             = 2,
 391         .num_resources  = ARRAY_SIZE(mv64x60_eth2_resources),
 392         .resource       = mv64x60_eth2_resources,
 393         .dev = {
 394                 .platform_data = &eth2_pd,
 395         },
 396 };
 397 #endif
 398 #endif
 399
 400 #ifdef  CONFIG_I2C_MV64XXX
 401 static struct mv64xxx_i2c_pdata mv64xxx_i2c_pdata = {
 402         .freq_m                 = 8,
 403         .freq_n                 = 3,
 404         .timeout                = 1000, /* Default timeout of 1 second */
 405         .retries                = 1,
 406 };
 407
 408 static struct resource mv64xxx_i2c_resources[] = {
 409         /* Do not change the order of the IORESOURCE_MEM resources */
 410         [0] = {
 411                 .name   = "mv64xxx i2c base",
 412                 .start  = MV64XXX_I2C_OFFSET,
 413                 .end    = MV64XXX_I2C_OFFSET + MV64XXX_I2C_REG_BLOCK_SIZE - 1,
 414                 .flags  = IORESOURCE_MEM,
 415         },
 416         [1] = {
 417                 .name   = "mv64xxx i2c irq",
 418                 .start  = MV64x60_IRQ_I2C,
 419                 .end    = MV64x60_IRQ_I2C,
 420                 .flags  = IORESOURCE_IRQ,
 421         },
 422 };
 423
 424 static struct platform_device i2c_device = {
 425         .name           = MV64XXX_I2C_CTLR_NAME,
 426         .id             = 0,
 427         .num_resources  = ARRAY_SIZE(mv64xxx_i2c_resources),
 428         .resource       = mv64xxx_i2c_resources,
 429         .dev = {
 430                 .platform_data = &mv64xxx_i2c_pdata,
 431         },
 432 };
 433 #endif
 434
 435 static struct platform_device *mv64x60_pd_devs[] __initdata = {
 436 #ifdef CONFIG_SERIAL_MPSC
 437         &mpsc_shared_device,
 438         &mpsc0_device,
 439         &mpsc1_device,
 440 #endif
 441 #ifdef CONFIG_MV643XX_ETH
 442         &mv64x60_eth_shared_device,
 443 #endif
 444 #ifdef CONFIG_MV643XX_ETH_0
 445         &eth0_device,
 446 #endif
 447 #ifdef CONFIG_MV643XX_ETH_1
 448         &eth1_device,
 449 #endif
 450 #ifdef CONFIG_MV643XX_ETH_2
 451         &eth2_device,
 452 #endif
 453 #ifdef  CONFIG_I2C_MV64XXX
 454         &i2c_device,
 455 #endif
 456 };
 457
 458 /*
 459  *****************************************************************************
 460  *
 461  *      Bridge Initialization Routines
 462  *
 463  *****************************************************************************
 464  */
 465 /*
 466  * mv64x60_init()
 467  *
 468  * Initialze the bridge based on setting passed in via 'si'.  The bridge
 469  * handle, 'bh', will be set so that it can be used to make subsequent
 470  * calls to routines in this file.
 471  */
 472 int __init
 473 mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si)
 474 {
 475         u32     mem_windows[MV64x60_CPU2MEM_WINDOWS][2];
 476
 477         if (ppc_md.progress)
 478                 ppc_md.progress("mv64x60 initialization", 0x0);
 479
 480         spin_lock_init(&mv64x60_lock);
 481         mv64x60_early_init(bh, si);
 482
 483         if (mv64x60_get_type(bh) || mv64x60_setup_for_chip(bh)) {
 484                 iounmap(bh->v_base);
 485                 bh->v_base = 0;
 486                 if (ppc_md.progress)
 487                         ppc_md.progress("mv64x60_init: Can't determine chip",0);
 488                 return -1;
 489         }
 490
 491         bh->ci->disable_all_windows(bh, si);
 492         mv64x60_get_mem_windows(bh, mem_windows);
 493         mv64x60_config_cpu2mem_windows(bh, si, mem_windows);
 494
 495         if (bh->ci->config_io2mem_windows)
 496                 bh->ci->config_io2mem_windows(bh, si, mem_windows);
 497         if (bh->ci->set_mpsc2regs_window)
 498                 bh->ci->set_mpsc2regs_window(bh, si->phys_reg_base);
 499
 500         if (si->pci_1.enable_bus) {
 501                 bh->io_base_b = (u32)ioremap(si->pci_1.pci_io.cpu_base,
 502                         si->pci_1.pci_io.size);
 503                 isa_io_base = bh->io_base_b;
 504         }
 505
 506         if (si->pci_0.enable_bus) {
 507                 bh->io_base_a = (u32)ioremap(si->pci_0.pci_io.cpu_base,
 508                         si->pci_0.pci_io.size);
 509                 isa_io_base = bh->io_base_a;
 510
 511                 mv64x60_alloc_hose(bh, MV64x60_PCI0_CONFIG_ADDR,
 512                         MV64x60_PCI0_CONFIG_DATA, &bh->hose_a);
 513                 mv64x60_config_resources(bh->hose_a, &si->pci_0, bh->io_base_a);
 514                 mv64x60_config_pci_params(bh->hose_a, &si->pci_0);
 515
 516                 mv64x60_config_cpu2pci_windows(bh, &si->pci_0, 0);
 517                 mv64x60_config_pci2mem_windows(bh, bh->hose_a, &si->pci_0, 0,
 518                         mem_windows);
 519                 bh->ci->set_pci2regs_window(bh, bh->hose_a, 0,
 520                         si->phys_reg_base);
 521         }
 522
 523         if (si->pci_1.enable_bus) {
 524                 mv64x60_alloc_hose(bh, MV64x60_PCI1_CONFIG_ADDR,
 525                         MV64x60_PCI1_CONFIG_DATA, &bh->hose_b);
 526                 mv64x60_config_resources(bh->hose_b, &si->pci_1, bh->io_base_b);
 527                 mv64x60_config_pci_params(bh->hose_b, &si->pci_1);
 528
 529                 mv64x60_config_cpu2pci_windows(bh, &si->pci_1, 1);
 530                 mv64x60_config_pci2mem_windows(bh, bh->hose_b, &si->pci_1, 1,
 531                         mem_windows);
 532                 bh->ci->set_pci2regs_window(bh, bh->hose_b, 1,
 533                         si->phys_reg_base);
 534         }
 535
 536         bh->ci->chip_specific_init(bh, si);
 537         mv64x60_pd_fixup(bh, mv64x60_pd_devs, ARRAY_SIZE(mv64x60_pd_devs));
 538
 539         return 0;
 540 }
 541
 542 /*
 543  * mv64x60_early_init()
 544  *
 545  * Do some bridge work that must take place before we start messing with
 546  * the bridge for real.
 547  */
 548 void __init
 549 mv64x60_early_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si)
 550 {
 551         struct pci_controller   hose_a, hose_b;
 552
 553         memset(bh, 0, sizeof(*bh));
 554
 555         bh->p_base = si->phys_reg_base;
 556         bh->v_base = ioremap(bh->p_base, MV64x60_INTERNAL_SPACE_SIZE);
 557
 558         mv64x60_bridge_pbase = bh->p_base;
 559         mv64x60_bridge_vbase = bh->v_base;
 560
 561         /* Assuming pci mode [reserved] bits 4:5 on 64260 are 0 */
 562         bh->pci_mode_a = mv64x60_read(bh, MV64x60_PCI0_MODE) &
 563                 MV64x60_PCIMODE_MASK;
 564         bh->pci_mode_b = mv64x60_read(bh, MV64x60_PCI1_MODE) &
 565                 MV64x60_PCIMODE_MASK;
 566
 567         /* Need temporary hose structs to call mv64x60_set_bus() */
 568         memset(&hose_a, 0, sizeof(hose_a));
 569         memset(&hose_b, 0, sizeof(hose_b));
 570         setup_indirect_pci_nomap(&hose_a, bh->v_base + MV64x60_PCI0_CONFIG_ADDR,
 571                 bh->v_base + MV64x60_PCI0_CONFIG_DATA);
 572         setup_indirect_pci_nomap(&hose_b, bh->v_base + MV64x60_PCI1_CONFIG_ADDR,
 573                 bh->v_base + MV64x60_PCI1_CONFIG_DATA);
 574         bh->hose_a = &hose_a;
 575         bh->hose_b = &hose_b;
 576
 577         mv64x60_set_bus(bh, 0, 0);
 578         mv64x60_set_bus(bh, 1, 0);
 579
 580         bh->hose_a = NULL;
 581         bh->hose_b = NULL;
 582
 583         /* Clear bit 0 of PCI addr decode control so PCI->CPU remap 1:1 */
 584         mv64x60_clr_bits(bh, MV64x60_PCI0_PCI_DECODE_CNTL, 0x00000001);
 585         mv64x60_clr_bits(bh, MV64x60_PCI1_PCI_DECODE_CNTL, 0x00000001);
 586
 587         /* Bit 12 MUST be 0; set bit 27--don't auto-update cpu remap regs */
 588         mv64x60_clr_bits(bh, MV64x60_CPU_CONFIG, (1<<12));
 589         mv64x60_set_bits(bh, MV64x60_CPU_CONFIG, (1<<27));
 590
 591         mv64x60_set_bits(bh, MV64x60_PCI0_TO_RETRY, 0xffff);
 592         mv64x60_set_bits(bh, MV64x60_PCI1_TO_RETRY, 0xffff);
 593
 594         return;
 595 }
 596
 597 /*
 598  *****************************************************************************
 599  *
 600  *      Window Config Routines
 601  *
 602  *****************************************************************************
 603  */
 604 /*
 605  * mv64x60_get_32bit_window()
 606  *
 607  * Determine the base address and size of a 32-bit window on the bridge.
 608  */
 609 void __init
 610 mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window,
 611         u32 *base, u32 *size)
 612 {
 613         u32     val, base_reg, size_reg, base_bits, size_bits;
 614         u32     (*get_from_field)(u32 val, u32 num_bits);
 615
 616         base_reg = bh->ci->window_tab_32bit[window].base_reg;
 617
 618         if (base_reg != 0) {
 619                 size_reg  = bh->ci->window_tab_32bit[window].size_reg;
 620                 base_bits = bh->ci->window_tab_32bit[window].base_bits;
 621                 size_bits = bh->ci->window_tab_32bit[window].size_bits;
 622                 get_from_field= bh->ci->window_tab_32bit[window].get_from_field;
 623
 624                 val = mv64x60_read(bh, base_reg);
 625                 *base = get_from_field(val, base_bits);
 626
 627                 if (size_reg != 0) {
 628                         val = mv64x60_read(bh, size_reg);
 629                         val = get_from_field(val, size_bits);
 630                         *size = bh->ci->untranslate_size(*base, val, size_bits);
 631                 }
 632                 else
 633                         *size = 0;
 634         }
 635         else {
 636                 *base = 0;
 637                 *size = 0;
 638         }
 639
 640         pr_debug("get 32bit window: %d, base: 0x%x, size: 0x%x\n",
 641                 window, *base, *size);
 642
 643         return;
 644 }
 645
 646 /*
 647  * mv64x60_set_32bit_window()
 648  *
 649  * Set the base address and size of a 32-bit window on the bridge.
 650  */
 651 void __init
 652 mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window,
 653         u32 base, u32 size, u32 other_bits)
 654 {
 655         u32     val, base_reg, size_reg, base_bits, size_bits;
 656         u32     (*map_to_field)(u32 val, u32 num_bits);
 657
 658         pr_debug("set 32bit window: %d, base: 0x%x, size: 0x%x, other: 0x%x\n",
 659                 window, base, size, other_bits);
 660
 661         base_reg = bh->ci->window_tab_32bit[window].base_reg;
 662
 663         if (base_reg != 0) {
 664                 size_reg  = bh->ci->window_tab_32bit[window].size_reg;
 665                 base_bits = bh->ci->window_tab_32bit[window].base_bits;
 666                 size_bits = bh->ci->window_tab_32bit[window].size_bits;
 667                 map_to_field = bh->ci->window_tab_32bit[window].map_to_field;
 668
 669                 val = map_to_field(base, base_bits) | other_bits;
 670                 mv64x60_write(bh, base_reg, val);
 671
 672                 if (size_reg != 0) {
 673                         val = bh->ci->translate_size(base, size, size_bits);
 674                         val = map_to_field(val, size_bits);
 675                         mv64x60_write(bh, size_reg, val);
 676                 }
 677
 678                 (void)mv64x60_read(bh, base_reg); /* Flush FIFO */
 679         }
 680
 681         return;
 682 }
 683
 684 /*
 685  * mv64x60_get_64bit_window()
 686  *
 687  * Determine the base address and size of a 64-bit window on the bridge.
 688  */
 689 void __init
 690 mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window,
 691         u32 *base_hi, u32 *base_lo, u32 *size)
 692 {
 693         u32     val, base_lo_reg, size_reg, base_lo_bits, size_bits;
 694         u32     (*get_from_field)(u32 val, u32 num_bits);
 695
 696         base_lo_reg = bh->ci->window_tab_64bit[window].base_lo_reg;
 697
 698         if (base_lo_reg != 0) {
 699                 size_reg = bh->ci->window_tab_64bit[window].size_reg;
 700                 base_lo_bits = bh->ci->window_tab_64bit[window].base_lo_bits;
 701                 size_bits = bh->ci->window_tab_64bit[window].size_bits;
 702                 get_from_field= bh->ci->window_tab_64bit[window].get_from_field;
 703
 704                 *base_hi = mv64x60_read(bh,
 705                         bh->ci->window_tab_64bit[window].base_hi_reg);
 706
 707                 val = mv64x60_read(bh, base_lo_reg);
 708                 *base_lo = get_from_field(val, base_lo_bits);
 709
 710                 if (size_reg != 0) {
 711                         val = mv64x60_read(bh, size_reg);
 712                         val = get_from_field(val, size_bits);
 713                         *size = bh->ci->untranslate_size(*base_lo, val,
 714                                                                 size_bits);
 715                 }
 716                 else
 717                         *size = 0;
 718         }
 719         else {
 720                 *base_hi = 0;
 721                 *base_lo = 0;
 722                 *size = 0;
 723         }
 724
 725         pr_debug("get 64bit window: %d, base hi: 0x%x, base lo: 0x%x, "
 726                 "size: 0x%x\n", window, *base_hi, *base_lo, *size);
 727
 728         return;
 729 }
 730
 731 /*
 732  * mv64x60_set_64bit_window()
 733  *
 734  * Set the base address and size of a 64-bit window on the bridge.
 735  */
 736 void __init
 737 mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window,
 738         u32 base_hi, u32 base_lo, u32 size, u32 other_bits)
 739 {
 740         u32     val, base_lo_reg, size_reg, base_lo_bits, size_bits;
 741         u32     (*map_to_field)(u32 val, u32 num_bits);
 742
 743         pr_debug("set 64bit window: %d, base hi: 0x%x, base lo: 0x%x, "
 744                 "size: 0x%x, other: 0x%x\n",
 745                 window, base_hi, base_lo, size, other_bits);
 746
 747         base_lo_reg = bh->ci->window_tab_64bit[window].base_lo_reg;
 748
 749         if (base_lo_reg != 0) {
 750                 size_reg = bh->ci->window_tab_64bit[window].size_reg;
 751                 base_lo_bits = bh->ci->window_tab_64bit[window].base_lo_bits;
 752                 size_bits = bh->ci->window_tab_64bit[window].size_bits;
 753                 map_to_field = bh->ci->window_tab_64bit[window].map_to_field;
 754
 755                 mv64x60_write(bh, bh->ci->window_tab_64bit[window].base_hi_reg,
 756                         base_hi);
 757
 758                 val = map_to_field(base_lo, base_lo_bits) | other_bits;
 759                 mv64x60_write(bh, base_lo_reg, val);
 760
 761                 if (size_reg != 0) {
 762                         val = bh->ci->translate_size(base_lo, size, size_bits);
 763                         val = map_to_field(val, size_bits);
 764                         mv64x60_write(bh, size_reg, val);
 765                 }
 766
 767                 (void)mv64x60_read(bh, base_lo_reg); /* Flush FIFO */
 768         }
 769
 770         return;
 771 }
 772
 773 /*
 774  * mv64x60_mask()
 775  *
 776  * Take the high-order 'num_bits' of 'val' & mask off low bits.
 777  */
 778 u32 __init
 779 mv64x60_mask(u32 val, u32 num_bits)
 780 {
 781         return val & (0xffffffff << (32 - num_bits));
 782 }
 783
 784 /*
 785  * mv64x60_shift_left()
 786  *
 787  * Take the low-order 'num_bits' of 'val', shift left to align at bit 31 (MSB).
 788  */
 789 u32 __init
 790 mv64x60_shift_left(u32 val, u32 num_bits)
 791 {
 792         return val << (32 - num_bits);
 793 }
 794
 795 /*
 796  * mv64x60_shift_right()
 797  *
 798  * Take the high-order 'num_bits' of 'val', shift right to align at bit 0 (LSB).
 799  */
 800 u32 __init
 801 mv64x60_shift_right(u32 val, u32 num_bits)
 802 {
 803         return val >> (32 - num_bits);
 804 }
 805
 806 /*
 807  *****************************************************************************
 808  *
 809  *      Chip Identification Routines
 810  *
 811  *****************************************************************************
 812  */
 813 /*
 814  * mv64x60_get_type()
 815  *
 816  * Determine the type of bridge chip we have.
 817  */
 818 int __init
 819 mv64x60_get_type(struct mv64x60_handle *bh)
 820 {
 821         struct pci_controller hose;
 822         u16     val;
 823         u8      save_exclude;
 824
 825         memset(&hose, 0, sizeof(hose));
 826         setup_indirect_pci_nomap(&hose, bh->v_base + MV64x60_PCI0_CONFIG_ADDR,
 827                 bh->v_base + MV64x60_PCI0_CONFIG_DATA);
 828
 829         save_exclude = mv64x60_pci_exclude_bridge;
 830         mv64x60_pci_exclude_bridge = 0;
 831         /* Sanity check of bridge's Vendor ID */
 832         early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);
 833
 834         if (val != PCI_VENDOR_ID_MARVELL) {
 835                 mv64x60_pci_exclude_bridge = save_exclude;
 836                 return -1;
 837         }
 838
 839         /* Get the revision of the chip */
 840         early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_CLASS_REVISION,
 841                 &val);
 842         bh->rev = (u32)(val & 0xff);
 843
 844         /* Figure out the type of Marvell bridge it is */
 845         early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &val);
 846         mv64x60_pci_exclude_bridge = save_exclude;
 847
 848         switch (val) {
 849         case PCI_DEVICE_ID_MARVELL_GT64260:
 850                 switch (bh->rev) {
 851                 case GT64260_REV_A:
 852                         bh->type = MV64x60_TYPE_GT64260A;
 853                         break;
 854
 855                 default:
 856                         printk(KERN_WARNING "Unsupported GT64260 rev %04x\n",
 857                                 bh->rev);
 858                         /* Assume its similar to a 'B' rev and fallthru */
 859                 case GT64260_REV_B:
 860                         bh->type = MV64x60_TYPE_GT64260B;
 861                         break;
 862                 }
 863                 break;
 864
 865         case PCI_DEVICE_ID_MARVELL_MV64360:
 866                 /* Marvell won't tell me how to distinguish a 64361 & 64362 */
 867                 bh->type = MV64x60_TYPE_MV64360;
 868                 break;
 869
 870         case PCI_DEVICE_ID_MARVELL_MV64460:
 871                 bh->type = MV64x60_TYPE_MV64460;
 872                 break;
 873
 874         default:
 875                 printk(KERN_ERR "Unknown Marvell bridge type %04x\n", val);
 876                 return -1;
 877         }
 878
 879         /* Hang onto bridge type & rev for PIC code */
 880         mv64x60_bridge_type = bh->type;
 881         mv64x60_bridge_rev = bh->rev;
 882
 883         return 0;
 884 }
 885
 886 /*
 887  * mv64x60_setup_for_chip()
 888  *
 889  * Set 'bh' to use the proper set of routine for the bridge chip that we have.
 890  */
 891 int __init
 892 mv64x60_setup_for_chip(struct mv64x60_handle *bh)
 893 {
 894         int     rc = 0;
 895
 896         /* Set up chip-specific info based on the chip/bridge type */
 897         switch(bh->type) {
 898         case MV64x60_TYPE_GT64260A:
 899                 bh->ci = &gt64260a_ci;
 900                 break;
 901
 902         case MV64x60_TYPE_GT64260B:
 903                 bh->ci = &gt64260b_ci;
 904                 break;
 905
 906         case MV64x60_TYPE_MV64360:
 907                 bh->ci = &mv64360_ci;
 908                 break;
 909
 910         case MV64x60_TYPE_MV64460:
 911                 bh->ci = &mv64460_ci;
 912                 break;
 913
 914         case MV64x60_TYPE_INVALID:
 915         default:
 916                 if (ppc_md.progress)
 917                         ppc_md.progress("mv64x60: Unsupported bridge", 0x0);
 918                 printk(KERN_ERR "mv64x60: Unsupported bridge\n");
 919                 rc = -1;
 920         }
 921
 922         return rc;
 923 }
 924
 925 /*
 926  * mv64x60_get_bridge_vbase()
 927  *
 928  * Return the virtual address of the bridge's registers.
 929  */
 930 void *
 931 mv64x60_get_bridge_vbase(void)
 932 {
 933         return mv64x60_bridge_vbase;
 934 }
 935
 936 /*
 937  * mv64x60_get_bridge_type()
 938  *
 939  * Return the type of bridge on the platform.
 940  */
 941 u32
 942 mv64x60_get_bridge_type(void)
 943 {
 944         return mv64x60_bridge_type;
 945 }
 946
 947 /*
 948  * mv64x60_get_bridge_rev()
 949  *
 950  * Return the revision of the bridge on the platform.
 951  */
 952 u32
 953 mv64x60_get_bridge_rev(void)
 954 {
 955         return mv64x60_bridge_rev;
 956 }
 957
 958 /*
 959  *****************************************************************************
 960  *
 961  *      System Memory Window Related Routines
 962  *
 963  *****************************************************************************
 964  */
 965 /*
 966  * mv64x60_get_mem_size()
 967  *
 968  * Calculate the amount of memory that the memory controller is set up for.
 969  * This should only be used by board-specific code if there is no other
 970  * way to determine the amount of memory in the system.
 971  */
 972 u32 __init
 973 mv64x60_get_mem_size(u32 bridge_base, u32 chip_type)
 974 {
 975         struct mv64x60_handle   bh;
 976         u32     mem_windows[MV64x60_CPU2MEM_WINDOWS][2];
 977         u32     rc = 0;
 978
 979         memset(&bh, 0, sizeof(bh));
 980
 981         bh.type = chip_type;
 982         bh.v_base = (void *)bridge_base;
 983
 984         if (!mv64x60_setup_for_chip(&bh)) {
 985                 mv64x60_get_mem_windows(&bh, mem_windows);
 986                 rc = mv64x60_calc_mem_size(&bh, mem_windows);
 987         }
 988
 989         return rc;
 990 }
 991
 992 /*
 993  * mv64x60_get_mem_windows()
 994  *
 995  * Get the values in the memory controller & return in the 'mem_windows' array.
 996  */
 997 void __init
 998 mv64x60_get_mem_windows(struct mv64x60_handle *bh,
 999         u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1000 {
1001         u32     i, win;
1002
1003         for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
1004                 if (bh->ci->is_enabled_32bit(bh, win))
1005                         mv64x60_get_32bit_window(bh, win,
1006                                 &mem_windows[i][0], &mem_windows[i][1]);
1007                 else {
1008                         mem_windows[i][0] = 0;
1009                         mem_windows[i][1] = 0;
1010                 }
1011
1012         return;
1013 }
1014
1015 /*
1016  * mv64x60_calc_mem_size()
1017  *
1018  * Using the memory controller register values in 'mem_windows', determine
1019  * how much memory it is set up for.
1020  */
1021 u32 __init
1022 mv64x60_calc_mem_size(struct mv64x60_handle *bh,
1023         u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1024 {
1025         u32     i, total = 0;
1026
1027         for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++)
1028                 total += mem_windows[i][1];
1029
1030         return total;
1031 }
1032
1033 /*
1034  *****************************************************************************
1035  *
1036  *      CPU->System MEM, PCI Config Routines
1037  *
1038  *****************************************************************************
1039  */
1040 /*
1041  * mv64x60_config_cpu2mem_windows()
1042  *
1043  * Configure CPU->Memory windows on the bridge.
1044  */
1045 static u32 prot_tab[] __initdata = {
1046         MV64x60_CPU_PROT_0_WIN, MV64x60_CPU_PROT_1_WIN,
1047         MV64x60_CPU_PROT_2_WIN, MV64x60_CPU_PROT_3_WIN
1048 };
1049
1050 static u32 cpu_snoop_tab[] __initdata = {
1051         MV64x60_CPU_SNOOP_0_WIN, MV64x60_CPU_SNOOP_1_WIN,
1052         MV64x60_CPU_SNOOP_2_WIN, MV64x60_CPU_SNOOP_3_WIN
1053 };
1054
1055 void __init
1056 mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh,
1057         struct mv64x60_setup_info *si,
1058         u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1059 {
1060         u32     i, win;
1061
1062         /* Set CPU protection & snoop windows */
1063         for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
1064                 if (bh->ci->is_enabled_32bit(bh, win)) {
1065                         mv64x60_set_32bit_window(bh, prot_tab[i],
1066                                 mem_windows[i][0], mem_windows[i][1],
1067                                 si->cpu_prot_options[i]);
1068                         bh->ci->enable_window_32bit(bh, prot_tab[i]);
1069
1070                         if (bh->ci->window_tab_32bit[cpu_snoop_tab[i]].
1071                                                                 base_reg != 0) {
1072                                 mv64x60_set_32bit_window(bh, cpu_snoop_tab[i],
1073                                         mem_windows[i][0], mem_windows[i][1],
1074                                         si->cpu_snoop_options[i]);
1075                                 bh->ci->enable_window_32bit(bh,
1076                                         cpu_snoop_tab[i]);
1077                         }
1078
1079                 }
1080
1081         return;
1082 }
1083
1084 /*
1085  * mv64x60_config_cpu2pci_windows()
1086  *
1087  * Configure the CPU->PCI windows for one of the PCI buses.
1088  */
1089 static u32 win_tab[2][4] __initdata = {
1090         { MV64x60_CPU2PCI0_IO_WIN, MV64x60_CPU2PCI0_MEM_0_WIN,
1091           MV64x60_CPU2PCI0_MEM_1_WIN, MV64x60_CPU2PCI0_MEM_2_WIN },
1092         { MV64x60_CPU2PCI1_IO_WIN, MV64x60_CPU2PCI1_MEM_0_WIN,
1093           MV64x60_CPU2PCI1_MEM_1_WIN, MV64x60_CPU2PCI1_MEM_2_WIN },
1094 };
1095
1096 static u32 remap_tab[2][4] __initdata = {
1097         { MV64x60_CPU2PCI0_IO_REMAP_WIN, MV64x60_CPU2PCI0_MEM_0_REMAP_WIN,
1098           MV64x60_CPU2PCI0_MEM_1_REMAP_WIN, MV64x60_CPU2PCI0_MEM_2_REMAP_WIN },
1099         { MV64x60_CPU2PCI1_IO_REMAP_WIN, MV64x60_CPU2PCI1_MEM_0_REMAP_WIN,
1100           MV64x60_CPU2PCI1_MEM_1_REMAP_WIN, MV64x60_CPU2PCI1_MEM_2_REMAP_WIN }
1101 };
1102
1103 void __init
1104 mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh,
1105         struct mv64x60_pci_info *pi, u32 bus)
1106 {
1107         int     i;
1108
1109         if (pi->pci_io.size > 0) {
1110                 mv64x60_set_32bit_window(bh, win_tab[bus][0],
1111                         pi->pci_io.cpu_base, pi->pci_io.size, pi->pci_io.swap);
1112                 mv64x60_set_32bit_window(bh, remap_tab[bus][0],
1113                         pi->pci_io.pci_base_lo, 0, 0);
1114                 bh->ci->enable_window_32bit(bh, win_tab[bus][0]);
1115         }
1116         else /* Actually, the window should already be disabled */
1117                 bh->ci->disable_window_32bit(bh, win_tab[bus][0]);
1118
1119         for (i=0; i<3; i++)
1120                 if (pi->pci_mem[i].size > 0) {
1121                         mv64x60_set_32bit_window(bh, win_tab[bus][i+1],
1122                                 pi->pci_mem[i].cpu_base, pi->pci_mem[i].size,
1123                                 pi->pci_mem[i].swap);
1124                         mv64x60_set_64bit_window(bh, remap_tab[bus][i+1],
1125                                 pi->pci_mem[i].pci_base_hi,
1126                                 pi->pci_mem[i].pci_base_lo, 0, 0);
1127                         bh->ci->enable_window_32bit(bh, win_tab[bus][i+1]);
1128                 }
1129                 else /* Actually, the window should already be disabled */
1130                         bh->ci->disable_window_32bit(bh, win_tab[bus][i+1]);
1131
1132         return;
1133 }
1134
1135 /*
1136  *****************************************************************************
1137  *
1138  *      PCI->System MEM Config Routines
1139  *
1140  *****************************************************************************
1141  */
1142 /*
1143  * mv64x60_config_pci2mem_windows()
1144  *
1145  * Configure the PCI->Memory windows on the bridge.
1146  */
1147 static u32 pci_acc_tab[2][4] __initdata = {
1148         { MV64x60_PCI02MEM_ACC_CNTL_0_WIN, MV64x60_PCI02MEM_ACC_CNTL_1_WIN,
1149           MV64x60_PCI02MEM_ACC_CNTL_2_WIN, MV64x60_PCI02MEM_ACC_CNTL_3_WIN },
1150         { MV64x60_PCI12MEM_ACC_CNTL_0_WIN, MV64x60_PCI12MEM_ACC_CNTL_1_WIN,
1151           MV64x60_PCI12MEM_ACC_CNTL_2_WIN, MV64x60_PCI12MEM_ACC_CNTL_3_WIN }
1152 };
1153
1154 static u32 pci_snoop_tab[2][4] __initdata = {
1155         { MV64x60_PCI02MEM_SNOOP_0_WIN, MV64x60_PCI02MEM_SNOOP_1_WIN,
1156           MV64x60_PCI02MEM_SNOOP_2_WIN, MV64x60_PCI02MEM_SNOOP_3_WIN },
1157         { MV64x60_PCI12MEM_SNOOP_0_WIN, MV64x60_PCI12MEM_SNOOP_1_WIN,
1158           MV64x60_PCI12MEM_SNOOP_2_WIN, MV64x60_PCI12MEM_SNOOP_3_WIN }
1159 };
1160
1161 static u32 pci_size_tab[2][4] __initdata = {
1162         { MV64x60_PCI0_MEM_0_SIZE, MV64x60_PCI0_MEM_1_SIZE,
1163           MV64x60_PCI0_MEM_2_SIZE, MV64x60_PCI0_MEM_3_SIZE },
1164         { MV64x60_PCI1_MEM_0_SIZE, MV64x60_PCI1_MEM_1_SIZE,
1165           MV64x60_PCI1_MEM_2_SIZE, MV64x60_PCI1_MEM_3_SIZE }
1166 };
1167
1168 void __init
1169 mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh,
1170         struct pci_controller *hose, struct mv64x60_pci_info *pi,
1171         u32 bus, u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1172 {
1173         u32     i, win;
1174
1175         /*
1176          * Set the access control, snoop, BAR size, and window base addresses.
1177          * PCI->MEM windows base addresses will match exactly what the
1178          * CPU->MEM windows are.
1179          */
1180         for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
1181                 if (bh->ci->is_enabled_32bit(bh, win)) {
1182                         mv64x60_set_64bit_window(bh,
1183                                 pci_acc_tab[bus][i], 0,
1184                                 mem_windows[i][0], mem_windows[i][1],
1185                                 pi->acc_cntl_options[i]);
1186                         bh->ci->enable_window_64bit(bh, pci_acc_tab[bus][i]);
1187
1188                         if (bh->ci->window_tab_64bit[
1189                                 pci_snoop_tab[bus][i]].base_lo_reg != 0) {
1190
1191                                 mv64x60_set_64bit_window(bh,
1192                                         pci_snoop_tab[bus][i], 0,
1193                                         mem_windows[i][0], mem_windows[i][1],
1194                                         pi->snoop_options[i]);
1195                                 bh->ci->enable_window_64bit(bh,
1196                                         pci_snoop_tab[bus][i]);
1197                         }
1198
1199                         bh->ci->set_pci2mem_window(hose, bus, i,
1200                                 mem_windows[i][0]);
1201                         mv64x60_write(bh, pci_size_tab[bus][i],
1202                                 mv64x60_mask(mem_windows[i][1] - 1, 20));
1203
1204                         /* Enable the window */
1205                         mv64x60_clr_bits(bh, ((bus == 0) ?
1206                                 MV64x60_PCI0_BAR_ENABLE :
1207                                 MV64x60_PCI1_BAR_ENABLE), (1 << i));
1208                 }
1209
1210         return;
1211 }
1212
1213 /*
1214  *****************************************************************************
1215  *
1216  *      Hose & Resource Alloc/Init Routines
1217  *
1218  *****************************************************************************
1219  */
1220 /*
1221  * mv64x60_alloc_hoses()
1222  *
1223  * Allocate the PCI hose structures for the bridge's PCI buses.
1224  */
1225 void __init
1226 mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr, u32 cfg_data,
1227         struct pci_controller **hose)
1228 {
1229         *hose = pcibios_alloc_controller();
1230         setup_indirect_pci_nomap(*hose, bh->v_base + cfg_addr,
1231                 bh->v_base + cfg_data);
1232         return;
1233 }
1234
1235 /*
1236  * mv64x60_config_resources()
1237  *
1238  * Calculate the offsets, etc. for the hose structures to reflect all of
1239  * the address remapping that happens as you go from CPU->PCI and PCI->MEM.
1240  */
1241 void __init
1242 mv64x60_config_resources(struct pci_controller *hose,
1243         struct mv64x60_pci_info *pi, u32 io_base)
1244 {
1245         int             i;
1246         /* 2 hoses; 4 resources/hose; string <= 64 bytes */
1247         static char     s[2][4][64];
1248
1249         if (pi->pci_io.size != 0) {
1250                 sprintf(s[hose->index][0], "PCI hose %d I/O Space",
1251                         hose->index);
1252                 pci_init_resource(&hose->io_resource, io_base - isa_io_base,
1253                         io_base - isa_io_base + pi->pci_io.size - 1,
1254                         IORESOURCE_IO, s[hose->index][0]);
1255                 hose->io_space.start = pi->pci_io.pci_base_lo;
1256                 hose->io_space.end = pi->pci_io.pci_base_lo + pi->pci_io.size-1;
1257                 hose->io_base_phys = pi->pci_io.cpu_base;
1258                 hose->io_base_virt = (void *)isa_io_base;
1259         }
1260
1261         for (i=0; i<3; i++)
1262                 if (pi->pci_mem[i].size != 0) {
1263                         sprintf(s[hose->index][i+1], "PCI hose %d MEM Space %d",
1264                                 hose->index, i);
1265                         pci_init_resource(&hose->mem_resources[i],
1266                                 pi->pci_mem[i].cpu_base,
1267                                 pi->pci_mem[i].cpu_base + pi->pci_mem[i].size-1,
1268                                 IORESOURCE_MEM, s[hose->index][i+1]);
1269                 }
1270
1271         hose->mem_space.end = pi->pci_mem[0].pci_base_lo +
1272                                                 pi->pci_mem[0].size - 1;
1273         hose->pci_mem_offset = pi->pci_mem[0].cpu_base -
1274                                                 pi->pci_mem[0].pci_base_lo;
1275         return;
1276 }
1277
1278 /*
1279  * mv64x60_config_pci_params()
1280  *
1281  * Configure a hose's PCI config space parameters.
1282  */
1283 void __init
1284 mv64x60_config_pci_params(struct pci_controller *hose,
1285         struct mv64x60_pci_info *pi)
1286 {
1287         u32     devfn;
1288         u16     u16_val;
1289         u8      save_exclude;
1290
1291         devfn = PCI_DEVFN(0,0);
1292
1293         save_exclude = mv64x60_pci_exclude_bridge;
1294         mv64x60_pci_exclude_bridge = 0;
1295
1296         /* Set class code to indicate host bridge */
1297         u16_val = PCI_CLASS_BRIDGE_HOST; /* 0x0600 (host bridge) */
1298         early_write_config_word(hose, 0, devfn, PCI_CLASS_DEVICE, u16_val);
1299
1300         /* Enable bridge to be PCI master & respond to PCI MEM cycles */
1301         early_read_config_word(hose, 0, devfn, PCI_COMMAND, &u16_val);
1302         u16_val &= ~(PCI_COMMAND_IO | PCI_COMMAND_INVALIDATE |
1303                 PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
1304         u16_val |= pi->pci_cmd_bits | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
1305         early_write_config_word(hose, 0, devfn, PCI_COMMAND, u16_val);
1306
1307         /* Set latency timer, cache line size, clear BIST */
1308         u16_val = (pi->latency_timer << 8) | (L1_CACHE_LINE_SIZE >> 2);
1309         early_write_config_word(hose, 0, devfn, PCI_CACHE_LINE_SIZE, u16_val);
1310
1311         mv64x60_pci_exclude_bridge = save_exclude;
1312         return;
1313 }
1314
1315 /*
1316  *****************************************************************************
1317  *
1318  *      PCI Related Routine
1319  *
1320  *****************************************************************************
1321  */
1322 /*
1323  * mv64x60_set_bus()
1324  *
1325  * Set the bus number for the hose directly under the bridge.
1326  */
1327 void __init
1328 mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus)
1329 {
1330         struct pci_controller   *hose;
1331         u32     pci_mode, p2p_cfg, pci_cfg_offset, val;
1332         u8      save_exclude;
1333
1334         if (bus == 0) {
1335                 pci_mode = bh->pci_mode_a;
1336                 p2p_cfg = MV64x60_PCI0_P2P_CONFIG;
1337                 pci_cfg_offset = 0x64;
1338                 hose = bh->hose_a;
1339         }
1340         else {
1341                 pci_mode = bh->pci_mode_b;
1342                 p2p_cfg = MV64x60_PCI1_P2P_CONFIG;
1343                 pci_cfg_offset = 0xe4;
1344                 hose = bh->hose_b;
1345         }
1346
1347         child_bus &= 0xff;
1348         val = mv64x60_read(bh, p2p_cfg);
1349
1350         if (pci_mode == MV64x60_PCIMODE_CONVENTIONAL) {
1351                 val &= 0xe0000000; /* Force dev num to 0, turn off P2P bridge */
1352                 val |= (child_bus << 16) | 0xff;
1353                 mv64x60_write(bh, p2p_cfg, val);
1354                 (void)mv64x60_read(bh, p2p_cfg); /* Flush FIFO */
1355         }
1356         else { /* PCI-X */
1357                 /*
1358                  * Need to use the current bus/dev number (that's in the
1359                  * P2P CONFIG reg) to access the bridge's pci config space.
1360                  */
1361                 save_exclude = mv64x60_pci_exclude_bridge;
1362                 mv64x60_pci_exclude_bridge = 0;
1363                 early_write_config_dword(hose, (val & 0x00ff0000) >> 16,
1364                         PCI_DEVFN(((val & 0x1f000000) >> 24), 0),
1365                         pci_cfg_offset, child_bus << 8);
1366                 mv64x60_pci_exclude_bridge = save_exclude;
1367         }
1368
1369         return;
1370 }
1371
1372 /*
1373  * mv64x60_pci_exclude_device()
1374  *
1375  * This routine is used to make the bridge not appear when the
1376  * PCI subsystem is accessing PCI devices (in PCI config space).
1377  */
1378 int
1379 mv64x60_pci_exclude_device(u8 bus, u8 devfn)
1380 {
1381         struct pci_controller   *hose;
1382
1383         hose = pci_bus_to_hose(bus);
1384
1385         /* Skip slot 0 on both hoses */
1386         if ((mv64x60_pci_exclude_bridge == 1) && (PCI_SLOT(devfn) == 0) &&
1387                 (hose->first_busno == bus))
1388
1389                 return PCIBIOS_DEVICE_NOT_FOUND;
1390         else
1391                 return PCIBIOS_SUCCESSFUL;
1392 } /* mv64x60_pci_exclude_device() */
1393
1394 /*
1395  *****************************************************************************
1396  *
1397  *      Platform Device Routines
1398  *
1399  *****************************************************************************
1400  */
1401
1402 /*
1403  * mv64x60_pd_fixup()
1404  *
1405  * Need to add the base addr of where the bridge's regs are mapped in the
1406  * physical addr space so drivers can ioremap() them.
1407  */
1408 void __init
1409 mv64x60_pd_fixup(struct mv64x60_handle *bh, struct platform_device *pd_devs[],
1410         u32 entries)
1411 {
1412         struct resource *r;
1413         u32             i, j;
1414
1415         for (i=0; i<entries; i++) {
1416                 j = 0;
1417
1418                 while ((r = platform_get_resource(pd_devs[i],IORESOURCE_MEM,j))
1419                         != NULL) {
1420
1421                         r->start += bh->p_base;
1422                         r->end += bh->p_base;
1423                         j++;
1424                 }
1425         }
1426
1427         return;
1428 }
1429
1430 /*
1431  * mv64x60_add_pds()
1432  *
1433  * Add the mv64x60 platform devices to the list of platform devices.
1434  */
1435 static int __init
1436 mv64x60_add_pds(void)
1437 {
1438         return platform_add_devices(mv64x60_pd_devs,
1439                 ARRAY_SIZE(mv64x60_pd_devs));
1440 }
1441 arch_initcall(mv64x60_add_pds);
1442
1443 /*
1444  *****************************************************************************
1445  *
1446  *      GT64260-Specific Routines
1447  *
1448  *****************************************************************************
1449  */
1450 /*
1451  * gt64260_translate_size()
1452  *
1453  * On the GT64260, the size register is really the "top" address of the window.
1454  */
1455 static u32 __init
1456 gt64260_translate_size(u32 base, u32 size, u32 num_bits)
1457 {
1458         return base + mv64x60_mask(size - 1, num_bits);
1459 }
1460
1461 /*
1462  * gt64260_untranslate_size()
1463  *
1464  * Translate the top address of a window into a window size.
1465  */
1466 static u32 __init
1467 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits)
1468 {
1469         if (size >= base)
1470                 size = size - base + (1 << (32 - num_bits));
1471         else
1472                 size = 0;
1473
1474         return size;
1475 }
1476
1477 /*
1478  * gt64260_set_pci2mem_window()
1479  *
1480  * The PCI->MEM window registers are actually in PCI config space so need
1481  * to set them by setting the correct config space BARs.
1482  */
1483 static u32 gt64260_reg_addrs[2][4] __initdata = {
1484         { 0x10, 0x14, 0x18, 0x1c }, { 0x90, 0x94, 0x98, 0x9c }
1485 };
1486
1487 static void __init
1488 gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window,
1489         u32 base)
1490 {
1491         u8      save_exclude;
1492
1493         pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window,
1494                 hose->index, base);
1495
1496         save_exclude = mv64x60_pci_exclude_bridge;
1497         mv64x60_pci_exclude_bridge = 0;
1498         early_write_config_dword(hose, 0, PCI_DEVFN(0, 0),
1499                 gt64260_reg_addrs[bus][window], mv64x60_mask(base, 20) | 0x8);
1500         mv64x60_pci_exclude_bridge = save_exclude;
1501
1502         return;
1503 }
1504
1505 /*
1506  * gt64260_set_pci2regs_window()
1507  *
1508  * Set where the bridge's registers appear in PCI MEM space.
1509  */
1510 static u32 gt64260_offset[2] __initdata = {0x20, 0xa0};
1511
1512 static void __init
1513 gt64260_set_pci2regs_window(struct mv64x60_handle *bh,
1514         struct pci_controller *hose, u32 bus, u32 base)
1515 {
1516         u8      save_exclude;
1517
1518         pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose->index,
1519                 base);
1520
1521         save_exclude = mv64x60_pci_exclude_bridge;
1522         mv64x60_pci_exclude_bridge = 0;
1523         early_write_config_dword(hose, 0, PCI_DEVFN(0,0), gt64260_offset[bus],
1524                 (base << 16));
1525         mv64x60_pci_exclude_bridge = save_exclude;
1526
1527         return;
1528 }
1529
1530 /*
1531  * gt64260_is_enabled_32bit()
1532  *
1533  * On a GT64260, a window is enabled iff its top address is >= to its base
1534  * address.
1535  */
1536 static u32 __init
1537 gt64260_is_enabled_32bit(struct mv64x60_handle *bh, u32 window)
1538 {
1539         u32     rc = 0;
1540
1541         if ((gt64260_32bit_windows[window].base_reg != 0) &&
1542                 (gt64260_32bit_windows[window].size_reg != 0) &&
1543                 ((mv64x60_read(bh, gt64260_32bit_windows[window].size_reg) &
1544                         ((1 << gt64260_32bit_windows[window].size_bits) - 1)) >=
1545                  (mv64x60_read(bh, gt64260_32bit_windows[window].base_reg) &
1546                         ((1 << gt64260_32bit_windows[window].base_bits) - 1))))
1547
1548                 rc = 1;
1549
1550         return rc;
1551 }
1552
1553 /*
1554  * gt64260_enable_window_32bit()
1555  *
1556  * On the GT64260, a window is enabled iff the top address is >= to the base
1557  * address of the window.  Since the window has already been configured by
1558  * the time this routine is called, we have nothing to do here.
1559  */
1560 static void __init
1561 gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window)
1562 {
1563         pr_debug("enable 32bit window: %d\n", window);
1564         return;
1565 }
1566
1567 /*
1568  * gt64260_disable_window_32bit()
1569  *
1570  * On a GT64260, you disable a window by setting its top address to be less
1571  * than its base address.
1572  */
1573 static void __init
1574 gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window)
1575 {
1576         pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
1577                 window, gt64260_32bit_windows[window].base_reg,
1578                 gt64260_32bit_windows[window].size_reg);
1579
1580         if ((gt64260_32bit_windows[window].base_reg != 0) &&
1581                 (gt64260_32bit_windows[window].size_reg != 0)) {
1582
1583                 /* To disable, make bottom reg higher than top reg */
1584                 mv64x60_write(bh, gt64260_32bit_windows[window].base_reg,0xfff);
1585                 mv64x60_write(bh, gt64260_32bit_windows[window].size_reg, 0);
1586         }
1587
1588         return;
1589 }
1590
1591 /*
1592  * gt64260_enable_window_64bit()
1593  *
1594  * On the GT64260, a window is enabled iff the top address is >= to the base
1595  * address of the window.  Since the window has already been configured by
1596  * the time this routine is called, we have nothing to do here.
1597  */
1598 static void __init
1599 gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window)
1600 {
1601         pr_debug("enable 64bit window: %d\n", window);
1602         return; /* Enabled when window configured (i.e., when top >= base) */
1603 }
1604
1605 /*
1606  * gt64260_disable_window_64bit()
1607  *
1608  * On a GT64260, you disable a window by setting its top address to be less
1609  * than its base address.
1610  */
1611 static void __init
1612 gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window)
1613 {
1614         pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
1615                 window, gt64260_64bit_windows[window].base_lo_reg,
1616                 gt64260_64bit_windows[window].size_reg);
1617
1618         if ((gt64260_64bit_windows[window].base_lo_reg != 0) &&
1619                 (gt64260_64bit_windows[window].size_reg != 0)) {
1620
1621                 /* To disable, make bottom reg higher than top reg */
1622                 mv64x60_write(bh, gt64260_64bit_windows[window].base_lo_reg,
1623                                                                         0xfff);
1624                 mv64x60_write(bh, gt64260_64bit_windows[window].base_hi_reg, 0);
1625                 mv64x60_write(bh, gt64260_64bit_windows[window].size_reg, 0);
1626         }
1627
1628         return;
1629 }
1630
1631 /*
1632  * gt64260_disable_all_windows()
1633  *
1634  * The GT64260 has several windows that aren't represented in the table of
1635  * windows at the top of this file.  This routine turns all of them off
1636  * except for the memory controller windows, of course.
1637  */
1638 static void __init
1639 gt64260_disable_all_windows(struct mv64x60_handle *bh,
1640         struct mv64x60_setup_info *si)
1641 {
1642         u32     i, preserve;
1643
1644         /* Disable 32bit windows (don't disable cpu->mem windows) */
1645         for (i=MV64x60_CPU2DEV_0_WIN; i<MV64x60_32BIT_WIN_COUNT; i++) {
1646                 if (i < 32)
1647                         preserve = si->window_preserve_mask_32_lo & (1 << i);
1648                 else
1649                         preserve = si->window_preserve_mask_32_hi & (1<<(i-32));
1650
1651                 if (!preserve)
1652                         gt64260_disable_window_32bit(bh, i);
1653         }
1654
1655         /* Disable 64bit windows */
1656         for (i=0; i<MV64x60_64BIT_WIN_COUNT; i++)
1657                 if (!(si->window_preserve_mask_64 & (1<<i)))
1658                         gt64260_disable_window_64bit(bh, i);
1659
1660         /* Turn off cpu protection windows not in gt64260_32bit_windows[] */
1661         mv64x60_write(bh, GT64260_CPU_PROT_BASE_4, 0xfff);
1662         mv64x60_write(bh, GT64260_CPU_PROT_SIZE_4, 0);
1663         mv64x60_write(bh, GT64260_CPU_PROT_BASE_5, 0xfff);
1664         mv64x60_write(bh, GT64260_CPU_PROT_SIZE_5, 0);
1665         mv64x60_write(bh, GT64260_CPU_PROT_BASE_6, 0xfff);
1666         mv64x60_write(bh, GT64260_CPU_PROT_SIZE_6, 0);
1667         mv64x60_write(bh, GT64260_CPU_PROT_BASE_7, 0xfff);
1668         mv64x60_write(bh, GT64260_CPU_PROT_SIZE_7, 0);
1669
1670         /* Turn off PCI->MEM access cntl wins not in gt64260_64bit_windows[] */
1671         mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_LO, 0xfff);
1672         mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_HI, 0);
1673         mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_SIZE, 0);
1674         mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_LO, 0xfff);
1675         mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_HI, 0);
1676         mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_SIZE, 0);
1677         mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_BASE_LO, 0xfff);
1678         mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_BASE_HI, 0);
1679         mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_SIZE, 0);
1680         mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_BASE_LO, 0xfff);
1681         mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_BASE_HI, 0);
1682         mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_SIZE, 0);
1683
1684         mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_LO, 0xfff);
1685         mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_HI, 0);
1686         mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_SIZE, 0);
1687         mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_LO, 0xfff);
1688         mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_HI, 0);
1689         mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_SIZE, 0);
1690         mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_BASE_LO, 0xfff);
1691         mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_BASE_HI, 0);
1692         mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_SIZE, 0);
1693         mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_BASE_LO, 0xfff);
1694         mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_BASE_HI, 0);
1695         mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_SIZE, 0);
1696
1697         /* Disable all PCI-><whatever> windows */
1698         mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x07fffdff);
1699         mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x07fffdff);
1700
1701         /*
1702          * Some firmwares enable a bunch of intr sources
1703          * for the PCI INT output pins.
1704          */
1705         mv64x60_write(bh, GT64260_IC_CPU_INTR_MASK_LO, 0);
1706         mv64x60_write(bh, GT64260_IC_CPU_INTR_MASK_HI, 0);
1707         mv64x60_write(bh, GT64260_IC_PCI0_INTR_MASK_LO, 0);
1708         mv64x60_write(bh, GT64260_IC_PCI0_INTR_MASK_HI, 0);
1709         mv64x60_write(bh, GT64260_IC_PCI1_INTR_MASK_LO, 0);
1710         mv64x60_write(bh, GT64260_IC_PCI1_INTR_MASK_HI, 0);
1711         mv64x60_write(bh, GT64260_IC_CPU_INT_0_MASK, 0);
1712         mv64x60_write(bh, GT64260_IC_CPU_INT_1_MASK, 0);
1713         mv64x60_write(bh, GT64260_IC_CPU_INT_2_MASK, 0);
1714         mv64x60_write(bh, GT64260_IC_CPU_INT_3_MASK, 0);
1715
1716         return;
1717 }
1718
1719 /*
1720  * gt64260a_chip_specific_init()
1721  *
1722  * Implement errata work arounds for the GT64260A.
1723  */
1724 static void __init
1725 gt64260a_chip_specific_init(struct mv64x60_handle *bh,
1726         struct mv64x60_setup_info *si)
1727 {
1728 #ifdef CONFIG_SERIAL_MPSC
1729         struct resource *r;
1730 #endif
1731 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1732         u32     val;
1733         u8      save_exclude;
1734 #endif
1735
1736         if (si->pci_0.enable_bus)
1737                 mv64x60_set_bits(bh, MV64x60_PCI0_CMD,
1738                         ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1739
1740         if (si->pci_1.enable_bus)
1741                 mv64x60_set_bits(bh, MV64x60_PCI1_CMD,
1742                         ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1743
1744         /*
1745          * Dave Wilhardt found that bit 4 in the PCI Command registers must
1746          * be set if you are using cache coherency.
1747          */
1748 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1749         /* Res #MEM-4 -- cpu read buffer to buffer 1 */
1750         if ((mv64x60_read(bh, MV64x60_CPU_MODE) & 0xf0) == 0x40)
1751                 mv64x60_set_bits(bh, GT64260_SDRAM_CONFIG, (1<<26));
1752
1753         save_exclude = mv64x60_pci_exclude_bridge;
1754         mv64x60_pci_exclude_bridge = 0;
1755         if (si->pci_0.enable_bus) {
1756                 early_read_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1757                         PCI_COMMAND, &val);
1758                 val |= PCI_COMMAND_INVALIDATE;
1759                 early_write_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1760                         PCI_COMMAND, val);
1761         }
1762
1763         if (si->pci_1.enable_bus) {
1764                 early_read_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1765                         PCI_COMMAND, &val);
1766                 val |= PCI_COMMAND_INVALIDATE;
1767                 early_write_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1768                         PCI_COMMAND, val);
1769         }
1770         mv64x60_pci_exclude_bridge = save_exclude;
1771 #endif
1772
1773         /* Disable buffer/descriptor snooping */
1774         mv64x60_clr_bits(bh, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1775         mv64x60_clr_bits(bh, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1776
1777 #ifdef CONFIG_SERIAL_MPSC
1778         mv64x60_mpsc0_pdata.mirror_regs = 1;
1779         mv64x60_mpsc0_pdata.cache_mgmt = 1;
1780         mv64x60_mpsc1_pdata.mirror_regs = 1;
1781         mv64x60_mpsc1_pdata.cache_mgmt = 1;
1782
1783         if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0))
1784                 != NULL) {
1785
1786                 r->start = MV64x60_IRQ_SDMA_0;
1787                 r->end = MV64x60_IRQ_SDMA_0;
1788         }
1789 #endif
1790
1791         return;
1792 }
1793
1794 /*
1795  * gt64260b_chip_specific_init()
1796  *
1797  * Implement errata work arounds for the GT64260B.
1798  */
1799 static void __init
1800 gt64260b_chip_specific_init(struct mv64x60_handle *bh,
1801         struct mv64x60_setup_info *si)
1802 {
1803 #ifdef CONFIG_SERIAL_MPSC
1804         struct resource *r;
1805 #endif
1806 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1807         u32     val;
1808         u8      save_exclude;
1809 #endif
1810
1811         if (si->pci_0.enable_bus)
1812                 mv64x60_set_bits(bh, MV64x60_PCI0_CMD,
1813                         ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1814
1815         if (si->pci_1.enable_bus)
1816                 mv64x60_set_bits(bh, MV64x60_PCI1_CMD,
1817                         ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1818
1819         /*
1820          * Dave Wilhardt found that bit 4 in the PCI Command registers must
1821          * be set if you are using cache coherency.
1822          */
1823 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1824         mv64x60_set_bits(bh, GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH, 0xf);
1825
1826         /* Res #MEM-4 -- cpu read buffer to buffer 1 */
1827         if ((mv64x60_read(bh, MV64x60_CPU_MODE) & 0xf0) == 0x40)
1828                 mv64x60_set_bits(bh, GT64260_SDRAM_CONFIG, (1<<26));
1829
1830         save_exclude = mv64x60_pci_exclude_bridge;
1831         mv64x60_pci_exclude_bridge = 0;
1832         if (si->pci_0.enable_bus) {
1833                 early_read_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1834                         PCI_COMMAND, &val);
1835                 val |= PCI_COMMAND_INVALIDATE;
1836                 early_write_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1837                         PCI_COMMAND, val);
1838         }
1839
1840         if (si->pci_1.enable_bus) {
1841                 early_read_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1842                         PCI_COMMAND, &val);
1843                 val |= PCI_COMMAND_INVALIDATE;
1844                 early_write_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1845                         PCI_COMMAND, val);
1846         }
1847         mv64x60_pci_exclude_bridge = save_exclude;
1848 #endif
1849
1850         /* Disable buffer/descriptor snooping */
1851         mv64x60_clr_bits(bh, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1852         mv64x60_clr_bits(bh, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1853
1854 #ifdef CONFIG_SERIAL_MPSC
1855         /*
1856          * The 64260B is not supposed to have the bug where the MPSC & ENET
1857          * can't access cache coherent regions.  However, testing has shown
1858          * that the MPSC, at least, still has this bug.
1859          */
1860         mv64x60_mpsc0_pdata.cache_mgmt = 1;
1861         mv64x60_mpsc1_pdata.cache_mgmt = 1;
1862
1863         if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0))
1864                 != NULL) {
1865
1866                 r->start = MV64x60_IRQ_SDMA_0;
1867                 r->end = MV64x60_IRQ_SDMA_0;
1868         }
1869 #endif
1870
1871         return;
1872 }
1873
1874 /*
1875  *****************************************************************************
1876  *
1877  *      MV64360-Specific Routines
1878  *
1879  *****************************************************************************
1880  */
1881 /*
1882  * mv64360_translate_size()
1883  *
1884  * On the MV64360, the size register is set similar to the size you get
1885  * from a pci config space BAR register.  That is, programmed from LSB to MSB
1886  * as a sequence of 1's followed by a sequence of 0's. IOW, "size -1" with the
1887  * assumption that the size is a power of 2.
1888  */
1889 static u32 __init
1890 mv64360_translate_size(u32 base_addr, u32 size, u32 num_bits)
1891 {
1892         return mv64x60_mask(size - 1, num_bits);
1893 }
1894
1895 /*
1896  * mv64360_untranslate_size()
1897  *
1898  * Translate the size register value of a window into a window size.
1899  */
1900 static u32 __init
1901 mv64360_untranslate_size(u32 base_addr, u32 size, u32 num_bits)
1902 {
1903         if (size > 0) {
1904                 size >>= (32 - num_bits);
1905                 size++;
1906                 size <<= (32 - num_bits);
1907         }
1908
1909         return size;
1910 }
1911
1912 /*
1913  * mv64360_set_pci2mem_window()
1914  *
1915  * The PCI->MEM window registers are actually in PCI config space so need
1916  * to set them by setting the correct config space BARs.
1917  */
1918 struct {
1919         u32     fcn;
1920         u32     base_hi_bar;
1921         u32     base_lo_bar;
1922 } static mv64360_reg_addrs[2][4] __initdata = {
1923         {{ 0, 0x14, 0x10 }, { 0, 0x1c, 0x18 },
1924          { 1, 0x14, 0x10 }, { 1, 0x1c, 0x18 }},
1925         {{ 0, 0x94, 0x90 }, { 0, 0x9c, 0x98 },
1926          { 1, 0x94, 0x90 }, { 1, 0x9c, 0x98 }}
1927 };
1928
1929 static void __init
1930 mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window,
1931         u32 base)
1932 {
1933         u8 save_exclude;
1934
1935         pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window,
1936                 hose->index, base);
1937
1938         save_exclude = mv64x60_pci_exclude_bridge;
1939         mv64x60_pci_exclude_bridge = 0;
1940         early_write_config_dword(hose, 0,
1941                 PCI_DEVFN(0, mv64360_reg_addrs[bus][window].fcn),
1942                 mv64360_reg_addrs[bus][window].base_hi_bar, 0);
1943         early_write_config_dword(hose, 0,
1944                 PCI_DEVFN(0, mv64360_reg_addrs[bus][window].fcn),
1945                 mv64360_reg_addrs[bus][window].base_lo_bar,
1946                 mv64x60_mask(base,20) | 0xc);
1947         mv64x60_pci_exclude_bridge = save_exclude;
1948
1949         return;
1950 }
1951
1952 /*
1953  * mv64360_set_pci2regs_window()
1954  *
1955  * Set where the bridge's registers appear in PCI MEM space.
1956  */
1957 static u32 mv64360_offset[2][2] __initdata = {{0x20, 0x24}, {0xa0, 0xa4}};
1958
1959 static void __init
1960 mv64360_set_pci2regs_window(struct mv64x60_handle *bh,
1961         struct pci_controller *hose, u32 bus, u32 base)
1962 {
1963         u8      save_exclude;
1964
1965         pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose->index,
1966                 base);
1967
1968         save_exclude = mv64x60_pci_exclude_bridge;
1969         mv64x60_pci_exclude_bridge = 0;
1970         early_write_config_dword(hose, 0, PCI_DEVFN(0,0),
1971                 mv64360_offset[bus][0], (base << 16));
1972         early_write_config_dword(hose, 0, PCI_DEVFN(0,0),
1973                 mv64360_offset[bus][1], 0);
1974         mv64x60_pci_exclude_bridge = save_exclude;
1975
1976         return;
1977 }
1978
1979 /*
1980  * mv64360_is_enabled_32bit()
1981  *
1982  * On a MV64360, a window is enabled by either clearing a bit in the
1983  * CPU BAR Enable reg or setting a bit in the window's base reg.
1984  * Note that this doesn't work for windows on the PCI slave side but we don't
1985  * check those so its okay.
1986  */
1987 static u32 __init
1988 mv64360_is_enabled_32bit(struct mv64x60_handle *bh, u32 window)
1989 {
1990         u32     extra, rc = 0;
1991
1992         if (((mv64360_32bit_windows[window].base_reg != 0) &&
1993                 (mv64360_32bit_windows[window].size_reg != 0)) ||
1994                 (window == MV64x60_CPU2SRAM_WIN)) {
1995
1996                 extra = mv64360_32bit_windows[window].extra;
1997
1998                 switch (extra & MV64x60_EXTRA_MASK) {
1999                 case MV64x60_EXTRA_CPUWIN_ENAB:
2000                         rc = (mv64x60_read(bh, MV64360_CPU_BAR_ENABLE) &
2001                                 (1 << (extra & 0x1f))) == 0;
2002                         break;
2003
2004                 case MV64x60_EXTRA_CPUPROT_ENAB:
2005                         rc = (mv64x60_read(bh,
2006                                 mv64360_32bit_windows[window].base_reg) &
2007                                         (1 << (extra & 0x1f))) != 0;
2008                         break;
2009
2010                 case MV64x60_EXTRA_ENET_ENAB:
2011                         rc = (mv64x60_read(bh, MV64360_ENET2MEM_BAR_ENABLE) &
2012                                 (1 << (extra & 0x7))) == 0;
2013                         break;
2014
2015                 case MV64x60_EXTRA_MPSC_ENAB:
2016                         rc = (mv64x60_read(bh, MV64360_MPSC2MEM_BAR_ENABLE) &
2017                                 (1 << (extra & 0x3))) == 0;
2018                         break;
2019
2020                 case MV64x60_EXTRA_IDMA_ENAB:
2021                         rc = (mv64x60_read(bh, MV64360_IDMA2MEM_BAR_ENABLE) &
2022                                 (1 << (extra & 0x7))) == 0;
2023                         break;
2024
2025                 default:
2026                         printk(KERN_ERR "mv64360_is_enabled: %s\n",
2027                                 "32bit table corrupted");
2028                 }
2029         }
2030
2031         return rc;
2032 }
2033
2034 /*
2035  * mv64360_enable_window_32bit()
2036  *
2037  * On a MV64360, a window is enabled by either clearing a bit in the
2038  * CPU BAR Enable reg or setting a bit in the window's base reg.
2039  */
2040 static void __init
2041 mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window)
2042 {
2043         u32     extra;
2044
2045         pr_debug("enable 32bit window: %d\n", window);
2046
2047         if (((mv64360_32bit_windows[window].base_reg != 0) &&
2048                 (mv64360_32bit_windows[window].size_reg != 0)) ||
2049                 (window == MV64x60_CPU2SRAM_WIN)) {
2050
2051                 extra = mv64360_32bit_windows[window].extra;
2052
2053                 switch (extra & MV64x60_EXTRA_MASK) {
2054                 case MV64x60_EXTRA_CPUWIN_ENAB:
2055                         mv64x60_clr_bits(bh, MV64360_CPU_BAR_ENABLE,
2056                                 (1 << (extra & 0x1f)));
2057                         break;
2058
2059                 case MV64x60_EXTRA_CPUPROT_ENAB:
2060                         mv64x60_set_bits(bh,
2061                                 mv64360_32bit_windows[window].base_reg,
2062                                 (1 << (extra & 0x1f)));
2063                         break;
2064
2065                 case MV64x60_EXTRA_ENET_ENAB:
2066                         mv64x60_clr_bits(bh, MV64360_ENET2MEM_BAR_ENABLE,
2067                                 (1 << (extra & 0x7)));
2068                         break;
2069
2070                 case MV64x60_EXTRA_MPSC_ENAB:
2071                         mv64x60_clr_bits(bh, MV64360_MPSC2MEM_BAR_ENABLE,
2072                                 (1 << (extra & 0x3)));
2073                         break;
2074
2075                 case MV64x60_EXTRA_IDMA_ENAB:
2076                         mv64x60_clr_bits(bh, MV64360_IDMA2MEM_BAR_ENABLE,
2077                                 (1 << (extra & 0x7)));
2078                         break;
2079
2080                 default:
2081                         printk(KERN_ERR "mv64360_enable: %s\n",
2082                                 "32bit table corrupted");
2083                 }
2084         }
2085
2086         return;
2087 }
2088
2089 /*
2090  * mv64360_disable_window_32bit()
2091  *
2092  * On a MV64360, a window is disabled by either setting a bit in the
2093  * CPU BAR Enable reg or clearing a bit in the window's base reg.
2094  */
2095 static void __init
2096 mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window)
2097 {
2098         u32     extra;
2099
2100         pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
2101                 window, mv64360_32bit_windows[window].base_reg,
2102                 mv64360_32bit_windows[window].size_reg);
2103
2104         if (((mv64360_32bit_windows[window].base_reg != 0) &&
2105                 (mv64360_32bit_windows[window].size_reg != 0)) ||
2106                 (window == MV64x60_CPU2SRAM_WIN)) {
2107
2108                 extra = mv64360_32bit_windows[window].extra;
2109
2110                 switch (extra & MV64x60_EXTRA_MASK) {
2111                 case MV64x60_EXTRA_CPUWIN_ENAB:
2112                         mv64x60_set_bits(bh, MV64360_CPU_BAR_ENABLE,
2113                                 (1 << (extra & 0x1f)));
2114                         break;
2115
2116                 case MV64x60_EXTRA_CPUPROT_ENAB:
2117                         mv64x60_clr_bits(bh,
2118                                 mv64360_32bit_windows[window].base_reg,
2119                                 (1 << (extra & 0x1f)));
2120                         break;
2121
2122                 case MV64x60_EXTRA_ENET_ENAB:
2123                         mv64x60_set_bits(bh, MV64360_ENET2MEM_BAR_ENABLE,
2124                                 (1 << (extra & 0x7)));
2125                         break;
2126
2127                 case MV64x60_EXTRA_MPSC_ENAB:
2128                         mv64x60_set_bits(bh, MV64360_MPSC2MEM_BAR_ENABLE,
2129                                 (1 << (extra & 0x3)));
2130                         break;
2131
2132                 case MV64x60_EXTRA_IDMA_ENAB:
2133                         mv64x60_set_bits(bh, MV64360_IDMA2MEM_BAR_ENABLE,
2134                                 (1 << (extra & 0x7)));
2135                         break;
2136
2137                 default:
2138                         printk(KERN_ERR "mv64360_disable: %s\n",
2139                                 "32bit table corrupted");
2140                 }
2141         }
2142
2143         return;
2144 }
2145
2146 /*
2147  * mv64360_enable_window_64bit()
2148  *
2149  * On the MV64360, a 64-bit window is enabled by setting a bit in the window's
2150  * base reg.
2151  */
2152 static void __init
2153 mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window)
2154 {
2155         pr_debug("enable 64bit window: %d\n", window);
2156
2157         if ((mv64360_64bit_windows[window].base_lo_reg!= 0) &&
2158                 (mv64360_64bit_windows[window].size_reg != 0)) {
2159
2160                 if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK)
2161                         == MV64x60_EXTRA_PCIACC_ENAB)
2162
2163                         mv64x60_set_bits(bh,
2164                                 mv64360_64bit_windows[window].base_lo_reg,
2165                                 (1 << (mv64360_64bit_windows[window].extra &
2166                                                                         0x1f)));
2167                 else
2168                         printk(KERN_ERR "mv64360_enable: %s\n",
2169                                 "64bit table corrupted");
2170         }
2171
2172         return;
2173 }
2174
2175 /*
2176  * mv64360_disable_window_64bit()
2177  *
2178  * On a MV64360, a 64-bit window is disabled by clearing a bit in the window's
2179  * base reg.
2180  */
2181 static void __init
2182 mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window)
2183 {
2184         pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
2185                 window, mv64360_64bit_windows[window].base_lo_reg,
2186                 mv64360_64bit_windows[window].size_reg);
2187
2188         if ((mv64360_64bit_windows[window].base_lo_reg != 0) &&
2189                 (mv64360_64bit_windows[window].size_reg != 0)) {
2190
2191                 if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK)
2192                         == MV64x60_EXTRA_PCIACC_ENAB)
2193
2194                         mv64x60_clr_bits(bh,
2195                                 mv64360_64bit_windows[window].base_lo_reg,
2196                                 (1 << (mv64360_64bit_windows[window].extra &
2197                                                                         0x1f)));
2198                 else
2199                         printk(KERN_ERR "mv64360_disable: %s\n",
2200                                 "64bit table corrupted");
2201         }
2202
2203         return;
2204 }
2205
2206 /*
2207  * mv64360_disable_all_windows()
2208  *
2209  * The MV64360 has a few windows that aren't represented in the table of
2210  * windows at the top of this file.  This routine turns all of them off
2211  * except for the memory controller windows, of course.
2212  */
2213 static void __init
2214 mv64360_disable_all_windows(struct mv64x60_handle *bh,
2215         struct mv64x60_setup_info *si)
2216 {
2217         u32     preserve, i;
2218
2219         /* Disable 32bit windows (don't disable cpu->mem windows) */
2220         for (i=MV64x60_CPU2DEV_0_WIN; i<MV64x60_32BIT_WIN_COUNT; i++) {
2221                 if (i < 32)
2222                         preserve = si->window_preserve_mask_32_lo & (1 << i);
2223                 else
2224                         preserve = si->window_preserve_mask_32_hi & (1<<(i-32));
2225
2226                 if (!preserve)
2227                         mv64360_disable_window_32bit(bh, i);
2228         }
2229
2230         /* Disable 64bit windows */
2231         for (i=0; i<MV64x60_64BIT_WIN_COUNT; i++)
2232                 if (!(si->window_preserve_mask_64 & (1<<i)))
2233                         mv64360_disable_window_64bit(bh, i);
2234
2235         /* Turn off PCI->MEM access cntl wins not in mv64360_64bit_windows[] */
2236         mv64x60_clr_bits(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_LO, 0);
2237         mv64x60_clr_bits(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_LO, 0);
2238         mv64x60_clr_bits(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_LO, 0);
2239         mv64x60_clr_bits(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_LO, 0);
2240
2241         /* Disable all PCI-><whatever> windows */
2242         mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x0000f9ff);
2243         mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x0000f9ff);
2244
2245         return;
2246 }
2247
2248 /*
2249  * mv64360_config_io2mem_windows()
2250  *
2251  * ENET, MPSC, and IDMA ctlrs on the MV64[34]60 have separate windows that
2252  * must be set up so that the respective ctlr can access system memory.
2253  */
2254 static u32 enet_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
2255         MV64x60_ENET2MEM_0_WIN, MV64x60_ENET2MEM_1_WIN,
2256         MV64x60_ENET2MEM_2_WIN, MV64x60_ENET2MEM_3_WIN,
2257 };
2258
2259 static u32 mpsc_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
2260         MV64x60_MPSC2MEM_0_WIN, MV64x60_MPSC2MEM_1_WIN,
2261         MV64x60_MPSC2MEM_2_WIN, MV64x60_MPSC2MEM_3_WIN,
2262 };
2263
2264 static u32 idma_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
2265         MV64x60_IDMA2MEM_0_WIN, MV64x60_IDMA2MEM_1_WIN,
2266         MV64x60_IDMA2MEM_2_WIN, MV64x60_IDMA2MEM_3_WIN,
2267 };
2268
2269 static u32 dram_selects[MV64x60_CPU2MEM_WINDOWS] __initdata =
2270         { 0xe, 0xd, 0xb, 0x7 };
2271
2272 static void __init
2273 mv64360_config_io2mem_windows(struct mv64x60_handle *bh,
2274         struct mv64x60_setup_info *si,
2275         u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
2276 {
2277         u32     i, win;
2278
2279         pr_debug("config_io2regs_windows: enet, mpsc, idma -> bridge regs\n");
2280
2281         mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_0, 0);
2282         mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_1, 0);
2283         mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_2, 0);
2284
2285         mv64x60_write(bh, MV64360_MPSC2MEM_ACC_PROT_0, 0);
2286         mv64x60_write(bh, MV64360_MPSC2MEM_ACC_PROT_1, 0);
2287
2288         mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_0, 0);
2289         mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_1, 0);
2290         mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_2, 0);
2291         mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_3, 0);
2292
2293         /* Assume that mem ctlr has no more windows than embedded I/O ctlr */
2294         for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
2295                 if (bh->ci->is_enabled_32bit(bh, win)) {
2296                         mv64x60_set_32bit_window(bh, enet_tab[i],
2297                                 mem_windows[i][0], mem_windows[i][1],
2298                                 (dram_selects[i] << 8) |
2299                                 (si->enet_options[i] & 0x3000));
2300                         bh->ci->enable_window_32bit(bh, enet_tab[i]);
2301
2302                         /* Give enet r/w access to memory region */
2303                         mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_0,
2304                                 (0x3 << (i << 1)));
2305                         mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_1,
2306                                 (0x3 << (i << 1)));
2307                         mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_2,
2308                                 (0x3 << (i << 1)));
2309
2310                         mv64x60_set_32bit_window(bh, mpsc_tab[i],
2311                                 mem_windows[i][0], mem_windows[i][1],
2312                                 (dram_selects[i] << 8) |
2313                                 (si->mpsc_options[i] & 0x3000));
2314                         bh->ci->enable_window_32bit(bh, mpsc_tab[i]);
2315
2316                         /* Give mpsc r/w access to memory region */
2317                         mv64x60_set_bits(bh, MV64360_MPSC2MEM_ACC_PROT_0,
2318                                 (0x3 << (i << 1)));
2319                         mv64x60_set_bits(bh, MV64360_MPSC2MEM_ACC_PROT_1,
2320                                 (0x3 << (i << 1)));
2321
2322                         mv64x60_set_32bit_window(bh, idma_tab[i],
2323                                 mem_windows[i][0], mem_windows[i][1],
2324                                 (dram_selects[i] << 8) |
2325                                 (si->idma_options[i] & 0x3000));
2326                         bh->ci->enable_window_32bit(bh, idma_tab[i]);
2327
2328                         /* Give idma r/w access to memory region */
2329                         mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_0,
2330                                 (0x3 << (i << 1)));
2331                         mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_1,
2332                                 (0x3 << (i << 1)));
2333                         mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_2,
2334                                 (0x3 << (i << 1)));
2335                         mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_3,
2336                                 (0x3 << (i << 1)));
2337                 }
2338
2339         return;
2340 }
2341
2342 /*
2343  * mv64360_set_mpsc2regs_window()
2344  *
2345  * MPSC has a window to the bridge's internal registers.  Call this routine
2346  * to change that window so it doesn't conflict with the windows mapping the
2347  * mpsc to system memory.
2348  */
2349 static void __init
2350 mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base)
2351 {
2352         pr_debug("set mpsc->internal regs, base: 0x%x\n", base);
2353
2354         mv64x60_write(bh, MV64360_MPSC2REGS_BASE, base & 0xffff0000);
2355         return;
2356 }
2357
2358 /*
2359  * mv64360_chip_specific_init()
2360  *
2361  * No errata work arounds for the MV64360 implemented at this point.
2362  */
2363 static void __init
2364 mv64360_chip_specific_init(struct mv64x60_handle *bh,
2365         struct mv64x60_setup_info *si)
2366 {
2367 #ifdef CONFIG_SERIAL_MPSC
2368         mv64x60_mpsc0_pdata.brg_can_tune = 1;
2369         mv64x60_mpsc0_pdata.cache_mgmt = 1;
2370         mv64x60_mpsc1_pdata.brg_can_tune = 1;
2371         mv64x60_mpsc1_pdata.cache_mgmt = 1;
2372 #endif
2373
2374         return;
2375 }
2376
2377 /*
2378  * mv64460_chip_specific_init()
2379  *
2380  * No errata work arounds for the MV64460 implemented at this point.
2381  */
2382 static void __init
2383 mv64460_chip_specific_init(struct mv64x60_handle *bh,
2384         struct mv64x60_setup_info *si)
2385 {
2386 #ifdef CONFIG_SERIAL_MPSC
2387         mv64x60_mpsc0_pdata.brg_can_tune = 1;
2388         mv64x60_mpsc1_pdata.brg_can_tune = 1;
2389 #endif
2390         return;
2391 }