arch/ppc/platforms/mpc866ads_setup.c

   1 /*arch/ppc/platforms/mpc885ads-setup.c
   2  *
   3  * Platform setup for the Freescale mpc885ads board
   4  *
   5  * Vitaly Bordug <vbordug@ru.mvista.com>
   6  *
   7  * Copyright 2005 MontaVista Software Inc.
   8  *
   9  * This file is licensed under the terms of the GNU General Public License
  10  * version 2. This program is licensed "as is" without any warranty of any
  11  * kind, whether express or implied.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16 #include <linux/param.h>
  17 #include <linux/string.h>
  18 #include <linux/ioport.h>
  19 #include <linux/device.h>
  20
  21 #include <linux/fs_enet_pd.h>
  22 #include <linux/fs_uart_pd.h>
  23 #include <linux/mii.h>
  24
  25 #include <asm/delay.h>
  26 #include <asm/io.h>
  27 #include <asm/machdep.h>
  28 #include <asm/page.h>
  29 #include <asm/processor.h>
  30 #include <asm/system.h>
  31 #include <asm/time.h>
  32 #include <asm/ppcboot.h>
  33 #include <asm/8xx_immap.h>
  34 #include <asm/commproc.h>
  35 #include <asm/ppc_sys.h>
  36 #include <asm/mpc8xx.h>
  37
  38 extern unsigned char __res[];
  39
  40 static void setup_fec1_ioports(void);
  41 static void setup_scc1_ioports(void);
  42 static void setup_smc1_ioports(void);
  43 static void setup_smc2_ioports(void);
  44
  45 static struct fs_mii_bus_info fec_mii_bus_info = {
  46         .method = fsmii_fec,
  47         .id = 0,
  48 };
  49
  50 static struct fs_mii_bus_info scc_mii_bus_info = {
  51         .method = fsmii_fixed,
  52         .id = 0,
  53         .i.fixed.speed = 10,
  54         .i.fixed.duplex = 0,
  55 };
  56
  57 static struct fs_platform_info mpc8xx_fec_pdata[] = {
  58         {
  59          .rx_ring = 128,
  60          .tx_ring = 16,
  61          .rx_copybreak = 240,
  62
  63          .use_napi = 1,
  64          .napi_weight = 17,
  65
  66          .phy_addr = 15,
  67          .phy_irq = -1,
  68
  69          .use_rmii = 0,
  70
  71          .bus_info = &fec_mii_bus_info,
  72          }
  73 };
  74
  75 static struct fs_platform_info mpc8xx_scc_pdata = {
  76         .rx_ring = 64,
  77         .tx_ring = 8,
  78         .rx_copybreak = 240,
  79
  80         .use_napi = 1,
  81         .napi_weight = 17,
  82
  83         .phy_addr = -1,
  84         .phy_irq = -1,
  85
  86         .bus_info = &scc_mii_bus_info,
  87
  88 };
  89
  90 static struct fs_uart_platform_info mpc866_uart_pdata[] = {
  91         [fsid_smc1_uart] = {
  92                 .brg            = 1,
  93                 .fs_no          = fsid_smc1_uart,
  94                 .init_ioports   = setup_smc1_ioports,
  95                 .tx_num_fifo    = 4,
  96                 .tx_buf_size    = 32,
  97                 .rx_num_fifo    = 4,
  98                 .rx_buf_size    = 32,
  99         },
 100         [fsid_smc2_uart] = {
 101                 .brg            = 2,
 102                 .fs_no          = fsid_smc2_uart,
 103                 .init_ioports   = setup_smc2_ioports,
 104                 .tx_num_fifo    = 4,
 105                 .tx_buf_size    = 32,
 106                 .rx_num_fifo    = 4,
 107                 .rx_buf_size    = 32,
 108         },
 109 };
 110
 111 void __init board_init(void)
 112 {
 113         volatile cpm8xx_t *cp = cpmp;
 114         unsigned *bcsr_io;
 115
 116         bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
 117
 118         if (bcsr_io == NULL) {
 119                 printk(KERN_CRIT "Could not remap BCSR1\n");
 120                 return;
 121         }
 122
 123 #ifdef CONFIG_SERIAL_CPM_SMC1
 124         cp->cp_simode &= ~(0xe0000000 >> 17);   /* brg1 */
 125         clrbits32(bcsr_io,(0x80000000 >> 7));
 126         cp->cp_smc[0].smc_smcm |= (SMCM_RX | SMCM_TX);
 127         cp->cp_smc[0].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
 128 #else
 129         setbits32(bcsr_io,(0x80000000 >> 7));
 130
 131         cp->cp_pbpar &= ~(0x000000c0);
 132         cp->cp_pbdir |= 0x000000c0;
 133         cp->cp_smc[0].smc_smcmr = 0;
 134         cp->cp_smc[0].smc_smce = 0;
 135 #endif
 136
 137 #ifdef CONFIG_SERIAL_CPM_SMC2
 138         cp->cp_simode &= ~(0xe0000000 >> 1);
 139         cp->cp_simode |= (0x20000000 >> 1);     /* brg2 */
 140         clrbits32(bcsr_io,(0x80000000 >> 13));
 141         cp->cp_smc[1].smc_smcm |= (SMCM_RX | SMCM_TX);
 142         cp->cp_smc[1].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
 143 #else
 144         clrbits32(bcsr_io,(0x80000000 >> 13));
 145         cp->cp_pbpar &= ~(0x00000c00);
 146         cp->cp_pbdir |= 0x00000c00;
 147         cp->cp_smc[1].smc_smcmr = 0;
 148         cp->cp_smc[1].smc_smce = 0;
 149 #endif
 150         iounmap(bcsr_io);
 151 }
 152
 153 static void setup_fec1_ioports(void)
 154 {
 155         immap_t *immap = (immap_t *) IMAP_ADDR;
 156
 157         setbits16(&immap->im_ioport.iop_pdpar, 0x1fff);
 158         setbits16(&immap->im_ioport.iop_pddir, 0x1fff);
 159 }
 160
 161 static void setup_scc1_ioports(void)
 162 {
 163         immap_t *immap = (immap_t *) IMAP_ADDR;
 164         unsigned *bcsr_io;
 165
 166         bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
 167
 168         if (bcsr_io == NULL) {
 169                 printk(KERN_CRIT "Could not remap BCSR1\n");
 170                 return;
 171         }
 172
 173         /* Enable the PHY.
 174          */
 175         clrbits32(bcsr_io,BCSR1_ETHEN);
 176
 177         /* Configure port A pins for Txd and Rxd.
 178          */
 179         /* Disable receive and transmit in case EPPC-Bug started it.
 180          */
 181         setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD);
 182         clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD);
 183         clrbits16(&immap->im_ioport.iop_paodr, PA_ENET_TXD);
 184
 185         /* Configure port C pins to enable CLSN and RENA.
 186          */
 187         clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
 188         clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
 189         setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
 190         /* Configure port A for TCLK and RCLK.
 191          */
 192         setbits16(&immap->im_ioport.iop_papar, PA_ENET_TCLK | PA_ENET_RCLK);
 193         clrbits16(&immap->im_ioport.iop_padir, PA_ENET_TCLK | PA_ENET_RCLK);
 194         clrbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA);
 195         clrbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA);
 196
 197         /* Configure Serial Interface clock routing.
 198          * First, clear all SCC bits to zero, then set the ones we want.
 199          */
 200         clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK);
 201         setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT);
 202
 203         /* In the original SCC enet driver the following code is placed at
 204         the end of the initialization */
 205         setbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA);
 206         setbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA);
 207
 208 }
 209
 210 static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
 211 {
 212         struct fs_platform_info *fpi = pdev->dev.platform_data;
 213
 214         volatile cpm8xx_t *cp;
 215         bd_t *bd = (bd_t *) __res;
 216         char *e;
 217         int i;
 218
 219         /* Get pointer to Communication Processor */
 220         cp = cpmp;
 221         switch (fs_no) {
 222         case fsid_fec1:
 223                 fpi = &mpc8xx_fec_pdata[0];
 224                 fpi->init_ioports = &setup_fec1_ioports;
 225
 226                 break;
 227         case fsid_scc1:
 228                 fpi = &mpc8xx_scc_pdata;
 229                 fpi->init_ioports = &setup_scc1_ioports;
 230
 231                 break;
 232         default:
 233                 printk(KERN_WARNING"Device %s is not supported!\n", pdev->name);
 234                 return;
 235         }
 236
 237         pdev->dev.platform_data = fpi;
 238         fpi->fs_no = fs_no;
 239
 240         e = (unsigned char *)&bd->bi_enetaddr;
 241         for (i = 0; i < 6; i++)
 242                 fpi->macaddr[i] = *e++;
 243
 244         fpi->macaddr[5 - pdev->id]++;
 245
 246 }
 247
 248 static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev,
 249                                            int idx)
 250 {
 251         /* This is for FEC devices only */
 252         if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec")))
 253                 return;
 254         mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
 255 }
 256
 257 static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev,
 258                                            int idx)
 259 {
 260         /* This is for SCC devices only */
 261         if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc")))
 262                 return;
 263
 264         mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
 265 }
 266
 267 static void setup_smc1_ioports(void)
 268 {
 269         immap_t *immap = (immap_t *) IMAP_ADDR;
 270         unsigned *bcsr_io;
 271         unsigned int iobits = 0x000000c0;
 272
 273         bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
 274
 275         if (bcsr_io == NULL) {
 276                 printk(KERN_CRIT "Could not remap BCSR1\n");
 277                 return;
 278         }
 279
 280         clrbits32(bcsr_io,BCSR1_RS232EN_1);
 281         iounmap(bcsr_io);
 282
 283         setbits32(&immap->im_cpm.cp_pbpar, iobits);
 284         clrbits32(&immap->im_cpm.cp_pbdir, iobits);
 285         clrbits16(&immap->im_cpm.cp_pbodr, iobits);
 286
 287 }
 288
 289 static void setup_smc2_ioports(void)
 290 {
 291         immap_t *immap = (immap_t *) IMAP_ADDR;
 292         unsigned *bcsr_io;
 293         unsigned int iobits = 0x00000c00;
 294
 295         bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
 296
 297         if (bcsr_io == NULL) {
 298                 printk(KERN_CRIT "Could not remap BCSR1\n");
 299                 return;
 300         }
 301
 302         clrbits32(bcsr_io,BCSR1_RS232EN_2);
 303
 304         iounmap(bcsr_io);
 305
 306 #ifndef CONFIG_SERIAL_CPM_ALT_SMC2
 307         setbits32(&immap->im_cpm.cp_pbpar, iobits);
 308         clrbits32(&immap->im_cpm.cp_pbdir, iobits);
 309         clrbits16(&immap->im_cpm.cp_pbodr, iobits);
 310 #else
 311         setbits16(&immap->im_ioport.iop_papar, iobits);
 312         clrbits16(&immap->im_ioport.iop_padir, iobits);
 313         clrbits16(&immap->im_ioport.iop_paodr, iobits);
 314 #endif
 315
 316 }
 317
 318 static void __init mpc866ads_fixup_uart_pdata(struct platform_device *pdev,
 319                                               int idx)
 320 {
 321         bd_t *bd = (bd_t *) __res;
 322         struct fs_uart_platform_info *pinfo;
 323         int num = ARRAY_SIZE(mpc866_uart_pdata);
 324
 325         int id = fs_uart_id_smc2fsid(idx);
 326
 327         /* no need to alter anything if console */
 328         if ((id <= num) && (!pdev->dev.platform_data)) {
 329                 pinfo = &mpc866_uart_pdata[id];
 330                 pinfo->uart_clk = bd->bi_intfreq;
 331                 pdev->dev.platform_data = pinfo;
 332         }
 333 }
 334
 335 static int mpc866ads_platform_notify(struct device *dev)
 336 {
 337         static const struct platform_notify_dev_map dev_map[] = {
 338                 {
 339                         .bus_id = "fsl-cpm-fec",
 340                         .rtn = mpc866ads_fixup_fec_enet_pdata,
 341                 },
 342                 {
 343                         .bus_id = "fsl-cpm-scc",
 344                         .rtn = mpc866ads_fixup_scc_enet_pdata,
 345                 },
 346                 {
 347                         .bus_id = "fsl-cpm-smc:uart",
 348                         .rtn = mpc866ads_fixup_uart_pdata
 349                 },
 350                 {
 351                         .bus_id = NULL
 352                 }
 353         };
 354
 355         platform_notify_map(dev_map,dev);
 356
 357         return 0;
 358 }
 359
 360 int __init mpc866ads_init(void)
 361 {
 362         printk(KERN_NOTICE "mpc866ads: Init\n");
 363
 364         platform_notify = mpc866ads_platform_notify;
 365
 366         ppc_sys_device_initfunc();
 367         ppc_sys_device_disable_all();
 368
 369 #ifdef MPC8xx_SECOND_ETH_SCC1
 370         ppc_sys_device_enable(MPC8xx_CPM_SCC1);
 371 #endif
 372         ppc_sys_device_enable(MPC8xx_CPM_FEC1);
 373
 374 /* Since either of the uarts could be used as console, they need to ready */
 375 #ifdef CONFIG_SERIAL_CPM_SMC1
 376         ppc_sys_device_enable(MPC8xx_CPM_SMC1);
 377         ppc_sys_device_setfunc(MPC8xx_CPM_SMC1, PPC_SYS_FUNC_UART);
 378 #endif
 379
 380 #ifdef CONFIG_SERIAL_CPM_SMC
 381         ppc_sys_device_enable(MPC8xx_CPM_SMC2);
 382         ppc_sys_device_setfunc(MPC8xx_CPM_SMC2, PPC_SYS_FUNC_UART);
 383 #endif
 384
 385         return 0;
 386 }
 387
 388 /*
 389    To prevent confusion, console selection is gross:
 390    by 0 assumed SMC1 and by 1 assumed SMC2
 391  */
 392 struct platform_device* early_uart_get_pdev(int index)
 393 {
 394         bd_t *bd = (bd_t *) __res;
 395         struct fs_uart_platform_info *pinfo;
 396
 397         struct platform_device* pdev = NULL;
 398         if(index) { /*assume SMC2 here*/
 399                 pdev = &ppc_sys_platform_devices[MPC8xx_CPM_SMC2];
 400                 pinfo = &mpc866_uart_pdata[1];
 401         } else { /*over SMC1*/
 402                 pdev = &ppc_sys_platform_devices[MPC8xx_CPM_SMC1];
 403                 pinfo = &mpc866_uart_pdata[0];
 404         }
 405
 406         pinfo->uart_clk = bd->bi_intfreq;
 407         pdev->dev.platform_data = pinfo;
 408         ppc_sys_fixup_mem_resource(pdev, IMAP_ADDR);
 409         return NULL;
 410 }
 411
 412 arch_initcall(mpc866ads_init);