arch/ppc/platforms/4xx/yucca.h

   1 /*
   2  * Yucca board definitions
   3  *
   4  * Roland Dreier <rolandd@cisco.com> (based on luan.h by Matt Porter)
   5  *
   6  * Copyright 2004-2005 MontaVista Software Inc.
   7  * Copyright (c) 2005 Cisco Systems.  All rights reserved.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  *
  14  */
  15
  16 #ifdef __KERNEL__
  17 #ifndef __ASM_YUCCA_H__
  18 #define __ASM_YUCCA_H__
  19
  20 #include <linux/config.h>
  21 #include <platforms/4xx/ppc440spe.h>
  22
  23 /* F/W TLB mapping used in bootloader glue to reset EMAC */
  24 #define PPC44x_EMAC0_MR0        0xa0000800
  25
  26 /* Location of MAC addresses in PIBS image */
  27 #define PIBS_FLASH_BASE         0xffe00000
  28 #define PIBS_MAC_BASE           (PIBS_FLASH_BASE+0x1b0400)
  29
  30 /* External timer clock frequency */
  31 #define YUCCA_TMR_CLK           25000000
  32
  33 /*
  34  * FPGA registers
  35  */
  36 #define YUCCA_FPGA_REG_BASE                     0x00000004e2000000ULL
  37 #define YUCCA_FPGA_REG_SIZE                     0x24
  38
  39 #define FPGA_REG1A                              0x1a
  40
  41 #define FPGA_REG1A_PE0_GLED                     0x8000
  42 #define FPGA_REG1A_PE1_GLED                     0x4000
  43 #define FPGA_REG1A_PE2_GLED                     0x2000
  44 #define FPGA_REG1A_PE0_YLED                     0x1000
  45 #define FPGA_REG1A_PE1_YLED                     0x0800
  46 #define FPGA_REG1A_PE2_YLED                     0x0400
  47 #define FPGA_REG1A_PE0_PWRON                    0x0200
  48 #define FPGA_REG1A_PE1_PWRON                    0x0100
  49 #define FPGA_REG1A_PE2_PWRON                    0x0080
  50 #define FPGA_REG1A_PE0_REFCLK_ENABLE            0x0040
  51 #define FPGA_REG1A_PE1_REFCLK_ENABLE            0x0020
  52 #define FPGA_REG1A_PE2_REFCLK_ENABLE            0x0010
  53 #define FPGA_REG1A_PE_SPREAD0                   0x0008
  54 #define FPGA_REG1A_PE_SPREAD1                   0x0004
  55 #define FPGA_REG1A_PE_SELSOURCE_0               0x0002
  56 #define FPGA_REG1A_PE_SELSOURCE_1               0x0001
  57
  58 #define FPGA_REG1C                              0x1c
  59
  60 #define FPGA_REG1C_PE0_ROOTPOINT                0x8000
  61 #define FPGA_REG1C_PE1_ENDPOINT                 0x4000
  62 #define FPGA_REG1C_PE2_ENDPOINT                 0x2000
  63 #define FPGA_REG1C_PE0_PRSNT                    0x1000
  64 #define FPGA_REG1C_PE1_PRSNT                    0x0800
  65 #define FPGA_REG1C_PE2_PRSNT                    0x0400
  66 #define FPGA_REG1C_PE0_WAKE                     0x0080
  67 #define FPGA_REG1C_PE1_WAKE                     0x0040
  68 #define FPGA_REG1C_PE2_WAKE                     0x0020
  69 #define FPGA_REG1C_PE0_PERST                    0x0010
  70 #define FPGA_REG1C_PE1_PERST                    0x0008
  71 #define FPGA_REG1C_PE2_PERST                    0x0004
  72
  73 /*
  74  * Serial port defines
  75  */
  76 #define RS_TABLE_SIZE   3
  77
  78 /* PIBS defined UART mappings, used before early_serial_setup */
  79 #define UART0_IO_BASE   0xa0000200
  80 #define UART1_IO_BASE   0xa0000300
  81 #define UART2_IO_BASE   0xa0000600
  82
  83 #define BASE_BAUD       11059200
  84 #define STD_UART_OP(num)                                        \
  85         { 0, BASE_BAUD, 0, UART##num##_INT,                     \
  86                 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),        \
  87                 iomem_base: (void*)UART##num##_IO_BASE,         \
  88                 io_type: SERIAL_IO_MEM},
  89
  90 #define SERIAL_PORT_DFNS        \
  91         STD_UART_OP(0)          \
  92         STD_UART_OP(1)          \
  93         STD_UART_OP(2)
  94
  95 /* PCI support */
  96 #define YUCCA_PCIX_LOWER_IO     0x00000000
  97 #define YUCCA_PCIX_UPPER_IO     0x0000ffff
  98 #define YUCCA_PCIX_LOWER_MEM    0x80000000
  99 #define YUCCA_PCIX_UPPER_MEM    0x8fffffff
 100 #define YUCCA_PCIE_LOWER_MEM    0x90000000
 101 #define YUCCA_PCIE_MEM_SIZE     0x10000000
 102
 103 #define YUCCA_PCIX_MEM_SIZE     0x10000000
 104 #define YUCCA_PCIX_MEM_OFFSET   0x00000000
 105 #define YUCCA_PCIE_MEM_SIZE     0x10000000
 106 #define YUCCA_PCIE_MEM_OFFSET   0x00000000
 107
 108 #endif                          /* __ASM_YUCCA_H__ */
 109 #endif                          /* __KERNEL__ */