arch/ppc/platforms/4xx/sycamore.c

   1 /*
   2  * Architecture- / platform-specific boot-time initialization code for
   3  * IBM PowerPC 4xx based boards.
   4  *
   5  * Author: Armin Kuster <akuster@mvista.com>
   6  *
   7  * 2000-2002 (c) MontaVista, Software, Inc.  This file is licensed under
   8  * the terms of the GNU General Public License version 2.  This program
   9  * is licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/smp.h>
  14 #include <linux/threads.h>
  15 #include <linux/param.h>
  16 #include <linux/string.h>
  17 #include <linux/pci.h>
  18 #include <linux/rtc.h>
  19
  20 #include <asm/ocp.h>
  21 #include <asm/ppc4xx_pic.h>
  22 #include <asm/system.h>
  23 #include <asm/pci-bridge.h>
  24 #include <asm/machdep.h>
  25 #include <asm/page.h>
  26 #include <asm/time.h>
  27 #include <asm/io.h>
  28 #include <asm/ibm_ocp_pci.h>
  29 #include <asm/todc.h>
  30
  31 #undef DEBUG
  32
  33 #ifdef DEBUG
  34 #define DBG(x...) printk(x)
  35 #else
  36 #define DBG(x...)
  37 #endif
  38
  39 void *kb_cs;
  40 void *kb_data;
  41 void *sycamore_rtc_base;
  42
  43 /*
  44  * Define external IRQ senses and polarities.
  45  */
  46 unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
  47         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 7 */
  48         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 8 */
  49         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 9 */
  50         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 10 */
  51         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 11 */
  52         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 12 */
  53         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 0 */
  54         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 1 */
  55         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 2 */
  56         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 3 */
  57         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 4 */
  58         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 5 */
  59         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 6 */
  60 };
  61
  62
  63 /* Some IRQs unique to Sycamore.
  64  * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
  65  */
  66 int __init
  67 ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  68 {
  69         static char pci_irq_table[][4] =
  70             /*
  71              *      PCI IDSEL/INTPIN->INTLINE
  72              *      A       B       C       D
  73              */
  74         {
  75                 {28, 28, 28, 28},       /* IDSEL 1 - PCI slot 1 */
  76                 {29, 29, 29, 29},       /* IDSEL 2 - PCI slot 2 */
  77                 {30, 30, 30, 30},       /* IDSEL 3 - PCI slot 3 */
  78                 {31, 31, 31, 31},       /* IDSEL 4 - PCI slot 4 */
  79         };
  80
  81         const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
  82         return PCI_IRQ_TABLE_LOOKUP;
  83 };
  84
  85 void __init
  86 sycamore_setup_arch(void)
  87 {
  88         void *fpga_brdc;
  89         unsigned char fpga_brdc_data;
  90         void *fpga_enable;
  91         void *fpga_polarity;
  92         void *fpga_status;
  93         void *fpga_trigger;
  94
  95         ppc4xx_setup_arch();
  96
  97         ibm_ocp_set_emac(0, 0);
  98
  99         kb_data = ioremap(SYCAMORE_PS2_BASE, 8);
 100         if (!kb_data) {
 101                 printk(KERN_CRIT
 102                        "sycamore_setup_arch() kb_data ioremap failed\n");
 103                 return;
 104         }
 105
 106         kb_cs = kb_data + 1;
 107
 108         fpga_status = ioremap(PPC40x_FPGA_BASE, 8);
 109         if (!fpga_status) {
 110                 printk(KERN_CRIT
 111                        "sycamore_setup_arch() fpga_status ioremap failed\n");
 112                 return;
 113         }
 114
 115         fpga_enable = fpga_status + 1;
 116         fpga_polarity = fpga_status + 2;
 117         fpga_trigger = fpga_status + 3;
 118         fpga_brdc = fpga_status + 4;
 119
 120         /* split the keyboard and mouse interrupts */
 121         fpga_brdc_data = readb(fpga_brdc);
 122         fpga_brdc_data |= 0x80;
 123         writeb(fpga_brdc_data, fpga_brdc);
 124
 125         writeb(0x3, fpga_enable);
 126
 127         writeb(0x3, fpga_polarity);
 128
 129         writeb(0x3, fpga_trigger);
 130
 131         /* RTC step for the sycamore */
 132         sycamore_rtc_base = (void *) SYCAMORE_RTC_VADDR;
 133         TODC_INIT(TODC_TYPE_DS1743, sycamore_rtc_base, sycamore_rtc_base,
 134                   sycamore_rtc_base, 8);
 135
 136         /* Identify the system */
 137         printk(KERN_INFO "IBM Sycamore (IBM405GPr) Platform\n");
 138         printk(KERN_INFO
 139                "Port by MontaVista Software, Inc. (source@mvista.com)\n");
 140 }
 141
 142 void __init
 143 bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
 144 {
 145 #ifdef CONFIG_PCI
 146         unsigned int bar_response, bar;
 147         /*
 148          * Expected PCI mapping:
 149          *
 150          *  PLB addr             PCI memory addr
 151          *  ---------------------       ---------------------
 152          *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
 153          *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
 154          *
 155          *  PLB addr             PCI io addr
 156          *  ---------------------       ---------------------
 157          *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
 158          *
 159          * The following code is simplified by assuming that the bootrom
 160          * has been well behaved in following this mapping.
 161          */
 162
 163 #ifdef DEBUG
 164         int i;
 165
 166         printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
 167         printk("PCI bridge regs before fixup \n");
 168         for (i = 0; i <= 3; i++) {
 169                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
 170                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
 171                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
 172                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
 173         }
 174         printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
 175         printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
 176         printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
 177         printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
 178
 179 #endif
 180
 181         /* added for IBM boot rom version 1.15 bios bar changes  -AK */
 182
 183         /* Disable region first */
 184         out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
 185         /* PLB starting addr, PCI: 0x80000000 */
 186         out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
 187         /* PCI start addr, 0x80000000 */
 188         out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
 189         /* 512MB range of PLB to PCI */
 190         out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
 191         /* Enable no pre-fetch, enable region */
 192         out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
 193                                                 (PPC405_PCI_UPPER_MEM -
 194                                                  PPC405_PCI_MEM_BASE)) | 0x01));
 195
 196         /* Enable inbound region one - 1GB size */
 197         out_le32((void *) &(pcip->ptm1ms), 0xc0000001);
 198
 199         /* Disable outbound region one */
 200         out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 201         out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
 202         out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
 203         out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
 204         out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 205
 206         /* Disable inbound region two */
 207         out_le32((void *) &(pcip->ptm2ms), 0x00000000);
 208
 209         /* Disable outbound region two */
 210         out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 211         out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
 212         out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
 213         out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
 214         out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 215
 216         /* Zero config bars */
 217         for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
 218                 early_write_config_dword(hose, hose->first_busno,
 219                                          PCI_FUNC(hose->first_busno), bar,
 220                                          0x00000000);
 221                 early_read_config_dword(hose, hose->first_busno,
 222                                         PCI_FUNC(hose->first_busno), bar,
 223                                         &bar_response);
 224                 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
 225                     hose->first_busno, PCI_SLOT(hose->first_busno),
 226                     PCI_FUNC(hose->first_busno), bar, bar_response);
 227         }
 228         /* end work arround */
 229
 230 #ifdef DEBUG
 231         printk("PCI bridge regs after fixup \n");
 232         for (i = 0; i <= 3; i++) {
 233                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
 234                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
 235                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
 236                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
 237         }
 238         printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
 239         printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
 240         printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
 241         printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
 242
 243 #endif
 244 #endif
 245
 246 }
 247
 248 void __init
 249 sycamore_map_io(void)
 250 {
 251         ppc4xx_map_io();
 252         io_block_mapping(SYCAMORE_RTC_VADDR,
 253                          SYCAMORE_RTC_PADDR, SYCAMORE_RTC_SIZE, _PAGE_IO);
 254 }
 255
 256 void __init
 257 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 258               unsigned long r6, unsigned long r7)
 259 {
 260         ppc4xx_init(r3, r4, r5, r6, r7);
 261
 262         ppc_md.setup_arch = sycamore_setup_arch;
 263         ppc_md.setup_io_mappings = sycamore_map_io;
 264
 265 #ifdef CONFIG_GEN_RTC
 266         ppc_md.time_init = todc_time_init;
 267         ppc_md.set_rtc_time = todc_set_rtc_time;
 268         ppc_md.get_rtc_time = todc_get_rtc_time;
 269         ppc_md.nvram_read_val = todc_direct_read_val;
 270         ppc_md.nvram_write_val = todc_direct_write_val;
 271 #endif
 272 }