2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
15 #include <linux/sys.h>
16 #include <asm/unistd.h>
17 #include <asm/errno.h>
18 #include <asm/processor.h>
20 #include <asm/cache.h>
21 #include <asm/cputable.h>
23 #include <asm/ppc_asm.h>
24 #include <asm/thread_info.h>
25 #include <asm/asm-offsets.h>
28 #define ISYNC_8xx isync
43 * Returns (address we're running at) - (address we were linked at)
44 * for use before the text and data are mapped to KERNELBASE.
57 * add_reloc_offset(x) returns x + reloc_offset().
59 _GLOBAL(add_reloc_offset)
71 * sub_reloc_offset(x) returns x - reloc_offset().
73 _GLOBAL(sub_reloc_offset)
85 * reloc_got2 runs through the .got2 section adding an offset
90 lis r7,__got2_start@ha
91 addi r7,r7,__got2_start@l
93 addi r8,r8,__got2_end@l
113 * call_setup_cpu - call the setup_cpu function for this cpu
114 * r3 = data offset, r24 = cpu number
116 * Setup function is called with:
118 * r4 = ptr to CPU spec (relocated)
120 _GLOBAL(call_setup_cpu)
121 addis r4,r3,cur_cpu_spec@ha
122 addi r4,r4,cur_cpu_spec@l
125 lwz r5,CPU_SPEC_SETUP(r4)
133 * complement mask on the msr then "or" some values on.
134 * _nmask_and_or_msr(nmask, value_to_or)
136 _GLOBAL(_nmask_and_or_msr)
137 mfmsr r0 /* Get current msr */
138 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
139 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
140 SYNC /* Some chip revs have problems here... */
141 mtmsr r0 /* Update machine state */
150 #if defined(CONFIG_40x)
151 sync /* Flush to memory before changing mapping */
153 isync /* Flush shadow TLB */
154 #elif defined(CONFIG_44x)
158 /* Load high watermark */
159 lis r4,tlb_44x_hwater@ha
160 lwz r5,tlb_44x_hwater@l(r4)
162 1: tlbwe r3,r3,PPC44x_TLB_PAGEID
168 #elif defined(CONFIG_FSL_BOOKE)
169 /* Invalidate all entries in TLB0 */
172 /* Invalidate all entries in TLB1 */
175 /* Invalidate all entries in TLB2 */
178 /* Invalidate all entries in TLB3 */
184 #endif /* CONFIG_SMP */
185 #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
186 #if defined(CONFIG_SMP)
192 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
193 rlwinm r0,r0,0,28,26 /* clear DR */
197 lis r9,mmu_hash_lock@h
198 ori r9,r9,mmu_hash_lock@l
210 stw r0,0(r9) /* clear mmu_hash_lock */
214 #else /* CONFIG_SMP */
218 #endif /* CONFIG_SMP */
219 #endif /* ! defined(CONFIG_40x) */
223 * Flush MMU TLB for a particular address
226 #if defined(CONFIG_40x)
227 /* We run the search with interrupts disabled because we have to change
228 * the PID and I don't want to preempt when that happens.
239 /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear.
240 * Since 25 is the V bit in the TLB_TAG, loading this value will invalidate
242 tlbwe r3, r3, TLB_TAG
245 #elif defined(CONFIG_44x)
247 rlwimi r5,r4,0,24,31 /* Set TID */
249 /* We have to run the search with interrupts disabled, even critical
250 * and debug interrupts (in fact the only critical exceptions we have
251 * are debug and machine check). Otherwise an interrupt which causes
252 * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */
254 lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha
255 addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l
263 /* There are only 64 TLB entries, so r3 < 64,
264 * which means bit 22, is clear. Since 22 is
265 * the V bit in the TLB_PAGEID, loading this
266 * value will invalidate the TLB entry.
268 tlbwe r3, r3, PPC44x_TLB_PAGEID
271 #elif defined(CONFIG_FSL_BOOKE)
272 rlwinm r4, r3, 0, 0, 19
273 ori r5, r4, 0x08 /* TLBSEL = 1 */
274 ori r6, r4, 0x10 /* TLBSEL = 2 */
275 ori r7, r4, 0x18 /* TLBSEL = 3 */
281 #if defined(CONFIG_SMP)
283 #endif /* CONFIG_SMP */
284 #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
285 #if defined(CONFIG_SMP)
291 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
292 rlwinm r0,r0,0,28,26 /* clear DR */
296 lis r9,mmu_hash_lock@h
297 ori r9,r9,mmu_hash_lock@l
309 stw r0,0(r9) /* clear mmu_hash_lock */
313 #else /* CONFIG_SMP */
316 #endif /* CONFIG_SMP */
317 #endif /* ! CONFIG_40x */
321 * Flush instruction cache.
322 * This is a no-op on the 601.
324 _GLOBAL(flush_instruction_cache)
325 #if defined(CONFIG_8xx)
328 mtspr SPRN_IC_CST, r5
329 #elif defined(CONFIG_4xx)
341 #elif CONFIG_FSL_BOOKE
344 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
345 /* msync; isync recommended here */
349 END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
351 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
355 rlwinm r3,r3,16,16,31
357 beqlr /* for 601, do nothing */
358 /* 603/604 processor - use invalidate-all bit in HID0 */
362 #endif /* CONFIG_8xx/4xx */
367 * Write any modified data cache blocks out to memory
368 * and invalidate the corresponding instruction cache blocks.
369 * This is a no-op on the 601.
371 * __flush_icache_range(unsigned long start, unsigned long stop)
373 _GLOBAL(__flush_icache_range)
375 blr /* for 601, do nothing */
376 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
377 li r5,L1_CACHE_BYTES-1
381 srwi. r4,r4,L1_CACHE_SHIFT
386 addi r3,r3,L1_CACHE_BYTES
388 sync /* wait for dcbst's to get to ram */
391 addi r6,r6,L1_CACHE_BYTES
393 sync /* additional sync needed on g4 */
397 * Write any modified data cache blocks out to memory.
398 * Does not invalidate the corresponding cache lines (especially for
399 * any corresponding instruction cache).
401 * clean_dcache_range(unsigned long start, unsigned long stop)
403 _GLOBAL(clean_dcache_range)
404 li r5,L1_CACHE_BYTES-1
408 srwi. r4,r4,L1_CACHE_SHIFT
413 addi r3,r3,L1_CACHE_BYTES
415 sync /* wait for dcbst's to get to ram */
419 * Write any modified data cache blocks out to memory and invalidate them.
420 * Does not invalidate the corresponding instruction cache blocks.
422 * flush_dcache_range(unsigned long start, unsigned long stop)
424 _GLOBAL(flush_dcache_range)
425 li r5,L1_CACHE_BYTES-1
429 srwi. r4,r4,L1_CACHE_SHIFT
434 addi r3,r3,L1_CACHE_BYTES
436 sync /* wait for dcbst's to get to ram */
440 * Like above, but invalidate the D-cache. This is used by the 8xx
441 * to invalidate the cache so the PPC core doesn't get stale data
442 * from the CPM (no cache snooping here :-).
444 * invalidate_dcache_range(unsigned long start, unsigned long stop)
446 _GLOBAL(invalidate_dcache_range)
447 li r5,L1_CACHE_BYTES-1
451 srwi. r4,r4,L1_CACHE_SHIFT
456 addi r3,r3,L1_CACHE_BYTES
458 sync /* wait for dcbi's to get to ram */
461 #ifdef CONFIG_NOT_COHERENT_CACHE
463 * 40x cores have 8K or 16K dcache and 32 byte line size.
464 * 44x has a 32K dcache and 32 byte line size.
465 * 8xx has 1, 2, 4, 8K variants.
466 * For now, cover the worst case of the 44x.
467 * Must be called with external interrupts disabled.
469 #define CACHE_NWAYS 64
470 #define CACHE_NLINES 16
472 _GLOBAL(flush_dcache_all)
473 li r4, (2 * CACHE_NWAYS * CACHE_NLINES)
476 1: lwz r3, 0(r5) /* Load one word from every line */
477 addi r5, r5, L1_CACHE_BYTES
480 #endif /* CONFIG_NOT_COHERENT_CACHE */
483 * Flush a particular page from the data cache to RAM.
484 * Note: this is necessary because the instruction cache does *not*
485 * snoop from the data cache.
486 * This is a no-op on the 601 which has a unified cache.
488 * void __flush_dcache_icache(void *page)
490 _GLOBAL(__flush_dcache_icache)
492 blr /* for 601, do nothing */
493 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
494 rlwinm r3,r3,0,0,19 /* Get page base address */
495 li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
498 0: dcbst 0,r3 /* Write line to ram */
499 addi r3,r3,L1_CACHE_BYTES
504 addi r6,r6,L1_CACHE_BYTES
511 * Flush a particular page from the data cache to RAM, identified
512 * by its physical address. We turn off the MMU so we can just use
513 * the physical address (this may be a highmem page without a kernel
516 * void __flush_dcache_icache_phys(unsigned long physaddr)
518 _GLOBAL(__flush_dcache_icache_phys)
520 blr /* for 601, do nothing */
521 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
523 rlwinm r0,r10,0,28,26 /* clear DR */
526 rlwinm r3,r3,0,0,19 /* Get page base address */
527 li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
530 0: dcbst 0,r3 /* Write line to ram */
531 addi r3,r3,L1_CACHE_BYTES
536 addi r6,r6,L1_CACHE_BYTES
539 mtmsr r10 /* restore DR */
544 * Clear pages using the dcbz instruction, which doesn't cause any
545 * memory traffic (except to write out any cache lines which get
546 * displaced). This only works on cacheable memory.
548 * void clear_pages(void *page, int order) ;
551 li r0,4096/L1_CACHE_BYTES
563 addi r3,r3,L1_CACHE_BYTES
568 * Copy a whole page. We use the dcbz instruction on the destination
569 * to reduce memory traffic (it eliminates the unnecessary reads of
570 * the destination into cache). This requires that the destination
573 #define COPY_16_BYTES \
588 /* don't use prefetch on 8xx */
589 li r0,4096/L1_CACHE_BYTES
595 #else /* not 8xx, we can prefetch */
598 #if MAX_COPY_PREFETCH > 1
599 li r0,MAX_COPY_PREFETCH
603 addi r11,r11,L1_CACHE_BYTES
605 #else /* MAX_COPY_PREFETCH == 1 */
607 li r11,L1_CACHE_BYTES+4
608 #endif /* MAX_COPY_PREFETCH */
609 li r0,4096/L1_CACHE_BYTES - MAX_COPY_PREFETCH
617 #if L1_CACHE_BYTES >= 32
619 #if L1_CACHE_BYTES >= 64
622 #if L1_CACHE_BYTES >= 128
632 crnot 4*cr0+eq,4*cr0+eq
633 li r0,MAX_COPY_PREFETCH
636 #endif /* CONFIG_8xx */
639 * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
640 * void atomic_set_mask(atomic_t mask, atomic_t *addr);
642 _GLOBAL(atomic_clear_mask)
649 _GLOBAL(atomic_set_mask)
658 * I/O string operations
660 * insb(port, buf, len)
661 * outsb(port, buf, len)
662 * insw(port, buf, len)
663 * outsw(port, buf, len)
664 * insl(port, buf, len)
665 * outsl(port, buf, len)
666 * insw_ns(port, buf, len)
667 * outsw_ns(port, buf, len)
668 * insl_ns(port, buf, len)
669 * outsl_ns(port, buf, len)
671 * The *_ns versions don't do byte-swapping.
685 .section __ex_table, "a"
706 .section __ex_table, "a"
727 .section __ex_table, "a"
748 .section __ex_table, "a"
769 .section __ex_table, "a"
790 .section __ex_table, "a"
800 * Extended precision shifts.
802 * Updated to be valid for shift counts from 0 to 63 inclusive.
805 * R3/R4 has 64 bit value
809 * ashrdi3: arithmetic right shift (sign propagation)
810 * lshrdi3: logical right shift
811 * ashldi3: left shift
815 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
816 addi r7,r5,32 # could be xori, or addi with -32
817 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
818 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
819 sraw r7,r3,r7 # t2 = MSW >> (count-32)
820 or r4,r4,r6 # LSW |= t1
821 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
822 sraw r3,r3,r5 # MSW = MSW >> count
823 or r4,r4,r7 # LSW |= t2
828 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
829 addi r7,r5,32 # could be xori, or addi with -32
830 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
831 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
832 or r3,r3,r6 # MSW |= t1
833 slw r4,r4,r5 # LSW = LSW << count
834 or r3,r3,r7 # MSW |= t2
839 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
840 addi r7,r5,32 # could be xori, or addi with -32
841 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
842 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
843 or r4,r4,r6 # LSW |= t1
844 srw r3,r3,r5 # MSW = MSW >> count
845 or r4,r4,r7 # LSW |= t2
855 mr r3,r1 /* Close enough */
859 * Create a kernel thread
860 * kernel_thread(fn, arg, flags)
862 _GLOBAL(kernel_thread)
866 mr r30,r3 /* function */
867 mr r31,r4 /* argument */
868 ori r3,r5,CLONE_VM /* flags */
869 oris r3,r3,CLONE_UNTRACED>>16
870 li r4,0 /* new sp (unused) */
873 cmpwi 0,r3,0 /* parent or child? */
874 bne 1f /* return if parent */
875 li r0,0 /* make top-level stack frame */
877 mtlr r30 /* fn addr in lr */
878 mr r3,r31 /* load arg and call fn */
881 li r0,__NR_exit /* exit if function returns */
889 _GLOBAL(kernel_execve)
897 * This routine is just here to keep GCC happy - sigh...