arch/powerpc/sysdev/ipic.c

   1 /*
   2  * arch/powerpc/sysdev/ipic.c
   3  *
   4  * IPIC routines implementations.
   5  *
   6  * Copyright 2005 Freescale Semiconductor, Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/errno.h>
  16 #include <linux/reboot.h>
  17 #include <linux/slab.h>
  18 #include <linux/stddef.h>
  19 #include <linux/sched.h>
  20 #include <linux/signal.h>
  21 #include <linux/sysdev.h>
  22 #include <linux/device.h>
  23 #include <linux/bootmem.h>
  24 #include <linux/spinlock.h>
  25 #include <asm/irq.h>
  26 #include <asm/io.h>
  27 #include <asm/prom.h>
  28 #include <asm/ipic.h>
  29
  30 #include "ipic.h"
  31
  32 static struct ipic * primary_ipic;
  33 static DEFINE_SPINLOCK(ipic_lock);
  34
  35 static struct ipic_info ipic_info[] = {
  36         [1] = {
  37                 .pend   = IPIC_SIPNR_H,
  38                 .mask   = IPIC_SIMSR_H,
  39                 .prio   = IPIC_SIPRR_C,
  40                 .force  = IPIC_SIFCR_H,
  41                 .bit    = 16,
  42                 .prio_mask = 0,
  43         },
  44         [2] = {
  45                 .pend   = IPIC_SIPNR_H,
  46                 .mask   = IPIC_SIMSR_H,
  47                 .prio   = IPIC_SIPRR_C,
  48                 .force  = IPIC_SIFCR_H,
  49                 .bit    = 17,
  50                 .prio_mask = 1,
  51         },
  52         [4] = {
  53                 .pend   = IPIC_SIPNR_H,
  54                 .mask   = IPIC_SIMSR_H,
  55                 .prio   = IPIC_SIPRR_C,
  56                 .force  = IPIC_SIFCR_H,
  57                 .bit    = 19,
  58                 .prio_mask = 3,
  59         },
  60         [9] = {
  61                 .pend   = IPIC_SIPNR_H,
  62                 .mask   = IPIC_SIMSR_H,
  63                 .prio   = IPIC_SIPRR_D,
  64                 .force  = IPIC_SIFCR_H,
  65                 .bit    = 24,
  66                 .prio_mask = 0,
  67         },
  68         [10] = {
  69                 .pend   = IPIC_SIPNR_H,
  70                 .mask   = IPIC_SIMSR_H,
  71                 .prio   = IPIC_SIPRR_D,
  72                 .force  = IPIC_SIFCR_H,
  73                 .bit    = 25,
  74                 .prio_mask = 1,
  75         },
  76         [11] = {
  77                 .pend   = IPIC_SIPNR_H,
  78                 .mask   = IPIC_SIMSR_H,
  79                 .prio   = IPIC_SIPRR_D,
  80                 .force  = IPIC_SIFCR_H,
  81                 .bit    = 26,
  82                 .prio_mask = 2,
  83         },
  84         [12] = {
  85                 .pend   = IPIC_SIPNR_H,
  86                 .mask   = IPIC_SIMSR_H,
  87                 .prio   = IPIC_SIPRR_D,
  88                 .force  = IPIC_SIFCR_H,
  89                 .bit    = 27,
  90                 .prio_mask = 3,
  91         },
  92         [13] = {
  93                 .pend   = IPIC_SIPNR_H,
  94                 .mask   = IPIC_SIMSR_H,
  95                 .prio   = IPIC_SIPRR_D,
  96                 .force  = IPIC_SIFCR_H,
  97                 .bit    = 28,
  98                 .prio_mask = 4,
  99         },
 100         [14] = {
 101                 .pend   = IPIC_SIPNR_H,
 102                 .mask   = IPIC_SIMSR_H,
 103                 .prio   = IPIC_SIPRR_D,
 104                 .force  = IPIC_SIFCR_H,
 105                 .bit    = 29,
 106                 .prio_mask = 5,
 107         },
 108         [15] = {
 109                 .pend   = IPIC_SIPNR_H,
 110                 .mask   = IPIC_SIMSR_H,
 111                 .prio   = IPIC_SIPRR_D,
 112                 .force  = IPIC_SIFCR_H,
 113                 .bit    = 30,
 114                 .prio_mask = 6,
 115         },
 116         [16] = {
 117                 .pend   = IPIC_SIPNR_H,
 118                 .mask   = IPIC_SIMSR_H,
 119                 .prio   = IPIC_SIPRR_D,
 120                 .force  = IPIC_SIFCR_H,
 121                 .bit    = 31,
 122                 .prio_mask = 7,
 123         },
 124         [17] = {
 125                 .pend   = IPIC_SEPNR,
 126                 .mask   = IPIC_SEMSR,
 127                 .prio   = IPIC_SMPRR_A,
 128                 .force  = IPIC_SEFCR,
 129                 .bit    = 1,
 130                 .prio_mask = 5,
 131         },
 132         [18] = {
 133                 .pend   = IPIC_SEPNR,
 134                 .mask   = IPIC_SEMSR,
 135                 .prio   = IPIC_SMPRR_A,
 136                 .force  = IPIC_SEFCR,
 137                 .bit    = 2,
 138                 .prio_mask = 6,
 139         },
 140         [19] = {
 141                 .pend   = IPIC_SEPNR,
 142                 .mask   = IPIC_SEMSR,
 143                 .prio   = IPIC_SMPRR_A,
 144                 .force  = IPIC_SEFCR,
 145                 .bit    = 3,
 146                 .prio_mask = 7,
 147         },
 148         [20] = {
 149                 .pend   = IPIC_SEPNR,
 150                 .mask   = IPIC_SEMSR,
 151                 .prio   = IPIC_SMPRR_B,
 152                 .force  = IPIC_SEFCR,
 153                 .bit    = 4,
 154                 .prio_mask = 4,
 155         },
 156         [21] = {
 157                 .pend   = IPIC_SEPNR,
 158                 .mask   = IPIC_SEMSR,
 159                 .prio   = IPIC_SMPRR_B,
 160                 .force  = IPIC_SEFCR,
 161                 .bit    = 5,
 162                 .prio_mask = 5,
 163         },
 164         [22] = {
 165                 .pend   = IPIC_SEPNR,
 166                 .mask   = IPIC_SEMSR,
 167                 .prio   = IPIC_SMPRR_B,
 168                 .force  = IPIC_SEFCR,
 169                 .bit    = 6,
 170                 .prio_mask = 6,
 171         },
 172         [23] = {
 173                 .pend   = IPIC_SEPNR,
 174                 .mask   = IPIC_SEMSR,
 175                 .prio   = IPIC_SMPRR_B,
 176                 .force  = IPIC_SEFCR,
 177                 .bit    = 7,
 178                 .prio_mask = 7,
 179         },
 180         [32] = {
 181                 .pend   = IPIC_SIPNR_H,
 182                 .mask   = IPIC_SIMSR_H,
 183                 .prio   = IPIC_SIPRR_A,
 184                 .force  = IPIC_SIFCR_H,
 185                 .bit    = 0,
 186                 .prio_mask = 0,
 187         },
 188         [33] = {
 189                 .pend   = IPIC_SIPNR_H,
 190                 .mask   = IPIC_SIMSR_H,
 191                 .prio   = IPIC_SIPRR_A,
 192                 .force  = IPIC_SIFCR_H,
 193                 .bit    = 1,
 194                 .prio_mask = 1,
 195         },
 196         [34] = {
 197                 .pend   = IPIC_SIPNR_H,
 198                 .mask   = IPIC_SIMSR_H,
 199                 .prio   = IPIC_SIPRR_A,
 200                 .force  = IPIC_SIFCR_H,
 201                 .bit    = 2,
 202                 .prio_mask = 2,
 203         },
 204         [35] = {
 205                 .pend   = IPIC_SIPNR_H,
 206                 .mask   = IPIC_SIMSR_H,
 207                 .prio   = IPIC_SIPRR_A,
 208                 .force  = IPIC_SIFCR_H,
 209                 .bit    = 3,
 210                 .prio_mask = 3,
 211         },
 212         [36] = {
 213                 .pend   = IPIC_SIPNR_H,
 214                 .mask   = IPIC_SIMSR_H,
 215                 .prio   = IPIC_SIPRR_A,
 216                 .force  = IPIC_SIFCR_H,
 217                 .bit    = 4,
 218                 .prio_mask = 4,
 219         },
 220         [37] = {
 221                 .pend   = IPIC_SIPNR_H,
 222                 .mask   = IPIC_SIMSR_H,
 223                 .prio   = IPIC_SIPRR_A,
 224                 .force  = IPIC_SIFCR_H,
 225                 .bit    = 5,
 226                 .prio_mask = 5,
 227         },
 228         [38] = {
 229                 .pend   = IPIC_SIPNR_H,
 230                 .mask   = IPIC_SIMSR_H,
 231                 .prio   = IPIC_SIPRR_A,
 232                 .force  = IPIC_SIFCR_H,
 233                 .bit    = 6,
 234                 .prio_mask = 6,
 235         },
 236         [39] = {
 237                 .pend   = IPIC_SIPNR_H,
 238                 .mask   = IPIC_SIMSR_H,
 239                 .prio   = IPIC_SIPRR_A,
 240                 .force  = IPIC_SIFCR_H,
 241                 .bit    = 7,
 242                 .prio_mask = 7,
 243         },
 244         [42] = {
 245                 .pend   = IPIC_SIPNR_H,
 246                 .mask   = IPIC_SIMSR_H,
 247                 .prio   = IPIC_SIPRR_B,
 248                 .force  = IPIC_SIFCR_H,
 249                 .bit    = 10,
 250                 .prio_mask = 2,
 251         },
 252         [44] = {
 253                 .pend   = IPIC_SIPNR_H,
 254                 .mask   = IPIC_SIMSR_H,
 255                 .prio   = IPIC_SIPRR_B,
 256                 .force  = IPIC_SIFCR_H,
 257                 .bit    = 12,
 258                 .prio_mask = 4,
 259         },
 260         [45] = {
 261                 .pend   = IPIC_SIPNR_H,
 262                 .mask   = IPIC_SIMSR_H,
 263                 .prio   = IPIC_SIPRR_B,
 264                 .force  = IPIC_SIFCR_H,
 265                 .bit    = 13,
 266                 .prio_mask = 5,
 267         },
 268         [46] = {
 269                 .pend   = IPIC_SIPNR_H,
 270                 .mask   = IPIC_SIMSR_H,
 271                 .prio   = IPIC_SIPRR_B,
 272                 .force  = IPIC_SIFCR_H,
 273                 .bit    = 14,
 274                 .prio_mask = 6,
 275         },
 276         [47] = {
 277                 .pend   = IPIC_SIPNR_H,
 278                 .mask   = IPIC_SIMSR_H,
 279                 .prio   = IPIC_SIPRR_B,
 280                 .force  = IPIC_SIFCR_H,
 281                 .bit    = 15,
 282                 .prio_mask = 7,
 283         },
 284         [48] = {
 285                 .pend   = IPIC_SEPNR,
 286                 .mask   = IPIC_SEMSR,
 287                 .prio   = IPIC_SMPRR_A,
 288                 .force  = IPIC_SEFCR,
 289                 .bit    = 0,
 290                 .prio_mask = 4,
 291         },
 292         [64] = {
 293                 .pend   = IPIC_SIPNR_L,
 294                 .mask   = IPIC_SIMSR_L,
 295                 .prio   = IPIC_SMPRR_A,
 296                 .force  = IPIC_SIFCR_L,
 297                 .bit    = 0,
 298                 .prio_mask = 0,
 299         },
 300         [65] = {
 301                 .pend   = IPIC_SIPNR_L,
 302                 .mask   = IPIC_SIMSR_L,
 303                 .prio   = IPIC_SMPRR_A,
 304                 .force  = IPIC_SIFCR_L,
 305                 .bit    = 1,
 306                 .prio_mask = 1,
 307         },
 308         [66] = {
 309                 .pend   = IPIC_SIPNR_L,
 310                 .mask   = IPIC_SIMSR_L,
 311                 .prio   = IPIC_SMPRR_A,
 312                 .force  = IPIC_SIFCR_L,
 313                 .bit    = 2,
 314                 .prio_mask = 2,
 315         },
 316         [67] = {
 317                 .pend   = IPIC_SIPNR_L,
 318                 .mask   = IPIC_SIMSR_L,
 319                 .prio   = IPIC_SMPRR_A,
 320                 .force  = IPIC_SIFCR_L,
 321                 .bit    = 3,
 322                 .prio_mask = 3,
 323         },
 324         [68] = {
 325                 .pend   = IPIC_SIPNR_L,
 326                 .mask   = IPIC_SIMSR_L,
 327                 .prio   = IPIC_SMPRR_B,
 328                 .force  = IPIC_SIFCR_L,
 329                 .bit    = 4,
 330                 .prio_mask = 0,
 331         },
 332         [69] = {
 333                 .pend   = IPIC_SIPNR_L,
 334                 .mask   = IPIC_SIMSR_L,
 335                 .prio   = IPIC_SMPRR_B,
 336                 .force  = IPIC_SIFCR_L,
 337                 .bit    = 5,
 338                 .prio_mask = 1,
 339         },
 340         [70] = {
 341                 .pend   = IPIC_SIPNR_L,
 342                 .mask   = IPIC_SIMSR_L,
 343                 .prio   = IPIC_SMPRR_B,
 344                 .force  = IPIC_SIFCR_L,
 345                 .bit    = 6,
 346                 .prio_mask = 2,
 347         },
 348         [71] = {
 349                 .pend   = IPIC_SIPNR_L,
 350                 .mask   = IPIC_SIMSR_L,
 351                 .prio   = IPIC_SMPRR_B,
 352                 .force  = IPIC_SIFCR_L,
 353                 .bit    = 7,
 354                 .prio_mask = 3,
 355         },
 356         [72] = {
 357                 .pend   = IPIC_SIPNR_L,
 358                 .mask   = IPIC_SIMSR_L,
 359                 .prio   = 0,
 360                 .force  = IPIC_SIFCR_L,
 361                 .bit    = 8,
 362         },
 363         [73] = {
 364                 .pend   = IPIC_SIPNR_L,
 365                 .mask   = IPIC_SIMSR_L,
 366                 .prio   = 0,
 367                 .force  = IPIC_SIFCR_L,
 368                 .bit    = 9,
 369         },
 370         [74] = {
 371                 .pend   = IPIC_SIPNR_L,
 372                 .mask   = IPIC_SIMSR_L,
 373                 .prio   = 0,
 374                 .force  = IPIC_SIFCR_L,
 375                 .bit    = 10,
 376         },
 377         [75] = {
 378                 .pend   = IPIC_SIPNR_L,
 379                 .mask   = IPIC_SIMSR_L,
 380                 .prio   = 0,
 381                 .force  = IPIC_SIFCR_L,
 382                 .bit    = 11,
 383         },
 384         [76] = {
 385                 .pend   = IPIC_SIPNR_L,
 386                 .mask   = IPIC_SIMSR_L,
 387                 .prio   = 0,
 388                 .force  = IPIC_SIFCR_L,
 389                 .bit    = 12,
 390         },
 391         [77] = {
 392                 .pend   = IPIC_SIPNR_L,
 393                 .mask   = IPIC_SIMSR_L,
 394                 .prio   = 0,
 395                 .force  = IPIC_SIFCR_L,
 396                 .bit    = 13,
 397         },
 398         [78] = {
 399                 .pend   = IPIC_SIPNR_L,
 400                 .mask   = IPIC_SIMSR_L,
 401                 .prio   = 0,
 402                 .force  = IPIC_SIFCR_L,
 403                 .bit    = 14,
 404         },
 405         [79] = {
 406                 .pend   = IPIC_SIPNR_L,
 407                 .mask   = IPIC_SIMSR_L,
 408                 .prio   = 0,
 409                 .force  = IPIC_SIFCR_L,
 410                 .bit    = 15,
 411         },
 412         [80] = {
 413                 .pend   = IPIC_SIPNR_L,
 414                 .mask   = IPIC_SIMSR_L,
 415                 .prio   = 0,
 416                 .force  = IPIC_SIFCR_L,
 417                 .bit    = 16,
 418         },
 419         [81] = {
 420                 .pend   = IPIC_SIPNR_L,
 421                 .mask   = IPIC_SIMSR_L,
 422                 .prio   = 0,
 423                 .force  = IPIC_SIFCR_L,
 424                 .bit    = 17,
 425         },
 426         [82] = {
 427                 .pend   = IPIC_SIPNR_L,
 428                 .mask   = IPIC_SIMSR_L,
 429                 .prio   = 0,
 430                 .force  = IPIC_SIFCR_L,
 431                 .bit    = 18,
 432         },
 433         [84] = {
 434                 .pend   = IPIC_SIPNR_L,
 435                 .mask   = IPIC_SIMSR_L,
 436                 .prio   = 0,
 437                 .force  = IPIC_SIFCR_L,
 438                 .bit    = 20,
 439         },
 440         [85] = {
 441                 .pend   = IPIC_SIPNR_L,
 442                 .mask   = IPIC_SIMSR_L,
 443                 .prio   = 0,
 444                 .force  = IPIC_SIFCR_L,
 445                 .bit    = 21,
 446         },
 447         [86] = {
 448                 .pend   = IPIC_SIPNR_L,
 449                 .mask   = IPIC_SIMSR_L,
 450                 .prio   = 0,
 451                 .force  = IPIC_SIFCR_L,
 452                 .bit    = 22,
 453         },
 454         [87] = {
 455                 .pend   = IPIC_SIPNR_L,
 456                 .mask   = IPIC_SIMSR_L,
 457                 .prio   = 0,
 458                 .force  = IPIC_SIFCR_L,
 459                 .bit    = 23,
 460         },
 461         [88] = {
 462                 .pend   = IPIC_SIPNR_L,
 463                 .mask   = IPIC_SIMSR_L,
 464                 .prio   = 0,
 465                 .force  = IPIC_SIFCR_L,
 466                 .bit    = 24,
 467         },
 468         [89] = {
 469                 .pend   = IPIC_SIPNR_L,
 470                 .mask   = IPIC_SIMSR_L,
 471                 .prio   = 0,
 472                 .force  = IPIC_SIFCR_L,
 473                 .bit    = 25,
 474         },
 475         [90] = {
 476                 .pend   = IPIC_SIPNR_L,
 477                 .mask   = IPIC_SIMSR_L,
 478                 .prio   = 0,
 479                 .force  = IPIC_SIFCR_L,
 480                 .bit    = 26,
 481         },
 482         [91] = {
 483                 .pend   = IPIC_SIPNR_L,
 484                 .mask   = IPIC_SIMSR_L,
 485                 .prio   = 0,
 486                 .force  = IPIC_SIFCR_L,
 487                 .bit    = 27,
 488         },
 489 };
 490
 491 static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
 492 {
 493         return in_be32(base + (reg >> 2));
 494 }
 495
 496 static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)
 497 {
 498         out_be32(base + (reg >> 2), value);
 499 }
 500
 501 static inline struct ipic * ipic_from_irq(unsigned int virq)
 502 {
 503         return primary_ipic;
 504 }
 505
 506 #define ipic_irq_to_hw(virq)    ((unsigned int)irq_map[virq].hwirq)
 507
 508 static void ipic_unmask_irq(unsigned int virq)
 509 {
 510         struct ipic *ipic = ipic_from_irq(virq);
 511         unsigned int src = ipic_irq_to_hw(virq);
 512         unsigned long flags;
 513         u32 temp;
 514
 515         spin_lock_irqsave(&ipic_lock, flags);
 516
 517         temp = ipic_read(ipic->regs, ipic_info[src].mask);
 518         temp |= (1 << (31 - ipic_info[src].bit));
 519         ipic_write(ipic->regs, ipic_info[src].mask, temp);
 520
 521         spin_unlock_irqrestore(&ipic_lock, flags);
 522 }
 523
 524 static void ipic_mask_irq(unsigned int virq)
 525 {
 526         struct ipic *ipic = ipic_from_irq(virq);
 527         unsigned int src = ipic_irq_to_hw(virq);
 528         unsigned long flags;
 529         u32 temp;
 530
 531         spin_lock_irqsave(&ipic_lock, flags);
 532
 533         temp = ipic_read(ipic->regs, ipic_info[src].mask);
 534         temp &= ~(1 << (31 - ipic_info[src].bit));
 535         ipic_write(ipic->regs, ipic_info[src].mask, temp);
 536
 537         spin_unlock_irqrestore(&ipic_lock, flags);
 538 }
 539
 540 static void ipic_ack_irq(unsigned int virq)
 541 {
 542         struct ipic *ipic = ipic_from_irq(virq);
 543         unsigned int src = ipic_irq_to_hw(virq);
 544         unsigned long flags;
 545         u32 temp;
 546
 547         spin_lock_irqsave(&ipic_lock, flags);
 548
 549         temp = ipic_read(ipic->regs, ipic_info[src].pend);
 550         temp |= (1 << (31 - ipic_info[src].bit));
 551         ipic_write(ipic->regs, ipic_info[src].pend, temp);
 552
 553         spin_unlock_irqrestore(&ipic_lock, flags);
 554 }
 555
 556 static void ipic_mask_irq_and_ack(unsigned int virq)
 557 {
 558         struct ipic *ipic = ipic_from_irq(virq);
 559         unsigned int src = ipic_irq_to_hw(virq);
 560         unsigned long flags;
 561         u32 temp;
 562
 563         spin_lock_irqsave(&ipic_lock, flags);
 564
 565         temp = ipic_read(ipic->regs, ipic_info[src].mask);
 566         temp &= ~(1 << (31 - ipic_info[src].bit));
 567         ipic_write(ipic->regs, ipic_info[src].mask, temp);
 568
 569         temp = ipic_read(ipic->regs, ipic_info[src].pend);
 570         temp |= (1 << (31 - ipic_info[src].bit));
 571         ipic_write(ipic->regs, ipic_info[src].pend, temp);
 572
 573         spin_unlock_irqrestore(&ipic_lock, flags);
 574 }
 575
 576 static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type)
 577 {
 578         struct ipic *ipic = ipic_from_irq(virq);
 579         unsigned int src = ipic_irq_to_hw(virq);
 580         struct irq_desc *desc = get_irq_desc(virq);
 581         unsigned int vold, vnew, edibit;
 582
 583         if (flow_type == IRQ_TYPE_NONE)
 584                 flow_type = IRQ_TYPE_LEVEL_LOW;
 585
 586         /* ipic supports only low assertion and high-to-low change senses
 587          */
 588         if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) {
 589                 printk(KERN_ERR "ipic: sense type 0x%x not supported\n",
 590                         flow_type);
 591                 return -EINVAL;
 592         }
 593
 594         desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
 595         desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
 596         if (flow_type & IRQ_TYPE_LEVEL_LOW)  {
 597                 desc->status |= IRQ_LEVEL;
 598                 desc->handle_irq = handle_level_irq;
 599         } else {
 600                 desc->handle_irq = handle_edge_irq;
 601         }
 602
 603         /* only EXT IRQ senses are programmable on ipic
 604          * internal IRQ senses are LEVEL_LOW
 605          */
 606         if (src == IPIC_IRQ_EXT0)
 607                 edibit = 15;
 608         else
 609                 if (src >= IPIC_IRQ_EXT1 && src <= IPIC_IRQ_EXT7)
 610                         edibit = (14 - (src - IPIC_IRQ_EXT1));
 611                 else
 612                         return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
 613
 614         vold = ipic_read(ipic->regs, IPIC_SECNR);
 615         if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) {
 616                 vnew = vold | (1 << edibit);
 617         } else {
 618                 vnew = vold & ~(1 << edibit);
 619         }
 620         if (vold != vnew)
 621                 ipic_write(ipic->regs, IPIC_SECNR, vnew);
 622         return 0;
 623 }
 624
 625 static struct irq_chip ipic_irq_chip = {
 626         .typename       = " IPIC  ",
 627         .unmask         = ipic_unmask_irq,
 628         .mask           = ipic_mask_irq,
 629         .mask_ack       = ipic_mask_irq_and_ack,
 630         .ack            = ipic_ack_irq,
 631         .set_type       = ipic_set_irq_type,
 632 };
 633
 634 static int ipic_host_match(struct irq_host *h, struct device_node *node)
 635 {
 636         /* Exact match, unless ipic node is NULL */
 637         return h->of_node == NULL || h->of_node == node;
 638 }
 639
 640 static int ipic_host_map(struct irq_host *h, unsigned int virq,
 641                          irq_hw_number_t hw)
 642 {
 643         struct ipic *ipic = h->host_data;
 644         struct irq_chip *chip;
 645
 646         /* Default chip */
 647         chip = &ipic->hc_irq;
 648
 649         set_irq_chip_data(virq, ipic);
 650         set_irq_chip_and_handler(virq, chip, handle_level_irq);
 651
 652         /* Set default irq type */
 653         set_irq_type(virq, IRQ_TYPE_NONE);
 654
 655         return 0;
 656 }
 657
 658 static int ipic_host_xlate(struct irq_host *h, struct device_node *ct,
 659                            u32 *intspec, unsigned int intsize,
 660                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 661
 662 {
 663         /* interrupt sense values coming from the device tree equal either
 664          * LEVEL_LOW (low assertion) or EDGE_FALLING (high-to-low change)
 665          */
 666         *out_hwirq = intspec[0];
 667         if (intsize > 1)
 668                 *out_flags = intspec[1];
 669         else
 670                 *out_flags = IRQ_TYPE_NONE;
 671         return 0;
 672 }
 673
 674 static struct irq_host_ops ipic_host_ops = {
 675         .match  = ipic_host_match,
 676         .map    = ipic_host_map,
 677         .xlate  = ipic_host_xlate,
 678 };
 679
 680 struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
 681 {
 682         struct ipic     *ipic;
 683         struct resource res;
 684         u32 temp = 0, ret;
 685
 686         ipic = alloc_bootmem(sizeof(struct ipic));
 687         if (ipic == NULL)
 688                 return NULL;
 689
 690         memset(ipic, 0, sizeof(struct ipic));
 691
 692         ipic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR,
 693                                        NR_IPIC_INTS,
 694                                        &ipic_host_ops, 0);
 695         if (ipic->irqhost == NULL) {
 696                 of_node_put(node);
 697                 return NULL;
 698         }
 699
 700         ret = of_address_to_resource(node, 0, &res);
 701         if (ret) {
 702                 of_node_put(node);
 703                 return NULL;
 704         }
 705
 706         ipic->regs = ioremap(res.start, res.end - res.start + 1);
 707
 708         ipic->irqhost->host_data = ipic;
 709         ipic->hc_irq = ipic_irq_chip;
 710
 711         /* init hw */
 712         ipic_write(ipic->regs, IPIC_SICNR, 0x0);
 713
 714         /* default priority scheme is grouped. If spread mode is required
 715          * configure SICFR accordingly */
 716         if (flags & IPIC_SPREADMODE_GRP_A)
 717                 temp |= SICFR_IPSA;
 718         if (flags & IPIC_SPREADMODE_GRP_B)
 719                 temp |= SICFR_IPSB;
 720         if (flags & IPIC_SPREADMODE_GRP_C)
 721                 temp |= SICFR_IPSC;
 722         if (flags & IPIC_SPREADMODE_GRP_D)
 723                 temp |= SICFR_IPSD;
 724         if (flags & IPIC_SPREADMODE_MIX_A)
 725                 temp |= SICFR_MPSA;
 726         if (flags & IPIC_SPREADMODE_MIX_B)
 727                 temp |= SICFR_MPSB;
 728
 729         ipic_write(ipic->regs, IPIC_SICFR, temp);
 730
 731         /* handle MCP route */
 732         temp = 0;
 733         if (flags & IPIC_DISABLE_MCP_OUT)
 734                 temp = SERCR_MCPR;
 735         ipic_write(ipic->regs, IPIC_SERCR, temp);
 736
 737         /* handle routing of IRQ0 to MCP */
 738         temp = ipic_read(ipic->regs, IPIC_SEMSR);
 739
 740         if (flags & IPIC_IRQ0_MCP)
 741                 temp |= SEMSR_SIRQ0;
 742         else
 743                 temp &= ~SEMSR_SIRQ0;
 744
 745         ipic_write(ipic->regs, IPIC_SEMSR, temp);
 746
 747         primary_ipic = ipic;
 748         irq_set_default_host(primary_ipic->irqhost);
 749
 750         printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS,
 751                         primary_ipic->regs);
 752
 753         return ipic;
 754 }
 755
 756 int ipic_set_priority(unsigned int virq, unsigned int priority)
 757 {
 758         struct ipic *ipic = ipic_from_irq(virq);
 759         unsigned int src = ipic_irq_to_hw(virq);
 760         u32 temp;
 761
 762         if (priority > 7)
 763                 return -EINVAL;
 764         if (src > 127)
 765                 return -EINVAL;
 766         if (ipic_info[src].prio == 0)
 767                 return -EINVAL;
 768
 769         temp = ipic_read(ipic->regs, ipic_info[src].prio);
 770
 771         if (priority < 4) {
 772                 temp &= ~(0x7 << (20 + (3 - priority) * 3));
 773                 temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3);
 774         } else {
 775                 temp &= ~(0x7 << (4 + (7 - priority) * 3));
 776                 temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3);
 777         }
 778
 779         ipic_write(ipic->regs, ipic_info[src].prio, temp);
 780
 781         return 0;
 782 }
 783
 784 void ipic_set_highest_priority(unsigned int virq)
 785 {
 786         struct ipic *ipic = ipic_from_irq(virq);
 787         unsigned int src = ipic_irq_to_hw(virq);
 788         u32 temp;
 789
 790         temp = ipic_read(ipic->regs, IPIC_SICFR);
 791
 792         /* clear and set HPI */
 793         temp &= 0x7f000000;
 794         temp |= (src & 0x7f) << 24;
 795
 796         ipic_write(ipic->regs, IPIC_SICFR, temp);
 797 }
 798
 799 void ipic_set_default_priority(void)
 800 {
 801         ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT);
 802         ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT);
 803         ipic_write(primary_ipic->regs, IPIC_SIPRR_C, IPIC_PRIORITY_DEFAULT);
 804         ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_PRIORITY_DEFAULT);
 805         ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_PRIORITY_DEFAULT);
 806         ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_PRIORITY_DEFAULT);
 807 }
 808
 809 void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
 810 {
 811         struct ipic *ipic = primary_ipic;
 812         u32 temp;
 813
 814         temp = ipic_read(ipic->regs, IPIC_SERMR);
 815         temp |= (1 << (31 - mcp_irq));
 816         ipic_write(ipic->regs, IPIC_SERMR, temp);
 817 }
 818
 819 void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq)
 820 {
 821         struct ipic *ipic = primary_ipic;
 822         u32 temp;
 823
 824         temp = ipic_read(ipic->regs, IPIC_SERMR);
 825         temp &= (1 << (31 - mcp_irq));
 826         ipic_write(ipic->regs, IPIC_SERMR, temp);
 827 }
 828
 829 u32 ipic_get_mcp_status(void)
 830 {
 831         return ipic_read(primary_ipic->regs, IPIC_SERMR);
 832 }
 833
 834 void ipic_clear_mcp_status(u32 mask)
 835 {
 836         ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
 837 }
 838
 839 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
 840 unsigned int ipic_get_irq(void)
 841 {
 842         int irq;
 843
 844         BUG_ON(primary_ipic == NULL);
 845
 846 #define IPIC_SIVCR_VECTOR_MASK  0x7f
 847         irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;
 848
 849         if (irq == 0)    /* 0 --> no irq is pending */
 850                 return NO_IRQ;
 851
 852         return irq_linear_revmap(primary_ipic->irqhost, irq);
 853 }
 854
 855 static struct sysdev_class ipic_sysclass = {
 856         set_kset_name("ipic"),
 857 };
 858
 859 static struct sys_device device_ipic = {
 860         .id             = 0,
 861         .cls            = &ipic_sysclass,
 862 };
 863
 864 static int __init init_ipic_sysfs(void)
 865 {
 866         int rc;
 867
 868         if (!primary_ipic->regs)
 869                 return -ENODEV;
 870         printk(KERN_DEBUG "Registering ipic with sysfs...\n");
 871
 872         rc = sysdev_class_register(&ipic_sysclass);
 873         if (rc) {
 874                 printk(KERN_ERR "Failed registering ipic sys class\n");
 875                 return -ENODEV;
 876         }
 877         rc = sysdev_register(&device_ipic);
 878         if (rc) {
 879                 printk(KERN_ERR "Failed registering ipic sys device\n");
 880                 return -ENODEV;
 881         }
 882         return 0;
 883 }
 884
 885 subsys_initcall(init_ipic_sysfs);