2 * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
4 * Author: Tony Li <tony.li@freescale.com>
5 * Jason Jin <Jason.jin@freescale.com>
7 * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; version 2 of the
15 #include <linux/irq.h>
16 #include <linux/bootmem.h>
17 #include <linux/msi.h>
18 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/of_platform.h>
21 #include <sysdev/fsl_soc.h>
23 #include <asm/hw_irq.h>
24 #include <asm/ppc-pci.h>
31 struct fsl_msi_feature {
33 u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */
36 struct fsl_msi_cascade_data {
37 struct fsl_msi *msi_data;
41 static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
43 return in_be32(base + (reg >> 2));
47 * We do not need this actually. The MSIR register has been read once
48 * in the cascade interrupt. So, this MSI interrupt has been acked
50 static void fsl_msi_end_irq(struct irq_data *d)
54 static struct irq_chip fsl_msi_chip = {
55 .irq_mask = mask_msi_irq,
56 .irq_unmask = unmask_msi_irq,
57 .irq_ack = fsl_msi_end_irq,
61 static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
64 struct fsl_msi *msi_data = h->host_data;
65 struct irq_chip *chip = &fsl_msi_chip;
67 irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);
69 irq_set_chip_data(virq, msi_data);
70 irq_set_chip_and_handler(virq, chip, handle_edge_irq);
75 static struct irq_host_ops fsl_msi_host_ops = {
76 .map = fsl_msi_host_map,
79 static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
83 rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
84 msi_data->irqhost->of_node);
88 rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap);
90 msi_bitmap_free(&msi_data->bitmap);
97 static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
99 if (type == PCI_CAP_ID_MSIX)
100 pr_debug("fslmsi: MSI-X untested, trying anyway.\n");
105 static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
107 struct msi_desc *entry;
108 struct fsl_msi *msi_data;
109 irq_hw_number_t hwirq;
111 list_for_each_entry(entry, &pdev->msi_list, list) {
112 if (entry->irq == NO_IRQ)
114 hwirq = virq_to_hw(entry->irq);
115 msi_data = irq_get_chip_data(entry->irq);
116 irq_set_msi_desc(entry->irq, NULL);
117 irq_dispose_mapping(entry->irq);
118 msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
124 static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
126 struct fsl_msi *fsl_msi_data)
128 struct fsl_msi *msi_data = fsl_msi_data;
129 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
130 u64 address; /* Physical address of the MSIIR */
134 /* If the msi-address-64 property exists, then use it */
135 reg = of_get_property(hose->dn, "msi-address-64", &len);
136 if (reg && (len == sizeof(u64)))
137 address = be64_to_cpup(reg);
139 address = fsl_pci_immrbar_base(hose) + msi_data->msiir_offset;
141 msg->address_lo = lower_32_bits(address);
142 msg->address_hi = upper_32_bits(address);
146 pr_debug("%s: allocated srs: %d, ibs: %d\n",
147 __func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
150 static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
152 int rc, hwirq = -ENOMEM;
154 struct msi_desc *entry;
156 struct fsl_msi *msi_data;
158 list_for_each_entry(entry, &pdev->msi_list, list) {
159 list_for_each_entry(msi_data, &msi_head, list) {
160 hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
167 pr_debug("%s: fail allocating msi interrupt\n",
172 virq = irq_create_mapping(msi_data->irqhost, hwirq);
174 if (virq == NO_IRQ) {
175 pr_debug("%s: fail mapping hwirq 0x%x\n",
177 msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
181 /* chip_data is msi_data via host->hostdata in host->map() */
182 irq_set_msi_desc(virq, entry);
184 fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
185 write_msi_msg(virq, &msg);
190 /* free by the caller of this function */
194 static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
196 struct irq_chip *chip = irq_desc_get_chip(desc);
197 struct irq_data *idata = irq_desc_get_irq_data(desc);
198 unsigned int cascade_irq;
199 struct fsl_msi *msi_data;
204 struct fsl_msi_cascade_data *cascade_data;
206 cascade_data = irq_get_handler_data(irq);
207 msi_data = cascade_data->msi_data;
209 raw_spin_lock(&desc->lock);
210 if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
211 if (chip->irq_mask_ack)
212 chip->irq_mask_ack(idata);
214 chip->irq_mask(idata);
215 chip->irq_ack(idata);
219 if (unlikely(irqd_irq_inprogress(idata)))
222 msir_index = cascade_data->index;
224 if (msir_index >= NR_MSI_REG)
225 cascade_irq = NO_IRQ;
227 irqd_set_chained_irq_inprogress(idata);
228 switch (msi_data->feature & FSL_PIC_IP_MASK) {
229 case FSL_PIC_IP_MPIC:
230 msir_value = fsl_msi_read(msi_data->msi_regs,
233 case FSL_PIC_IP_IPIC:
234 msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
239 intr_index = ffs(msir_value) - 1;
241 cascade_irq = irq_linear_revmap(msi_data->irqhost,
242 msir_index * IRQS_PER_MSI_REG +
243 intr_index + have_shift);
244 if (cascade_irq != NO_IRQ)
245 generic_handle_irq(cascade_irq);
246 have_shift += intr_index + 1;
247 msir_value = msir_value >> (intr_index + 1);
249 irqd_clr_chained_irq_inprogress(idata);
251 switch (msi_data->feature & FSL_PIC_IP_MASK) {
252 case FSL_PIC_IP_MPIC:
253 chip->irq_eoi(idata);
255 case FSL_PIC_IP_IPIC:
256 if (!irqd_irq_disabled(idata) && chip->irq_unmask)
257 chip->irq_unmask(idata);
261 raw_spin_unlock(&desc->lock);
264 static int fsl_of_msi_remove(struct platform_device *ofdev)
266 struct fsl_msi *msi = platform_get_drvdata(ofdev);
268 struct fsl_msi_cascade_data *cascade_data;
270 if (msi->list.prev != NULL)
271 list_del(&msi->list);
272 for (i = 0; i < NR_MSI_REG; i++) {
273 virq = msi->msi_virqs[i];
274 if (virq != NO_IRQ) {
275 cascade_data = irq_get_handler_data(virq);
277 irq_dispose_mapping(virq);
280 if (msi->bitmap.bitmap)
281 msi_bitmap_free(&msi->bitmap);
282 iounmap(msi->msi_regs);
288 static int __devinit fsl_msi_setup_hwirq(struct fsl_msi *msi,
289 struct platform_device *dev,
290 int offset, int irq_index)
292 struct fsl_msi_cascade_data *cascade_data = NULL;
295 virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
296 if (virt_msir == NO_IRQ) {
297 dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n",
298 __func__, irq_index);
302 cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL);
304 dev_err(&dev->dev, "No memory for MSI cascade data\n");
308 msi->msi_virqs[irq_index] = virt_msir;
309 cascade_data->index = offset;
310 cascade_data->msi_data = msi;
311 irq_set_handler_data(virt_msir, cascade_data);
312 irq_set_chained_handler(virt_msir, fsl_msi_cascade);
317 static const struct of_device_id fsl_of_msi_ids[];
318 static int __devinit fsl_of_msi_probe(struct platform_device *dev)
320 const struct of_device_id *match;
323 int err, i, j, irq_index, count;
326 struct fsl_msi_feature *features;
329 static const u32 all_avail[] = { 0, NR_MSI_IRQS };
331 match = of_match_device(fsl_of_msi_ids, &dev->dev);
334 features = match->data;
336 printk(KERN_DEBUG "Setting up Freescale MSI support\n");
338 msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
340 dev_err(&dev->dev, "No memory for MSI structure\n");
343 platform_set_drvdata(dev, msi);
345 msi->irqhost = irq_alloc_host(dev->dev.of_node, IRQ_HOST_MAP_LINEAR,
346 NR_MSI_IRQS, &fsl_msi_host_ops, 0);
348 if (msi->irqhost == NULL) {
349 dev_err(&dev->dev, "No memory for MSI irqhost\n");
354 /* Get the MSI reg base */
355 err = of_address_to_resource(dev->dev.of_node, 0, &res);
357 dev_err(&dev->dev, "%s resource error!\n",
358 dev->dev.of_node->full_name);
362 msi->msi_regs = ioremap(res.start, resource_size(&res));
363 if (!msi->msi_regs) {
364 dev_err(&dev->dev, "ioremap problem failed\n");
368 msi->feature = features->fsl_pic_ip;
370 msi->irqhost->host_data = msi;
372 msi->msiir_offset = features->msiir_offset + (res.start & 0xfffff);
374 rc = fsl_msi_init_allocator(msi);
376 dev_err(&dev->dev, "Error allocating MSI bitmap\n");
380 p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
381 if (p && len % (2 * sizeof(u32)) != 0) {
382 dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
390 len = sizeof(all_avail);
393 for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
394 if (p[i * 2] % IRQS_PER_MSI_REG ||
395 p[i * 2 + 1] % IRQS_PER_MSI_REG) {
396 printk(KERN_WARNING "%s: %s: msi available range of %u at %u is not IRQ-aligned\n",
397 __func__, dev->dev.of_node->full_name,
398 p[i * 2 + 1], p[i * 2]);
403 offset = p[i * 2] / IRQS_PER_MSI_REG;
404 count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
406 for (j = 0; j < count; j++, irq_index++) {
407 err = fsl_msi_setup_hwirq(msi, dev, offset + j, irq_index);
413 list_add_tail(&msi->list, &msi_head);
415 /* The multiple setting ppc_md.setup_msi_irqs will not harm things */
416 if (!ppc_md.setup_msi_irqs) {
417 ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
418 ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
419 ppc_md.msi_check_device = fsl_msi_check_device;
420 } else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
421 dev_err(&dev->dev, "Different MSI driver already installed!\n");
427 fsl_of_msi_remove(dev);
431 static const struct fsl_msi_feature mpic_msi_feature = {
432 .fsl_pic_ip = FSL_PIC_IP_MPIC,
433 .msiir_offset = 0x140,
436 static const struct fsl_msi_feature ipic_msi_feature = {
437 .fsl_pic_ip = FSL_PIC_IP_IPIC,
438 .msiir_offset = 0x38,
441 static const struct of_device_id fsl_of_msi_ids[] = {
443 .compatible = "fsl,mpic-msi",
444 .data = (void *)&mpic_msi_feature,
447 .compatible = "fsl,ipic-msi",
448 .data = (void *)&ipic_msi_feature,
453 static struct platform_driver fsl_of_msi_driver = {
456 .owner = THIS_MODULE,
457 .of_match_table = fsl_of_msi_ids,
459 .probe = fsl_of_msi_probe,
460 .remove = fsl_of_msi_remove,
463 static __init int fsl_of_msi_init(void)
465 return platform_driver_register(&fsl_of_msi_driver);
468 subsys_initcall(fsl_of_msi_init);