arch/powerpc/sysdev/cpm1.c

   1 /*
   2  * General Purpose functions for the global management of the
   3  * Communication Processor Module.
   4  * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
   5  *
   6  * In addition to the individual control of the communication
   7  * channels, there are a few functions that globally affect the
   8  * communication processor.
   9  *
  10  * Buffer descriptors must be allocated from the dual ported memory
  11  * space.  The allocator for that is here.  When the communication
  12  * process is reset, we reclaim the memory available.  There is
  13  * currently no deallocator for this memory.
  14  * The amount of space available is platform dependent.  On the
  15  * MBX, the EPPC software loads additional microcode into the
  16  * communication processor, and uses some of the DP ram for this
  17  * purpose.  Current, the first 512 bytes and the last 256 bytes of
  18  * memory are used.  Right now I am conservative and only use the
  19  * memory that can never be used for microcode.  If there are
  20  * applications that require more DP ram, we can expand the boundaries
  21  * but then we have to be careful of any downloaded microcode.
  22  */
  23 #include <linux/errno.h>
  24 #include <linux/sched.h>
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/param.h>
  28 #include <linux/string.h>
  29 #include <linux/mm.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/irq.h>
  32 #include <linux/module.h>
  33 #include <linux/spinlock.h>
  34 #include <asm/page.h>
  35 #include <asm/pgtable.h>
  36 #include <asm/8xx_immap.h>
  37 #include <asm/cpm1.h>
  38 #include <asm/io.h>
  39 #include <asm/tlbflush.h>
  40 #include <asm/rheap.h>
  41 #include <asm/prom.h>
  42 #include <asm/cpm.h>
  43
  44 #include <asm/fs_pd.h>
  45
  46 #ifdef CONFIG_8xx_GPIO
  47 #include <linux/of_gpio.h>
  48 #endif
  49
  50 #define CPM_MAP_SIZE    (0x4000)
  51
  52 cpm8xx_t __iomem *cpmp;  /* Pointer to comm processor space */
  53 immap_t __iomem *mpc8xx_immr;
  54 static cpic8xx_t __iomem *cpic_reg;
  55
  56 static struct irq_host *cpm_pic_host;
  57
  58 static void cpm_mask_irq(unsigned int irq)
  59 {
  60         unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
  61
  62         clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
  63 }
  64
  65 static void cpm_unmask_irq(unsigned int irq)
  66 {
  67         unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
  68
  69         setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
  70 }
  71
  72 static void cpm_end_irq(unsigned int irq)
  73 {
  74         unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
  75
  76         out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec));
  77 }
  78
  79 static struct irq_chip cpm_pic = {
  80         .typename = " CPM PIC ",
  81         .mask = cpm_mask_irq,
  82         .unmask = cpm_unmask_irq,
  83         .eoi = cpm_end_irq,
  84 };
  85
  86 int cpm_get_irq(void)
  87 {
  88         int cpm_vec;
  89
  90         /* Get the vector by setting the ACK bit and then reading
  91          * the register.
  92          */
  93         out_be16(&cpic_reg->cpic_civr, 1);
  94         cpm_vec = in_be16(&cpic_reg->cpic_civr);
  95         cpm_vec >>= 11;
  96
  97         return irq_linear_revmap(cpm_pic_host, cpm_vec);
  98 }
  99
 100 static int cpm_pic_host_map(struct irq_host *h, unsigned int virq,
 101                           irq_hw_number_t hw)
 102 {
 103         pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
 104
 105         get_irq_desc(virq)->status |= IRQ_LEVEL;
 106         set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
 107         return 0;
 108 }
 109
 110 /* The CPM can generate the error interrupt when there is a race condition
 111  * between generating and masking interrupts.  All we have to do is ACK it
 112  * and return.  This is a no-op function so we don't need any special
 113  * tests in the interrupt handler.
 114  */
 115 static irqreturn_t cpm_error_interrupt(int irq, void *dev)
 116 {
 117         return IRQ_HANDLED;
 118 }
 119
 120 static struct irqaction cpm_error_irqaction = {
 121         .handler = cpm_error_interrupt,
 122         .mask = CPU_MASK_NONE,
 123         .name = "error",
 124 };
 125
 126 static struct irq_host_ops cpm_pic_host_ops = {
 127         .map = cpm_pic_host_map,
 128 };
 129
 130 unsigned int cpm_pic_init(void)
 131 {
 132         struct device_node *np = NULL;
 133         struct resource res;
 134         unsigned int sirq = NO_IRQ, hwirq, eirq;
 135         int ret;
 136
 137         pr_debug("cpm_pic_init\n");
 138
 139         np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic");
 140         if (np == NULL)
 141                 np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
 142         if (np == NULL) {
 143                 printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
 144                 return sirq;
 145         }
 146
 147         ret = of_address_to_resource(np, 0, &res);
 148         if (ret)
 149                 goto end;
 150
 151         cpic_reg = ioremap(res.start, res.end - res.start + 1);
 152         if (cpic_reg == NULL)
 153                 goto end;
 154
 155         sirq = irq_of_parse_and_map(np, 0);
 156         if (sirq == NO_IRQ)
 157                 goto end;
 158
 159         /* Initialize the CPM interrupt controller. */
 160         hwirq = (unsigned int)irq_map[sirq].hwirq;
 161         out_be32(&cpic_reg->cpic_cicr,
 162             (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
 163                 ((hwirq/2) << 13) | CICR_HP_MASK);
 164
 165         out_be32(&cpic_reg->cpic_cimr, 0);
 166
 167         cpm_pic_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR,
 168                                       64, &cpm_pic_host_ops, 64);
 169         if (cpm_pic_host == NULL) {
 170                 printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
 171                 sirq = NO_IRQ;
 172                 goto end;
 173         }
 174
 175         /* Install our own error handler. */
 176         np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
 177         if (np == NULL)
 178                 np = of_find_node_by_type(NULL, "cpm");
 179         if (np == NULL) {
 180                 printk(KERN_ERR "CPM PIC init: can not find cpm node\n");
 181                 goto end;
 182         }
 183
 184         eirq = irq_of_parse_and_map(np, 0);
 185         if (eirq == NO_IRQ)
 186                 goto end;
 187
 188         if (setup_irq(eirq, &cpm_error_irqaction))
 189                 printk(KERN_ERR "Could not allocate CPM error IRQ!");
 190
 191         setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
 192
 193 end:
 194         of_node_put(np);
 195         return sirq;
 196 }
 197
 198 void __init cpm_reset(void)
 199 {
 200         sysconf8xx_t __iomem *siu_conf;
 201
 202         mpc8xx_immr = ioremap(get_immrbase(), 0x4000);
 203         if (!mpc8xx_immr) {
 204                 printk(KERN_CRIT "Could not map IMMR\n");
 205                 return;
 206         }
 207
 208         cpmp = &mpc8xx_immr->im_cpm;
 209
 210 #ifndef CONFIG_PPC_EARLY_DEBUG_CPM
 211         /* Perform a reset.
 212         */
 213         out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
 214
 215         /* Wait for it.
 216         */
 217         while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
 218 #endif
 219
 220 #ifdef CONFIG_UCODE_PATCH
 221         cpm_load_patch(cpmp);
 222 #endif
 223
 224         /* Set SDMA Bus Request priority 5.
 225          * On 860T, this also enables FEC priority 6.  I am not sure
 226          * this is what we realy want for some applications, but the
 227          * manual recommends it.
 228          * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
 229          */
 230         siu_conf = immr_map(im_siu_conf);
 231         out_be32(&siu_conf->sc_sdcr, 1);
 232         immr_unmap(siu_conf);
 233
 234         cpm_muram_init();
 235 }
 236
 237 static DEFINE_SPINLOCK(cmd_lock);
 238
 239 #define MAX_CR_CMD_LOOPS        10000
 240
 241 int cpm_command(u32 command, u8 opcode)
 242 {
 243         int i, ret;
 244         unsigned long flags;
 245
 246         if (command & 0xffffff0f)
 247                 return -EINVAL;
 248
 249         spin_lock_irqsave(&cmd_lock, flags);
 250
 251         ret = 0;
 252         out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8));
 253         for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
 254                 if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
 255                         goto out;
 256
 257         printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
 258         ret = -EIO;
 259 out:
 260         spin_unlock_irqrestore(&cmd_lock, flags);
 261         return ret;
 262 }
 263 EXPORT_SYMBOL(cpm_command);
 264
 265 /* Set a baud rate generator.  This needs lots of work.  There are
 266  * four BRGs, any of which can be wired to any channel.
 267  * The internal baud rate clock is the system clock divided by 16.
 268  * This assumes the baudrate is 16x oversampled by the uart.
 269  */
 270 #define BRG_INT_CLK             (get_brgfreq())
 271 #define BRG_UART_CLK            (BRG_INT_CLK/16)
 272 #define BRG_UART_CLK_DIV16      (BRG_UART_CLK/16)
 273
 274 void
 275 cpm_setbrg(uint brg, uint rate)
 276 {
 277         u32 __iomem *bp;
 278
 279         /* This is good enough to get SMCs running.....
 280         */
 281         bp = &cpmp->cp_brgc1;
 282         bp += brg;
 283         /* The BRG has a 12-bit counter.  For really slow baud rates (or
 284          * really fast processors), we may have to further divide by 16.
 285          */
 286         if (((BRG_UART_CLK / rate) - 1) < 4096)
 287                 out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
 288         else
 289                 out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
 290                               CPM_BRG_EN | CPM_BRG_DIV16);
 291 }
 292
 293 struct cpm_ioport16 {
 294         __be16 dir, par, odr_sor, dat, intr;
 295         __be16 res[3];
 296 };
 297
 298 struct cpm_ioport32b {
 299         __be32 dir, par, odr, dat;
 300 };
 301
 302 struct cpm_ioport32e {
 303         __be32 dir, par, sor, odr, dat;
 304 };
 305
 306 static void cpm1_set_pin32(int port, int pin, int flags)
 307 {
 308         struct cpm_ioport32e __iomem *iop;
 309         pin = 1 << (31 - pin);
 310
 311         if (port == CPM_PORTB)
 312                 iop = (struct cpm_ioport32e __iomem *)
 313                       &mpc8xx_immr->im_cpm.cp_pbdir;
 314         else
 315                 iop = (struct cpm_ioport32e __iomem *)
 316                       &mpc8xx_immr->im_cpm.cp_pedir;
 317
 318         if (flags & CPM_PIN_OUTPUT)
 319                 setbits32(&iop->dir, pin);
 320         else
 321                 clrbits32(&iop->dir, pin);
 322
 323         if (!(flags & CPM_PIN_GPIO))
 324                 setbits32(&iop->par, pin);
 325         else
 326                 clrbits32(&iop->par, pin);
 327
 328         if (port == CPM_PORTB) {
 329                 if (flags & CPM_PIN_OPENDRAIN)
 330                         setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
 331                 else
 332                         clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
 333         }
 334
 335         if (port == CPM_PORTE) {
 336                 if (flags & CPM_PIN_SECONDARY)
 337                         setbits32(&iop->sor, pin);
 338                 else
 339                         clrbits32(&iop->sor, pin);
 340
 341                 if (flags & CPM_PIN_OPENDRAIN)
 342                         setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
 343                 else
 344                         clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
 345         }
 346 }
 347
 348 static void cpm1_set_pin16(int port, int pin, int flags)
 349 {
 350         struct cpm_ioport16 __iomem *iop =
 351                 (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport;
 352
 353         pin = 1 << (15 - pin);
 354
 355         if (port != 0)
 356                 iop += port - 1;
 357
 358         if (flags & CPM_PIN_OUTPUT)
 359                 setbits16(&iop->dir, pin);
 360         else
 361                 clrbits16(&iop->dir, pin);
 362
 363         if (!(flags & CPM_PIN_GPIO))
 364                 setbits16(&iop->par, pin);
 365         else
 366                 clrbits16(&iop->par, pin);
 367
 368         if (port == CPM_PORTA) {
 369                 if (flags & CPM_PIN_OPENDRAIN)
 370                         setbits16(&iop->odr_sor, pin);
 371                 else
 372                         clrbits16(&iop->odr_sor, pin);
 373         }
 374         if (port == CPM_PORTC) {
 375                 if (flags & CPM_PIN_SECONDARY)
 376                         setbits16(&iop->odr_sor, pin);
 377                 else
 378                         clrbits16(&iop->odr_sor, pin);
 379         }
 380 }
 381
 382 void cpm1_set_pin(enum cpm_port port, int pin, int flags)
 383 {
 384         if (port == CPM_PORTB || port == CPM_PORTE)
 385                 cpm1_set_pin32(port, pin, flags);
 386         else
 387                 cpm1_set_pin16(port, pin, flags);
 388 }
 389
 390 int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
 391 {
 392         int shift;
 393         int i, bits = 0;
 394         u32 __iomem *reg;
 395         u32 mask = 7;
 396
 397         u8 clk_map[][3] = {
 398                 {CPM_CLK_SCC1, CPM_BRG1, 0},
 399                 {CPM_CLK_SCC1, CPM_BRG2, 1},
 400                 {CPM_CLK_SCC1, CPM_BRG3, 2},
 401                 {CPM_CLK_SCC1, CPM_BRG4, 3},
 402                 {CPM_CLK_SCC1, CPM_CLK1, 4},
 403                 {CPM_CLK_SCC1, CPM_CLK2, 5},
 404                 {CPM_CLK_SCC1, CPM_CLK3, 6},
 405                 {CPM_CLK_SCC1, CPM_CLK4, 7},
 406
 407                 {CPM_CLK_SCC2, CPM_BRG1, 0},
 408                 {CPM_CLK_SCC2, CPM_BRG2, 1},
 409                 {CPM_CLK_SCC2, CPM_BRG3, 2},
 410                 {CPM_CLK_SCC2, CPM_BRG4, 3},
 411                 {CPM_CLK_SCC2, CPM_CLK1, 4},
 412                 {CPM_CLK_SCC2, CPM_CLK2, 5},
 413                 {CPM_CLK_SCC2, CPM_CLK3, 6},
 414                 {CPM_CLK_SCC2, CPM_CLK4, 7},
 415
 416                 {CPM_CLK_SCC3, CPM_BRG1, 0},
 417                 {CPM_CLK_SCC3, CPM_BRG2, 1},
 418                 {CPM_CLK_SCC3, CPM_BRG3, 2},
 419                 {CPM_CLK_SCC3, CPM_BRG4, 3},
 420                 {CPM_CLK_SCC3, CPM_CLK5, 4},
 421                 {CPM_CLK_SCC3, CPM_CLK6, 5},
 422                 {CPM_CLK_SCC3, CPM_CLK7, 6},
 423                 {CPM_CLK_SCC3, CPM_CLK8, 7},
 424
 425                 {CPM_CLK_SCC4, CPM_BRG1, 0},
 426                 {CPM_CLK_SCC4, CPM_BRG2, 1},
 427                 {CPM_CLK_SCC4, CPM_BRG3, 2},
 428                 {CPM_CLK_SCC4, CPM_BRG4, 3},
 429                 {CPM_CLK_SCC4, CPM_CLK5, 4},
 430                 {CPM_CLK_SCC4, CPM_CLK6, 5},
 431                 {CPM_CLK_SCC4, CPM_CLK7, 6},
 432                 {CPM_CLK_SCC4, CPM_CLK8, 7},
 433
 434                 {CPM_CLK_SMC1, CPM_BRG1, 0},
 435                 {CPM_CLK_SMC1, CPM_BRG2, 1},
 436                 {CPM_CLK_SMC1, CPM_BRG3, 2},
 437                 {CPM_CLK_SMC1, CPM_BRG4, 3},
 438                 {CPM_CLK_SMC1, CPM_CLK1, 4},
 439                 {CPM_CLK_SMC1, CPM_CLK2, 5},
 440                 {CPM_CLK_SMC1, CPM_CLK3, 6},
 441                 {CPM_CLK_SMC1, CPM_CLK4, 7},
 442
 443                 {CPM_CLK_SMC2, CPM_BRG1, 0},
 444                 {CPM_CLK_SMC2, CPM_BRG2, 1},
 445                 {CPM_CLK_SMC2, CPM_BRG3, 2},
 446                 {CPM_CLK_SMC2, CPM_BRG4, 3},
 447                 {CPM_CLK_SMC2, CPM_CLK5, 4},
 448                 {CPM_CLK_SMC2, CPM_CLK6, 5},
 449                 {CPM_CLK_SMC2, CPM_CLK7, 6},
 450                 {CPM_CLK_SMC2, CPM_CLK8, 7},
 451         };
 452
 453         switch (target) {
 454         case CPM_CLK_SCC1:
 455                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 456                 shift = 0;
 457                 break;
 458
 459         case CPM_CLK_SCC2:
 460                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 461                 shift = 8;
 462                 break;
 463
 464         case CPM_CLK_SCC3:
 465                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 466                 shift = 16;
 467                 break;
 468
 469         case CPM_CLK_SCC4:
 470                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 471                 shift = 24;
 472                 break;
 473
 474         case CPM_CLK_SMC1:
 475                 reg = &mpc8xx_immr->im_cpm.cp_simode;
 476                 shift = 12;
 477                 break;
 478
 479         case CPM_CLK_SMC2:
 480                 reg = &mpc8xx_immr->im_cpm.cp_simode;
 481                 shift = 28;
 482                 break;
 483
 484         default:
 485                 printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n");
 486                 return -EINVAL;
 487         }
 488
 489         if (reg == &mpc8xx_immr->im_cpm.cp_sicr && mode == CPM_CLK_RX)
 490                 shift += 3;
 491
 492         for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
 493                 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
 494                         bits = clk_map[i][2];
 495                         break;
 496                 }
 497         }
 498
 499         if (i == ARRAY_SIZE(clk_map)) {
 500                 printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n");
 501                 return -EINVAL;
 502         }
 503
 504         bits <<= shift;
 505         mask <<= shift;
 506         out_be32(reg, (in_be32(reg) & ~mask) | bits);
 507
 508         return 0;
 509 }
 510
 511 /*
 512  * GPIO LIB API implementation
 513  */
 514 #ifdef CONFIG_8xx_GPIO
 515
 516 struct cpm1_gpio16_chip {
 517         struct of_mm_gpio_chip mm_gc;
 518         spinlock_t lock;
 519
 520         /* shadowed data register to clear/set bits safely */
 521         u16 cpdata;
 522 };
 523
 524 static inline struct cpm1_gpio16_chip *
 525 to_cpm1_gpio16_chip(struct of_mm_gpio_chip *mm_gc)
 526 {
 527         return container_of(mm_gc, struct cpm1_gpio16_chip, mm_gc);
 528 }
 529
 530 static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc)
 531 {
 532         struct cpm1_gpio16_chip *cpm1_gc = to_cpm1_gpio16_chip(mm_gc);
 533         struct cpm_ioport16 __iomem *iop = mm_gc->regs;
 534
 535         cpm1_gc->cpdata = in_be16(&iop->dat);
 536 }
 537
 538 static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio)
 539 {
 540         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 541         struct cpm_ioport16 __iomem *iop = mm_gc->regs;
 542         u16 pin_mask;
 543
 544         pin_mask = 1 << (15 - gpio);
 545
 546         return !!(in_be16(&iop->dat) & pin_mask);
 547 }
 548
 549 static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value)
 550 {
 551         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 552         struct cpm1_gpio16_chip *cpm1_gc = to_cpm1_gpio16_chip(mm_gc);
 553         struct cpm_ioport16 __iomem *iop = mm_gc->regs;
 554         unsigned long flags;
 555         u16 pin_mask = 1 << (15 - gpio);
 556
 557         spin_lock_irqsave(&cpm1_gc->lock, flags);
 558
 559         if (value)
 560                 cpm1_gc->cpdata |= pin_mask;
 561         else
 562                 cpm1_gc->cpdata &= ~pin_mask;
 563
 564         out_be16(&iop->dat, cpm1_gc->cpdata);
 565
 566         spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 567 }
 568
 569 static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 570 {
 571         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 572         struct cpm_ioport16 __iomem *iop = mm_gc->regs;
 573         u16 pin_mask;
 574
 575         pin_mask = 1 << (15 - gpio);
 576
 577         setbits16(&iop->dir, pin_mask);
 578
 579         cpm1_gpio16_set(gc, gpio, val);
 580
 581         return 0;
 582 }
 583
 584 static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio)
 585 {
 586         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 587         struct cpm_ioport16 __iomem *iop = mm_gc->regs;
 588         u16 pin_mask;
 589
 590         pin_mask = 1 << (15 - gpio);
 591
 592         clrbits16(&iop->dir, pin_mask);
 593
 594         return 0;
 595 }
 596
 597 int cpm1_gpiochip_add16(struct device_node *np)
 598 {
 599         struct cpm1_gpio16_chip *cpm1_gc;
 600         struct of_mm_gpio_chip *mm_gc;
 601         struct of_gpio_chip *of_gc;
 602         struct gpio_chip *gc;
 603
 604         cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
 605         if (!cpm1_gc)
 606                 return -ENOMEM;
 607
 608         spin_lock_init(&cpm1_gc->lock);
 609
 610         mm_gc = &cpm1_gc->mm_gc;
 611         of_gc = &mm_gc->of_gc;
 612         gc = &of_gc->gc;
 613
 614         mm_gc->save_regs = cpm1_gpio16_save_regs;
 615         of_gc->gpio_cells = 2;
 616         gc->ngpio = 16;
 617         gc->direction_input = cpm1_gpio16_dir_in;
 618         gc->direction_output = cpm1_gpio16_dir_out;
 619         gc->get = cpm1_gpio16_get;
 620         gc->set = cpm1_gpio16_set;
 621
 622         return of_mm_gpiochip_add(np, mm_gc);
 623 }
 624
 625 struct cpm1_gpio32_chip {
 626         struct of_mm_gpio_chip mm_gc;
 627         spinlock_t lock;
 628
 629         /* shadowed data register to clear/set bits safely */
 630         u32 cpdata;
 631 };
 632
 633 static inline struct cpm1_gpio32_chip *
 634 to_cpm1_gpio32_chip(struct of_mm_gpio_chip *mm_gc)
 635 {
 636         return container_of(mm_gc, struct cpm1_gpio32_chip, mm_gc);
 637 }
 638
 639 static void cpm1_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
 640 {
 641         struct cpm1_gpio32_chip *cpm1_gc = to_cpm1_gpio32_chip(mm_gc);
 642         struct cpm_ioport32b __iomem *iop = mm_gc->regs;
 643
 644         cpm1_gc->cpdata = in_be32(&iop->dat);
 645 }
 646
 647 static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
 648 {
 649         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 650         struct cpm_ioport32b __iomem *iop = mm_gc->regs;
 651         u32 pin_mask;
 652
 653         pin_mask = 1 << (31 - gpio);
 654
 655         return !!(in_be32(&iop->dat) & pin_mask);
 656 }
 657
 658 static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
 659 {
 660         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 661         struct cpm1_gpio32_chip *cpm1_gc = to_cpm1_gpio32_chip(mm_gc);
 662         struct cpm_ioport32b __iomem *iop = mm_gc->regs;
 663         unsigned long flags;
 664         u32 pin_mask = 1 << (31 - gpio);
 665
 666         spin_lock_irqsave(&cpm1_gc->lock, flags);
 667
 668         if (value)
 669                 cpm1_gc->cpdata |= pin_mask;
 670         else
 671                 cpm1_gc->cpdata &= ~pin_mask;
 672
 673         out_be32(&iop->dat, cpm1_gc->cpdata);
 674
 675         spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 676 }
 677
 678 static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 679 {
 680         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 681         struct cpm_ioport32b __iomem *iop = mm_gc->regs;
 682         u32 pin_mask;
 683
 684         pin_mask = 1 << (31 - gpio);
 685
 686         setbits32(&iop->dir, pin_mask);
 687
 688         cpm1_gpio32_set(gc, gpio, val);
 689
 690         return 0;
 691 }
 692
 693 static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
 694 {
 695         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 696         struct cpm_ioport32b __iomem *iop = mm_gc->regs;
 697         u32 pin_mask;
 698
 699         pin_mask = 1 << (31 - gpio);
 700
 701         clrbits32(&iop->dir, pin_mask);
 702
 703         return 0;
 704 }
 705
 706 int cpm1_gpiochip_add32(struct device_node *np)
 707 {
 708         struct cpm1_gpio32_chip *cpm1_gc;
 709         struct of_mm_gpio_chip *mm_gc;
 710         struct of_gpio_chip *of_gc;
 711         struct gpio_chip *gc;
 712
 713         cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
 714         if (!cpm1_gc)
 715                 return -ENOMEM;
 716
 717         spin_lock_init(&cpm1_gc->lock);
 718
 719         mm_gc = &cpm1_gc->mm_gc;
 720         of_gc = &mm_gc->of_gc;
 721         gc = &of_gc->gc;
 722
 723         mm_gc->save_regs = cpm1_gpio32_save_regs;
 724         of_gc->gpio_cells = 2;
 725         gc->ngpio = 32;
 726         gc->direction_input = cpm1_gpio32_dir_in;
 727         gc->direction_output = cpm1_gpio32_dir_out;
 728         gc->get = cpm1_gpio32_get;
 729         gc->set = cpm1_gpio32_set;
 730
 731         return of_mm_gpiochip_add(np, mm_gc);
 732 }
 733
 734 static int cpm_init_par_io(void)
 735 {
 736         struct device_node *np;
 737
 738         for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-a")
 739                 cpm1_gpiochip_add16(np);
 740
 741         for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-b")
 742                 cpm1_gpiochip_add32(np);
 743
 744         for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-c")
 745                 cpm1_gpiochip_add16(np);
 746
 747         for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-d")
 748                 cpm1_gpiochip_add16(np);
 749
 750         /* Port E uses CPM2 layout */
 751         for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-e")
 752                 cpm2_gpiochip_add32(np);
 753         return 0;
 754 }
 755 arch_initcall(cpm_init_par_io);
 756
 757 #endif /* CONFIG_8xx_GPIO */