2 * arch/powerpc/platforms/pseries/xics.c
4 * Copyright 2000 IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/types.h>
13 #include <linux/threads.h>
14 #include <linux/kernel.h>
15 #include <linux/irq.h>
16 #include <linux/smp.h>
17 #include <linux/interrupt.h>
18 #include <linux/signal.h>
19 #include <linux/init.h>
20 #include <linux/gfp.h>
21 #include <linux/radix-tree.h>
22 #include <linux/cpu.h>
24 #include <asm/firmware.h>
27 #include <asm/pgtable.h>
30 #include <asm/hvcall.h>
31 #include <asm/machdep.h>
32 #include <asm/i8259.h>
35 #include "plpar_wrappers.h"
37 static struct irq_host *xics_host;
40 #define XICS_IRQ_SPURIOUS 0
42 /* Want a priority other than 0. Various HW issues require this. */
43 #define DEFAULT_PRIORITY 5
46 * Mark IPIs as higher priority so we can take them inside interrupts that
47 * arent marked IRQF_DISABLED
49 #define IPI_PRIORITY 4
51 static unsigned int default_server = 0xFF;
52 static unsigned int default_distrib_server = 0;
53 static unsigned int interrupt_server_size = 8;
55 /* RTAS service tokens */
56 static int ibm_get_xive;
57 static int ibm_set_xive;
58 static int ibm_int_on;
59 static int ibm_int_off;
62 /* Direct hardware low level accessors */
64 /* The part of the interrupt presentation layer that we care about */
81 static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS];
83 static inline unsigned int direct_xirr_info_get(void)
85 int cpu = smp_processor_id();
87 return in_be32(&xics_per_cpu[cpu]->xirr.word);
90 static inline void direct_xirr_info_set(int value)
92 int cpu = smp_processor_id();
94 out_be32(&xics_per_cpu[cpu]->xirr.word, value);
97 static inline void direct_cppr_info(u8 value)
99 int cpu = smp_processor_id();
101 out_8(&xics_per_cpu[cpu]->xirr.bytes[0], value);
104 static inline void direct_qirr_info(int n_cpu, u8 value)
106 out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value);
110 /* LPAR low level accessors */
112 static inline unsigned int lpar_xirr_info_get(void)
114 unsigned long lpar_rc;
115 unsigned long return_value;
117 lpar_rc = plpar_xirr(&return_value);
118 if (lpar_rc != H_SUCCESS)
119 panic(" bad return code xirr - rc = %lx \n", lpar_rc);
120 return (unsigned int)return_value;
123 static inline void lpar_xirr_info_set(int value)
125 unsigned long lpar_rc;
126 unsigned long val64 = value & 0xffffffff;
128 lpar_rc = plpar_eoi(val64);
129 if (lpar_rc != H_SUCCESS)
130 panic("bad return code EOI - rc = %ld, value=%lx\n", lpar_rc,
134 static inline void lpar_cppr_info(u8 value)
136 unsigned long lpar_rc;
138 lpar_rc = plpar_cppr(value);
139 if (lpar_rc != H_SUCCESS)
140 panic("bad return code cppr - rc = %lx\n", lpar_rc);
143 static inline void lpar_qirr_info(int n_cpu , u8 value)
145 unsigned long lpar_rc;
147 lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value);
148 if (lpar_rc != H_SUCCESS)
149 panic("bad return code qirr - rc = %lx\n", lpar_rc);
153 /* Interface to generic irq subsystem */
156 static int get_irq_server(unsigned int virq, unsigned int strict_check)
159 /* For the moment only implement delivery to all cpus or one cpu */
160 cpumask_t cpumask = irq_desc[virq].affinity;
161 cpumask_t tmp = CPU_MASK_NONE;
163 if (!distribute_irqs)
164 return default_server;
166 if (!cpus_equal(cpumask, CPU_MASK_ALL)) {
167 cpus_and(tmp, cpu_online_map, cpumask);
169 server = first_cpu(tmp);
171 if (server < NR_CPUS)
172 return get_hard_smp_processor_id(server);
178 if (cpus_equal(cpu_online_map, cpu_present_map))
179 return default_distrib_server;
181 return default_server;
184 static int get_irq_server(unsigned int virq, unsigned int strict_check)
186 return default_server;
190 static void xics_unmask_irq(unsigned int virq)
196 pr_debug("xics: unmask virq %d\n", virq);
198 irq = (unsigned int)irq_map[virq].hwirq;
199 pr_debug(" -> map to hwirq 0x%x\n", irq);
200 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
203 server = get_irq_server(virq, 0);
205 call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server,
207 if (call_status != 0) {
208 printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_set_xive "
209 "returned %d\n", irq, call_status);
210 printk("set_xive %x, server %x\n", ibm_set_xive, server);
214 /* Now unmask the interrupt (often a no-op) */
215 call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq);
216 if (call_status != 0) {
217 printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_int_on "
218 "returned %d\n", irq, call_status);
223 static unsigned int xics_startup(unsigned int virq)
226 xics_unmask_irq(virq);
230 static void xics_mask_real_irq(unsigned int irq)
237 call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq);
238 if (call_status != 0) {
239 printk(KERN_ERR "xics_disable_real_irq: irq=%u: "
240 "ibm_int_off returned %d\n", irq, call_status);
244 /* Have to set XIVE to 0xff to be able to remove a slot */
245 call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq,
246 default_server, 0xff);
247 if (call_status != 0) {
248 printk(KERN_ERR "xics_disable_irq: irq=%u: ibm_set_xive(0xff)"
249 " returned %d\n", irq, call_status);
254 static void xics_mask_irq(unsigned int virq)
258 pr_debug("xics: mask virq %d\n", virq);
260 irq = (unsigned int)irq_map[virq].hwirq;
261 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
263 xics_mask_real_irq(irq);
266 static void xics_mask_unknown_vec(unsigned int vec)
268 printk(KERN_ERR "Interrupt %u (real) is invalid, disabling it.\n", vec);
269 xics_mask_real_irq(vec);
272 static inline unsigned int xics_xirr_vector(unsigned int xirr)
275 * The top byte is the old cppr, to be restored on EOI.
276 * The remaining 24 bits are the vector.
278 return xirr & 0x00ffffff;
281 static unsigned int xics_get_irq_direct(void)
283 unsigned int xirr = direct_xirr_info_get();
284 unsigned int vec = xics_xirr_vector(xirr);
287 if (vec == XICS_IRQ_SPURIOUS)
290 irq = irq_radix_revmap_lookup(xics_host, vec);
291 if (likely(irq != NO_IRQ))
294 /* We don't have a linux mapping, so have rtas mask it. */
295 xics_mask_unknown_vec(vec);
297 /* We might learn about it later, so EOI it */
298 direct_xirr_info_set(xirr);
302 static unsigned int xics_get_irq_lpar(void)
304 unsigned int xirr = lpar_xirr_info_get();
305 unsigned int vec = xics_xirr_vector(xirr);
308 if (vec == XICS_IRQ_SPURIOUS)
311 irq = irq_radix_revmap_lookup(xics_host, vec);
312 if (likely(irq != NO_IRQ))
315 /* We don't have a linux mapping, so have RTAS mask it. */
316 xics_mask_unknown_vec(vec);
318 /* We might learn about it later, so EOI it */
319 lpar_xirr_info_set(xirr);
323 static void xics_eoi_direct(unsigned int virq)
325 unsigned int irq = (unsigned int)irq_map[virq].hwirq;
328 direct_xirr_info_set((0xff << 24) | irq);
331 static void xics_eoi_lpar(unsigned int virq)
333 unsigned int irq = (unsigned int)irq_map[virq].hwirq;
336 lpar_xirr_info_set((0xff << 24) | irq);
339 static void xics_set_affinity(unsigned int virq, cpumask_t cpumask)
346 irq = (unsigned int)irq_map[virq].hwirq;
347 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
350 status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
353 printk(KERN_ERR "xics_set_affinity: irq=%u ibm,get-xive "
354 "returns %d\n", irq, status);
359 * For the moment only implement delivery to all cpus or one cpu.
360 * Get current irq_server for the given irq
362 irq_server = get_irq_server(virq, 1);
363 if (irq_server == -1) {
365 cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask);
366 printk(KERN_WARNING "xics_set_affinity: No online cpus in "
367 "the mask %s for irq %d\n", cpulist, virq);
371 status = rtas_call(ibm_set_xive, 3, 1, NULL,
372 irq, irq_server, xics_status[1]);
375 printk(KERN_ERR "xics_set_affinity: irq=%u ibm,set-xive "
376 "returns %d\n", irq, status);
381 static struct irq_chip xics_pic_direct = {
382 .typename = " XICS ",
383 .startup = xics_startup,
384 .mask = xics_mask_irq,
385 .unmask = xics_unmask_irq,
386 .eoi = xics_eoi_direct,
387 .set_affinity = xics_set_affinity
390 static struct irq_chip xics_pic_lpar = {
391 .typename = " XICS ",
392 .startup = xics_startup,
393 .mask = xics_mask_irq,
394 .unmask = xics_unmask_irq,
395 .eoi = xics_eoi_lpar,
396 .set_affinity = xics_set_affinity
400 /* Interface to arch irq controller subsystem layer */
402 /* Points to the irq_chip we're actually using */
403 static struct irq_chip *xics_irq_chip;
405 static int xics_host_match(struct irq_host *h, struct device_node *node)
407 /* IBM machines have interrupt parents of various funky types for things
408 * like vdevices, events, etc... The trick we use here is to match
409 * everything here except the legacy 8259 which is compatible "chrp,iic"
411 return !of_device_is_compatible(node, "chrp,iic");
414 static int xics_host_map(struct irq_host *h, unsigned int virq,
417 pr_debug("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
419 /* Insert the interrupt mapping into the radix tree for fast lookup */
420 irq_radix_revmap_insert(xics_host, virq, hw);
422 get_irq_desc(virq)->status |= IRQ_LEVEL;
423 set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq);
427 static int xics_host_xlate(struct irq_host *h, struct device_node *ct,
428 u32 *intspec, unsigned int intsize,
429 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
432 /* Current xics implementation translates everything
433 * to level. It is not technically right for MSIs but this
434 * is irrelevant at this point. We might get smarter in the future
436 *out_hwirq = intspec[0];
437 *out_flags = IRQ_TYPE_LEVEL_LOW;
442 static struct irq_host_ops xics_host_ops = {
443 .match = xics_host_match,
444 .map = xics_host_map,
445 .xlate = xics_host_xlate,
448 static void __init xics_init_host(void)
450 if (firmware_has_feature(FW_FEATURE_LPAR))
451 xics_irq_chip = &xics_pic_lpar;
453 xics_irq_chip = &xics_pic_direct;
455 xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, &xics_host_ops,
457 BUG_ON(xics_host == NULL);
458 irq_set_default_host(xics_host);
462 /* Inter-processor interrupt support */
466 * XICS only has a single IPI, so encode the messages per CPU
468 struct xics_ipi_struct {
470 } ____cacheline_aligned;
472 static struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
474 static inline void smp_xics_do_message(int cpu, int msg)
476 set_bit(msg, &xics_ipi_message[cpu].value);
478 if (firmware_has_feature(FW_FEATURE_LPAR))
479 lpar_qirr_info(cpu, IPI_PRIORITY);
481 direct_qirr_info(cpu, IPI_PRIORITY);
484 void smp_xics_message_pass(int target, int msg)
488 if (target < NR_CPUS) {
489 smp_xics_do_message(target, msg);
491 for_each_online_cpu(i) {
492 if (target == MSG_ALL_BUT_SELF
493 && i == smp_processor_id())
495 smp_xics_do_message(i, msg);
500 static irqreturn_t xics_ipi_dispatch(int cpu)
502 WARN_ON(cpu_is_offline(cpu));
504 while (xics_ipi_message[cpu].value) {
505 if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION,
506 &xics_ipi_message[cpu].value)) {
508 smp_message_recv(PPC_MSG_CALL_FUNCTION);
510 if (test_and_clear_bit(PPC_MSG_RESCHEDULE,
511 &xics_ipi_message[cpu].value)) {
513 smp_message_recv(PPC_MSG_RESCHEDULE);
515 if (test_and_clear_bit(PPC_MSG_CALL_FUNC_SINGLE,
516 &xics_ipi_message[cpu].value)) {
518 smp_message_recv(PPC_MSG_CALL_FUNC_SINGLE);
520 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
521 if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK,
522 &xics_ipi_message[cpu].value)) {
524 smp_message_recv(PPC_MSG_DEBUGGER_BREAK);
531 static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id)
533 int cpu = smp_processor_id();
535 direct_qirr_info(cpu, 0xff);
537 return xics_ipi_dispatch(cpu);
540 static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id)
542 int cpu = smp_processor_id();
544 lpar_qirr_info(cpu, 0xff);
546 return xics_ipi_dispatch(cpu);
549 static void xics_request_ipi(void)
554 ipi = irq_create_mapping(xics_host, XICS_IPI);
555 BUG_ON(ipi == NO_IRQ);
558 * IPIs are marked IRQF_DISABLED as they must run with irqs
561 set_irq_handler(ipi, handle_percpu_irq);
562 if (firmware_has_feature(FW_FEATURE_LPAR))
563 rc = request_irq(ipi, xics_ipi_action_lpar, IRQF_DISABLED,
566 rc = request_irq(ipi, xics_ipi_action_direct, IRQF_DISABLED,
571 int __init smp_xics_probe(void)
575 return cpus_weight(cpu_possible_map);
578 #endif /* CONFIG_SMP */
583 static void xics_update_irq_servers(void)
586 struct device_node *np;
588 const u32 *ireg, *isize;
591 /* Find the server numbers for the boot cpu. */
592 np = of_get_cpu_node(boot_cpuid, NULL);
595 ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
601 i = ilen / sizeof(int);
602 hcpuid = get_hard_smp_processor_id(boot_cpuid);
604 /* Global interrupt distribution server is specified in the last
605 * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
606 * entry fom this property for current boot cpu id and use it as
607 * default distribution server
609 for (j = 0; j < i; j += 2) {
610 if (ireg[j] == hcpuid) {
611 default_server = hcpuid;
612 default_distrib_server = ireg[j+1];
614 isize = of_get_property(np,
615 "ibm,interrupt-server#-size", NULL);
617 interrupt_server_size = *isize;
624 static void __init xics_map_one_cpu(int hw_id, unsigned long addr,
630 /* This may look gross but it's good enough for now, we don't quite
631 * have a hard -> linux processor id matching.
633 for_each_possible_cpu(i) {
636 if (hw_id == get_hard_smp_processor_id(i)) {
637 xics_per_cpu[i] = ioremap(addr, size);
644 xics_per_cpu[0] = ioremap(addr, size);
645 #endif /* CONFIG_SMP */
648 static void __init xics_init_one_node(struct device_node *np,
654 /* This code does the theorically broken assumption that the interrupt
655 * server numbers are the same as the hard CPU numbers.
656 * This happens to be the case so far but we are playing with fire...
657 * should be fixed one of these days. -BenH.
659 ireg = of_get_property(np, "ibm,interrupt-server-ranges", NULL);
661 /* Do that ever happen ? we'll know soon enough... but even good'old
662 * f80 does have that property ..
664 WARN_ON(ireg == NULL);
667 * set node starting index for this node
671 ireg = of_get_property(np, "reg", &ilen);
673 panic("xics_init_IRQ: can't find interrupt reg property");
675 while (ilen >= (4 * sizeof(u32))) {
676 unsigned long addr, size;
678 /* XXX Use proper OF parsing code here !!! */
679 addr = (unsigned long)*ireg++ << 32;
683 size = (unsigned long)*ireg++ << 32;
687 xics_map_one_cpu(*indx, addr, size);
692 void __init xics_init_IRQ(void)
694 struct device_node *np;
698 ppc64_boot_msg(0x20, "XICS Init");
700 ibm_get_xive = rtas_token("ibm,get-xive");
701 ibm_set_xive = rtas_token("ibm,set-xive");
702 ibm_int_on = rtas_token("ibm,int-on");
703 ibm_int_off = rtas_token("ibm,int-off");
705 for_each_node_by_type(np, "PowerPC-External-Interrupt-Presentation") {
707 if (firmware_has_feature(FW_FEATURE_LPAR))
709 xics_init_one_node(np, &indx);
714 xics_update_irq_servers();
717 if (firmware_has_feature(FW_FEATURE_LPAR))
718 ppc_md.get_irq = xics_get_irq_lpar;
720 ppc_md.get_irq = xics_get_irq_direct;
724 ppc64_boot_msg(0x21, "XICS Done");
727 /* Cpu startup, shutdown, and hotplug */
729 static void xics_set_cpu_priority(unsigned char cppr)
731 if (firmware_has_feature(FW_FEATURE_LPAR))
732 lpar_cppr_info(cppr);
734 direct_cppr_info(cppr);
739 void xics_setup_cpu(void)
741 xics_set_cpu_priority(0xff);
744 * Put the calling processor into the GIQ. This is really only
745 * necessary from a secondary thread as the OF start-cpu interface
746 * performs this function for us on primary threads.
748 * XXX: undo of teardown on kexec needs this too, as may hotplug
750 rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
751 (1UL << interrupt_server_size) - 1 - default_distrib_server, 1);
754 void xics_teardown_cpu(void)
756 int cpu = smp_processor_id();
758 xics_set_cpu_priority(0);
763 if (firmware_has_feature(FW_FEATURE_LPAR))
764 lpar_qirr_info(cpu, 0xff);
766 direct_qirr_info(cpu, 0xff);
769 void xics_kexec_teardown_cpu(int secondary)
772 struct irq_desc *desc;
777 * we need to EOI the IPI
779 * probably need to check all the other interrupts too
780 * should we be flagging idle loop instead?
781 * or creating some task to be scheduled?
784 ipi = irq_find_mapping(xics_host, XICS_IPI);
785 if (ipi == XICS_IRQ_SPURIOUS)
787 desc = get_irq_desc(ipi);
788 if (desc->chip && desc->chip->eoi)
789 desc->chip->eoi(ipi);
792 * Some machines need to have at least one cpu in the GIQ,
793 * so leave the master cpu in the group.
796 rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
797 (1UL << interrupt_server_size) - 1 -
798 default_distrib_server, 0);
801 #ifdef CONFIG_HOTPLUG_CPU
803 /* Interrupts are disabled. */
804 void xics_migrate_irqs_away(void)
807 int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
808 unsigned int irq, virq;
810 /* If we used to be the default server, move to the new "boot_cpuid" */
811 if (hw_cpu == default_server)
812 xics_update_irq_servers();
814 /* Reject any interrupt that was queued to us... */
815 xics_set_cpu_priority(0);
817 /* remove ourselves from the global interrupt queue */
818 status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
819 (1UL << interrupt_server_size) - 1 - default_distrib_server, 0);
822 /* Allow IPIs again... */
823 xics_set_cpu_priority(DEFAULT_PRIORITY);
826 struct irq_desc *desc;
830 /* We cant set affinity on ISA interrupts */
831 if (virq < NUM_ISA_INTERRUPTS)
833 if (irq_map[virq].host != xics_host)
835 irq = (unsigned int)irq_map[virq].hwirq;
836 /* We need to get IPIs still. */
837 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
839 desc = get_irq_desc(virq);
841 /* We only need to migrate enabled IRQS */
842 if (desc == NULL || desc->chip == NULL
843 || desc->action == NULL
844 || desc->chip->set_affinity == NULL)
847 spin_lock_irqsave(&desc->lock, flags);
849 status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
851 printk(KERN_ERR "migrate_irqs_away: irq=%u "
852 "ibm,get-xive returns %d\n",
858 * We only support delivery to all cpus or to one cpu.
859 * The irq has to be migrated only in the single cpu
862 if (xics_status[0] != hw_cpu)
865 printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n",
868 /* Reset affinity to all cpus */
869 irq_desc[virq].affinity = CPU_MASK_ALL;
870 desc->chip->set_affinity(virq, CPU_MASK_ALL);
872 spin_unlock_irqrestore(&desc->lock, flags);