2 * arch/powerpc/platforms/pseries/xics.c
4 * Copyright 2000 IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/types.h>
13 #include <linux/threads.h>
14 #include <linux/kernel.h>
15 #include <linux/irq.h>
16 #include <linux/smp.h>
17 #include <linux/interrupt.h>
18 #include <linux/init.h>
19 #include <linux/radix-tree.h>
20 #include <linux/cpu.h>
23 #include <asm/firmware.h>
25 #include <asm/pgtable.h>
28 #include <asm/hvcall.h>
29 #include <asm/machdep.h>
32 #include "plpar_wrappers.h"
34 static struct irq_host *xics_host;
37 #define XICS_IRQ_SPURIOUS 0
39 /* Want a priority other than 0. Various HW issues require this. */
40 #define DEFAULT_PRIORITY 5
43 * Mark IPIs as higher priority so we can take them inside interrupts that
44 * arent marked IRQF_DISABLED
46 #define IPI_PRIORITY 4
48 static unsigned int default_server = 0xFF;
49 static unsigned int default_distrib_server = 0;
50 static unsigned int interrupt_server_size = 8;
52 /* RTAS service tokens */
53 static int ibm_get_xive;
54 static int ibm_set_xive;
55 static int ibm_int_on;
56 static int ibm_int_off;
59 /* Direct hardware low level accessors */
61 /* The part of the interrupt presentation layer that we care about */
78 static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS];
80 static inline unsigned int direct_xirr_info_get(void)
82 int cpu = smp_processor_id();
84 return in_be32(&xics_per_cpu[cpu]->xirr.word);
87 static inline void direct_xirr_info_set(unsigned int value)
89 int cpu = smp_processor_id();
91 out_be32(&xics_per_cpu[cpu]->xirr.word, value);
94 static inline void direct_cppr_info(u8 value)
96 int cpu = smp_processor_id();
98 out_8(&xics_per_cpu[cpu]->xirr.bytes[0], value);
101 static inline void direct_qirr_info(int n_cpu, u8 value)
103 out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value);
107 /* LPAR low level accessors */
109 static inline unsigned int lpar_xirr_info_get(void)
111 unsigned long lpar_rc;
112 unsigned long return_value;
114 lpar_rc = plpar_xirr(&return_value);
115 if (lpar_rc != H_SUCCESS)
116 panic(" bad return code xirr - rc = %lx \n", lpar_rc);
117 return (unsigned int)return_value;
120 static inline void lpar_xirr_info_set(unsigned int value)
122 unsigned long lpar_rc;
124 lpar_rc = plpar_eoi(value);
125 if (lpar_rc != H_SUCCESS)
126 panic("bad return code EOI - rc = %ld, value=%x\n", lpar_rc,
130 static inline void lpar_cppr_info(u8 value)
132 unsigned long lpar_rc;
134 lpar_rc = plpar_cppr(value);
135 if (lpar_rc != H_SUCCESS)
136 panic("bad return code cppr - rc = %lx\n", lpar_rc);
139 static inline void lpar_qirr_info(int n_cpu , u8 value)
141 unsigned long lpar_rc;
143 lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value);
144 if (lpar_rc != H_SUCCESS)
145 panic("bad return code qirr - rc = %lx\n", lpar_rc);
149 /* Interface to generic irq subsystem */
152 static int get_irq_server(unsigned int virq, unsigned int strict_check)
155 /* For the moment only implement delivery to all cpus or one cpu */
156 cpumask_t cpumask = irq_desc[virq].affinity;
157 cpumask_t tmp = CPU_MASK_NONE;
159 if (!distribute_irqs)
160 return default_server;
162 if (!cpus_equal(cpumask, CPU_MASK_ALL)) {
163 cpus_and(tmp, cpu_online_map, cpumask);
165 server = first_cpu(tmp);
167 if (server < NR_CPUS)
168 return get_hard_smp_processor_id(server);
174 if (cpus_equal(cpu_online_map, cpu_present_map))
175 return default_distrib_server;
177 return default_server;
180 static int get_irq_server(unsigned int virq, unsigned int strict_check)
182 return default_server;
186 static void xics_unmask_irq(unsigned int virq)
192 pr_debug("xics: unmask virq %d\n", virq);
194 irq = (unsigned int)irq_map[virq].hwirq;
195 pr_debug(" -> map to hwirq 0x%x\n", irq);
196 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
199 server = get_irq_server(virq, 0);
201 call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server,
203 if (call_status != 0) {
204 printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_set_xive "
205 "returned %d\n", irq, call_status);
206 printk("set_xive %x, server %x\n", ibm_set_xive, server);
210 /* Now unmask the interrupt (often a no-op) */
211 call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq);
212 if (call_status != 0) {
213 printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_int_on "
214 "returned %d\n", irq, call_status);
219 static unsigned int xics_startup(unsigned int virq)
222 xics_unmask_irq(virq);
226 static void xics_mask_real_irq(unsigned int irq)
233 call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq);
234 if (call_status != 0) {
235 printk(KERN_ERR "xics_disable_real_irq: irq=%u: "
236 "ibm_int_off returned %d\n", irq, call_status);
240 /* Have to set XIVE to 0xff to be able to remove a slot */
241 call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq,
242 default_server, 0xff);
243 if (call_status != 0) {
244 printk(KERN_ERR "xics_disable_irq: irq=%u: ibm_set_xive(0xff)"
245 " returned %d\n", irq, call_status);
250 static void xics_mask_irq(unsigned int virq)
254 pr_debug("xics: mask virq %d\n", virq);
256 irq = (unsigned int)irq_map[virq].hwirq;
257 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
259 xics_mask_real_irq(irq);
262 static void xics_mask_unknown_vec(unsigned int vec)
264 printk(KERN_ERR "Interrupt %u (real) is invalid, disabling it.\n", vec);
265 xics_mask_real_irq(vec);
268 static inline unsigned int xics_xirr_vector(unsigned int xirr)
271 * The top byte is the old cppr, to be restored on EOI.
272 * The remaining 24 bits are the vector.
274 return xirr & 0x00ffffff;
277 static unsigned int xics_get_irq_direct(void)
279 unsigned int xirr = direct_xirr_info_get();
280 unsigned int vec = xics_xirr_vector(xirr);
283 if (vec == XICS_IRQ_SPURIOUS)
286 irq = irq_radix_revmap_lookup(xics_host, vec);
287 if (likely(irq != NO_IRQ))
290 /* We don't have a linux mapping, so have rtas mask it. */
291 xics_mask_unknown_vec(vec);
293 /* We might learn about it later, so EOI it */
294 direct_xirr_info_set(xirr);
298 static unsigned int xics_get_irq_lpar(void)
300 unsigned int xirr = lpar_xirr_info_get();
301 unsigned int vec = xics_xirr_vector(xirr);
304 if (vec == XICS_IRQ_SPURIOUS)
307 irq = irq_radix_revmap_lookup(xics_host, vec);
308 if (likely(irq != NO_IRQ))
311 /* We don't have a linux mapping, so have RTAS mask it. */
312 xics_mask_unknown_vec(vec);
314 /* We might learn about it later, so EOI it */
315 lpar_xirr_info_set(xirr);
319 static void xics_eoi_direct(unsigned int virq)
321 unsigned int irq = (unsigned int)irq_map[virq].hwirq;
324 direct_xirr_info_set((0xff << 24) | irq);
327 static void xics_eoi_lpar(unsigned int virq)
329 unsigned int irq = (unsigned int)irq_map[virq].hwirq;
332 lpar_xirr_info_set((0xff << 24) | irq);
335 static void xics_set_affinity(unsigned int virq, cpumask_t cpumask)
342 irq = (unsigned int)irq_map[virq].hwirq;
343 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
346 status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
349 printk(KERN_ERR "xics_set_affinity: irq=%u ibm,get-xive "
350 "returns %d\n", irq, status);
355 * For the moment only implement delivery to all cpus or one cpu.
356 * Get current irq_server for the given irq
358 irq_server = get_irq_server(virq, 1);
359 if (irq_server == -1) {
361 cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask);
362 printk(KERN_WARNING "xics_set_affinity: No online cpus in "
363 "the mask %s for irq %d\n", cpulist, virq);
367 status = rtas_call(ibm_set_xive, 3, 1, NULL,
368 irq, irq_server, xics_status[1]);
371 printk(KERN_ERR "xics_set_affinity: irq=%u ibm,set-xive "
372 "returns %d\n", irq, status);
377 static struct irq_chip xics_pic_direct = {
378 .typename = " XICS ",
379 .startup = xics_startup,
380 .mask = xics_mask_irq,
381 .unmask = xics_unmask_irq,
382 .eoi = xics_eoi_direct,
383 .set_affinity = xics_set_affinity
386 static struct irq_chip xics_pic_lpar = {
387 .typename = " XICS ",
388 .startup = xics_startup,
389 .mask = xics_mask_irq,
390 .unmask = xics_unmask_irq,
391 .eoi = xics_eoi_lpar,
392 .set_affinity = xics_set_affinity
396 /* Interface to arch irq controller subsystem layer */
398 /* Points to the irq_chip we're actually using */
399 static struct irq_chip *xics_irq_chip;
401 static int xics_host_match(struct irq_host *h, struct device_node *node)
403 /* IBM machines have interrupt parents of various funky types for things
404 * like vdevices, events, etc... The trick we use here is to match
405 * everything here except the legacy 8259 which is compatible "chrp,iic"
407 return !of_device_is_compatible(node, "chrp,iic");
410 static int xics_host_map(struct irq_host *h, unsigned int virq,
413 pr_debug("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
415 /* Insert the interrupt mapping into the radix tree for fast lookup */
416 irq_radix_revmap_insert(xics_host, virq, hw);
418 get_irq_desc(virq)->status |= IRQ_LEVEL;
419 set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq);
423 static int xics_host_xlate(struct irq_host *h, struct device_node *ct,
424 u32 *intspec, unsigned int intsize,
425 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
428 /* Current xics implementation translates everything
429 * to level. It is not technically right for MSIs but this
430 * is irrelevant at this point. We might get smarter in the future
432 *out_hwirq = intspec[0];
433 *out_flags = IRQ_TYPE_LEVEL_LOW;
438 static struct irq_host_ops xics_host_ops = {
439 .match = xics_host_match,
440 .map = xics_host_map,
441 .xlate = xics_host_xlate,
444 static void __init xics_init_host(void)
446 if (firmware_has_feature(FW_FEATURE_LPAR))
447 xics_irq_chip = &xics_pic_lpar;
449 xics_irq_chip = &xics_pic_direct;
451 xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, &xics_host_ops,
453 BUG_ON(xics_host == NULL);
454 irq_set_default_host(xics_host);
458 /* Inter-processor interrupt support */
462 * XICS only has a single IPI, so encode the messages per CPU
464 struct xics_ipi_struct {
466 } ____cacheline_aligned;
468 static struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
470 static inline void smp_xics_do_message(int cpu, int msg)
472 set_bit(msg, &xics_ipi_message[cpu].value);
474 if (firmware_has_feature(FW_FEATURE_LPAR))
475 lpar_qirr_info(cpu, IPI_PRIORITY);
477 direct_qirr_info(cpu, IPI_PRIORITY);
480 void smp_xics_message_pass(int target, int msg)
484 if (target < NR_CPUS) {
485 smp_xics_do_message(target, msg);
487 for_each_online_cpu(i) {
488 if (target == MSG_ALL_BUT_SELF
489 && i == smp_processor_id())
491 smp_xics_do_message(i, msg);
496 static irqreturn_t xics_ipi_dispatch(int cpu)
498 WARN_ON(cpu_is_offline(cpu));
500 while (xics_ipi_message[cpu].value) {
501 if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION,
502 &xics_ipi_message[cpu].value)) {
504 smp_message_recv(PPC_MSG_CALL_FUNCTION);
506 if (test_and_clear_bit(PPC_MSG_RESCHEDULE,
507 &xics_ipi_message[cpu].value)) {
509 smp_message_recv(PPC_MSG_RESCHEDULE);
511 if (test_and_clear_bit(PPC_MSG_CALL_FUNC_SINGLE,
512 &xics_ipi_message[cpu].value)) {
514 smp_message_recv(PPC_MSG_CALL_FUNC_SINGLE);
516 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
517 if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK,
518 &xics_ipi_message[cpu].value)) {
520 smp_message_recv(PPC_MSG_DEBUGGER_BREAK);
527 static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id)
529 int cpu = smp_processor_id();
531 direct_qirr_info(cpu, 0xff);
533 return xics_ipi_dispatch(cpu);
536 static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id)
538 int cpu = smp_processor_id();
540 lpar_qirr_info(cpu, 0xff);
542 return xics_ipi_dispatch(cpu);
545 static void xics_request_ipi(void)
550 ipi = irq_create_mapping(xics_host, XICS_IPI);
551 BUG_ON(ipi == NO_IRQ);
554 * IPIs are marked IRQF_DISABLED as they must run with irqs
557 set_irq_handler(ipi, handle_percpu_irq);
558 if (firmware_has_feature(FW_FEATURE_LPAR))
559 rc = request_irq(ipi, xics_ipi_action_lpar, IRQF_DISABLED,
562 rc = request_irq(ipi, xics_ipi_action_direct, IRQF_DISABLED,
567 int __init smp_xics_probe(void)
571 return cpus_weight(cpu_possible_map);
574 #endif /* CONFIG_SMP */
579 static void xics_update_irq_servers(void)
582 struct device_node *np;
584 const u32 *ireg, *isize;
587 /* Find the server numbers for the boot cpu. */
588 np = of_get_cpu_node(boot_cpuid, NULL);
591 ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
597 i = ilen / sizeof(int);
598 hcpuid = get_hard_smp_processor_id(boot_cpuid);
600 /* Global interrupt distribution server is specified in the last
601 * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
602 * entry fom this property for current boot cpu id and use it as
603 * default distribution server
605 for (j = 0; j < i; j += 2) {
606 if (ireg[j] == hcpuid) {
607 default_server = hcpuid;
608 default_distrib_server = ireg[j+1];
612 /* get the bit size of server numbers */
613 isize = of_get_property(np, "ibm,interrupt-server#-size", NULL);
615 interrupt_server_size = *isize;
620 static void __init xics_map_one_cpu(int hw_id, unsigned long addr,
625 /* This may look gross but it's good enough for now, we don't quite
626 * have a hard -> linux processor id matching.
628 for_each_possible_cpu(i) {
631 if (hw_id == get_hard_smp_processor_id(i)) {
632 xics_per_cpu[i] = ioremap(addr, size);
638 static void __init xics_init_one_node(struct device_node *np,
644 /* This code does the theorically broken assumption that the interrupt
645 * server numbers are the same as the hard CPU numbers.
646 * This happens to be the case so far but we are playing with fire...
647 * should be fixed one of these days. -BenH.
649 ireg = of_get_property(np, "ibm,interrupt-server-ranges", NULL);
651 /* Do that ever happen ? we'll know soon enough... but even good'old
652 * f80 does have that property ..
654 WARN_ON(ireg == NULL);
657 * set node starting index for this node
661 ireg = of_get_property(np, "reg", &ilen);
663 panic("xics_init_IRQ: can't find interrupt reg property");
665 while (ilen >= (4 * sizeof(u32))) {
666 unsigned long addr, size;
668 /* XXX Use proper OF parsing code here !!! */
669 addr = (unsigned long)*ireg++ << 32;
673 size = (unsigned long)*ireg++ << 32;
677 xics_map_one_cpu(*indx, addr, size);
682 void __init xics_init_IRQ(void)
684 struct device_node *np;
688 ppc64_boot_msg(0x20, "XICS Init");
690 ibm_get_xive = rtas_token("ibm,get-xive");
691 ibm_set_xive = rtas_token("ibm,set-xive");
692 ibm_int_on = rtas_token("ibm,int-on");
693 ibm_int_off = rtas_token("ibm,int-off");
695 for_each_node_by_type(np, "PowerPC-External-Interrupt-Presentation") {
697 if (firmware_has_feature(FW_FEATURE_LPAR)) {
701 xics_init_one_node(np, &indx);
706 xics_update_irq_servers();
709 if (firmware_has_feature(FW_FEATURE_LPAR))
710 ppc_md.get_irq = xics_get_irq_lpar;
712 ppc_md.get_irq = xics_get_irq_direct;
716 ppc64_boot_msg(0x21, "XICS Done");
719 /* Cpu startup, shutdown, and hotplug */
721 static void xics_set_cpu_priority(unsigned char cppr)
723 if (firmware_has_feature(FW_FEATURE_LPAR))
724 lpar_cppr_info(cppr);
726 direct_cppr_info(cppr);
730 /* Have the calling processor join or leave the specified global queue */
731 static void xics_set_cpu_giq(unsigned int gserver, unsigned int join)
733 int status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
734 (1UL << interrupt_server_size) - 1 - gserver, join);
738 void xics_setup_cpu(void)
740 xics_set_cpu_priority(0xff);
742 xics_set_cpu_giq(default_distrib_server, 1);
745 void xics_teardown_cpu(void)
747 int cpu = smp_processor_id();
749 xics_set_cpu_priority(0);
751 /* Clear any pending IPI request */
752 if (firmware_has_feature(FW_FEATURE_LPAR))
753 lpar_qirr_info(cpu, 0xff);
755 direct_qirr_info(cpu, 0xff);
758 void xics_kexec_teardown_cpu(int secondary)
763 * we take the ipi irq but and never return so we
764 * need to EOI the IPI, but want to leave our priority 0
766 * should we check all the other interrupts too?
767 * should we be flagging idle loop instead?
768 * or creating some task to be scheduled?
771 if (firmware_has_feature(FW_FEATURE_LPAR))
772 lpar_xirr_info_set((0x00 << 24) | XICS_IPI);
774 direct_xirr_info_set((0x00 << 24) | XICS_IPI);
777 * Some machines need to have at least one cpu in the GIQ,
778 * so leave the master cpu in the group.
781 xics_set_cpu_giq(default_distrib_server, 0);
784 #ifdef CONFIG_HOTPLUG_CPU
786 /* Interrupts are disabled. */
787 void xics_migrate_irqs_away(void)
789 int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
790 unsigned int irq, virq;
792 /* If we used to be the default server, move to the new "boot_cpuid" */
793 if (hw_cpu == default_server)
794 xics_update_irq_servers();
796 /* Reject any interrupt that was queued to us... */
797 xics_set_cpu_priority(0);
799 /* Remove ourselves from the global interrupt queue */
800 xics_set_cpu_giq(default_distrib_server, 0);
802 /* Allow IPIs again... */
803 xics_set_cpu_priority(DEFAULT_PRIORITY);
806 struct irq_desc *desc;
811 /* We cant set affinity on ISA interrupts */
812 if (virq < NUM_ISA_INTERRUPTS)
814 if (irq_map[virq].host != xics_host)
816 irq = (unsigned int)irq_map[virq].hwirq;
817 /* We need to get IPIs still. */
818 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
820 desc = get_irq_desc(virq);
822 /* We only need to migrate enabled IRQS */
823 if (desc == NULL || desc->chip == NULL
824 || desc->action == NULL
825 || desc->chip->set_affinity == NULL)
828 spin_lock_irqsave(&desc->lock, flags);
830 status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
832 printk(KERN_ERR "migrate_irqs_away: irq=%u "
833 "ibm,get-xive returns %d\n",
839 * We only support delivery to all cpus or to one cpu.
840 * The irq has to be migrated only in the single cpu
843 if (xics_status[0] != hw_cpu)
846 printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n",
849 /* Reset affinity to all cpus */
850 irq_desc[virq].affinity = CPU_MASK_ALL;
851 desc->chip->set_affinity(virq, CPU_MASK_ALL);
853 spin_unlock_irqrestore(&desc->lock, flags);