2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
6 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
7 * Copyright (C) 2006 Olof Johansson <olof@lixom.net>
9 * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 #include <linux/config.h>
28 #include <linux/init.h>
29 #include <linux/types.h>
30 #include <linux/slab.h>
32 #include <linux/spinlock.h>
33 #include <linux/string.h>
34 #include <linux/pci.h>
35 #include <linux/dma-mapping.h>
39 #include <asm/iommu.h>
40 #include <asm/pci-bridge.h>
41 #include <asm/machdep.h>
42 #include <asm/abs_addr.h>
43 #include <asm/pSeries_reconfig.h>
44 #include <asm/firmware.h>
46 #include <asm/ppc-pci.h>
49 #include "plpar_wrappers.h"
53 static void tce_build_pSeries(struct iommu_table *tbl, long index,
54 long npages, unsigned long uaddr,
55 enum dma_data_direction direction)
61 index <<= TCE_PAGE_FACTOR;
62 npages <<= TCE_PAGE_FACTOR;
64 proto_tce = TCE_PCI_READ; // Read allowed
66 if (direction != DMA_TO_DEVICE)
67 proto_tce |= TCE_PCI_WRITE;
69 tcep = ((u64 *)tbl->it_base) + index;
72 /* can't move this out since we might cross LMB boundary */
73 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
74 *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
76 uaddr += TCE_PAGE_SIZE;
82 static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
86 npages <<= TCE_PAGE_FACTOR;
87 index <<= TCE_PAGE_FACTOR;
89 tcep = ((u64 *)tbl->it_base) + index;
96 static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
97 long npages, unsigned long uaddr,
98 enum dma_data_direction direction)
104 tcenum <<= TCE_PAGE_FACTOR;
105 npages <<= TCE_PAGE_FACTOR;
107 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
108 proto_tce = TCE_PCI_READ;
109 if (direction != DMA_TO_DEVICE)
110 proto_tce |= TCE_PCI_WRITE;
113 tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
114 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce);
116 if (rc && printk_ratelimit()) {
117 printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
118 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
119 printk("\ttcenum = 0x%lx\n", (u64)tcenum);
120 printk("\ttce val = 0x%lx\n", tce );
121 show_stack(current, (unsigned long *)__get_SP());
129 static DEFINE_PER_CPU(u64 *, tce_page) = NULL;
131 static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
132 long npages, unsigned long uaddr,
133 enum dma_data_direction direction)
141 if (TCE_PAGE_FACTOR == 0 && npages == 1)
142 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
145 tcep = __get_cpu_var(tce_page);
147 /* This is safe to do since interrupts are off when we're called
148 * from iommu_alloc{,_sg}()
151 tcep = (u64 *)__get_free_page(GFP_ATOMIC);
152 /* If allocation fails, fall back to the loop implementation */
154 return tce_build_pSeriesLP(tbl, tcenum, npages,
156 __get_cpu_var(tce_page) = tcep;
159 tcenum <<= TCE_PAGE_FACTOR;
160 npages <<= TCE_PAGE_FACTOR;
162 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
163 proto_tce = TCE_PCI_READ;
164 if (direction != DMA_TO_DEVICE)
165 proto_tce |= TCE_PCI_WRITE;
167 /* We can map max one pageful of TCEs at a time */
170 * Set up the page with TCE data, looping through and setting
173 limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE);
175 for (l = 0; l < limit; l++) {
176 tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
180 rc = plpar_tce_put_indirect((u64)tbl->it_index,
182 (u64)virt_to_abs(tcep),
187 } while (npages > 0 && !rc);
189 if (rc && printk_ratelimit()) {
190 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
191 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
192 printk("\tnpages = 0x%lx\n", (u64)npages);
193 printk("\ttce[0] val = 0x%lx\n", tcep[0]);
194 show_stack(current, (unsigned long *)__get_SP());
198 static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
202 tcenum <<= TCE_PAGE_FACTOR;
203 npages <<= TCE_PAGE_FACTOR;
206 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0);
208 if (rc && printk_ratelimit()) {
209 printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
210 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
211 printk("\ttcenum = 0x%lx\n", (u64)tcenum);
212 show_stack(current, (unsigned long *)__get_SP());
220 static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
224 tcenum <<= TCE_PAGE_FACTOR;
225 npages <<= TCE_PAGE_FACTOR;
227 rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages);
229 if (rc && printk_ratelimit()) {
230 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
231 printk("\trc = %ld\n", rc);
232 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
233 printk("\tnpages = 0x%lx\n", (u64)npages);
234 show_stack(current, (unsigned long *)__get_SP());
238 static void iommu_table_setparms(struct pci_controller *phb,
239 struct device_node *dn,
240 struct iommu_table *tbl)
242 struct device_node *node;
243 unsigned long *basep;
246 node = (struct device_node *)phb->arch_data;
248 basep = (unsigned long *)get_property(node, "linux,tce-base", NULL);
249 sizep = (unsigned int *)get_property(node, "linux,tce-size", NULL);
250 if (basep == NULL || sizep == NULL) {
251 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
252 "missing tce entries !\n", dn->full_name);
256 tbl->it_base = (unsigned long)__va(*basep);
257 memset((void *)tbl->it_base, 0, *sizep);
259 tbl->it_busno = phb->bus->number;
261 /* Units of tce entries */
262 tbl->it_offset = phb->dma_window_base_cur >> PAGE_SHIFT;
264 /* Test if we are going over 2GB of DMA space */
265 if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
266 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
267 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
270 phb->dma_window_base_cur += phb->dma_window_size;
272 /* Set the tce table size - measured in entries */
273 tbl->it_size = phb->dma_window_size >> PAGE_SHIFT;
276 tbl->it_blocksize = 16;
277 tbl->it_type = TCE_PCI;
281 * iommu_table_setparms_lpar
283 * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
285 static void iommu_table_setparms_lpar(struct pci_controller *phb,
286 struct device_node *dn,
287 struct iommu_table *tbl,
288 unsigned char *dma_window)
290 unsigned long offset, size;
292 tbl->it_busno = PCI_DN(dn)->bussubno;
293 of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
296 tbl->it_blocksize = 16;
297 tbl->it_type = TCE_PCI;
298 tbl->it_offset = offset >> PAGE_SHIFT;
299 tbl->it_size = size >> PAGE_SHIFT;
302 static void iommu_bus_setup_pSeries(struct pci_bus *bus)
304 struct device_node *dn;
305 struct iommu_table *tbl;
306 struct device_node *isa_dn, *isa_dn_orig;
307 struct device_node *tmp;
311 DBG("iommu_bus_setup_pSeries, bus %p, bus->self %p\n", bus, bus->self);
313 dn = pci_bus_to_OF_node(bus);
317 /* This is not a root bus, any setup will be done for the
318 * device-side of the bridge in iommu_dev_setup_pSeries().
323 /* Check if the ISA bus on the system is under
326 isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa");
328 while (isa_dn && isa_dn != dn)
329 isa_dn = isa_dn->parent;
332 of_node_put(isa_dn_orig);
334 /* Count number of direct PCI children of the PHB.
335 * All PCI device nodes have class-code property, so it's
336 * an easy way to find them.
338 for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling)
339 if (get_property(tmp, "class-code", NULL))
342 DBG("Children: %d\n", children);
344 /* Calculate amount of DMA window per slot. Each window must be
345 * a power of two (due to pci_alloc_consistent requirements).
347 * Keep 256MB aside for PHBs with ISA.
351 /* No ISA/IDE - just set window size and return */
352 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */
354 while (pci->phb->dma_window_size * children > 0x80000000ul)
355 pci->phb->dma_window_size >>= 1;
356 DBG("No ISA/IDE, window size is 0x%lx\n",
357 pci->phb->dma_window_size);
358 pci->phb->dma_window_base_cur = 0;
363 /* If we have ISA, then we probably have an IDE
364 * controller too. Allocate a 128MB table but
365 * skip the first 128MB to avoid stepping on ISA
368 pci->phb->dma_window_size = 0x8000000ul;
369 pci->phb->dma_window_base_cur = 0x8000000ul;
371 tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL);
373 iommu_table_setparms(pci->phb, dn, tbl);
374 pci->iommu_table = iommu_init_table(tbl);
376 /* Divide the rest (1.75GB) among the children */
377 pci->phb->dma_window_size = 0x80000000ul;
378 while (pci->phb->dma_window_size * children > 0x70000000ul)
379 pci->phb->dma_window_size >>= 1;
381 DBG("ISA/IDE, window size is 0x%lx\n", pci->phb->dma_window_size);
386 static void iommu_bus_setup_pSeriesLP(struct pci_bus *bus)
388 struct iommu_table *tbl;
389 struct device_node *dn, *pdn;
391 unsigned char *dma_window = NULL;
393 DBG("iommu_bus_setup_pSeriesLP, bus %p, bus->self %p\n", bus, bus->self);
395 dn = pci_bus_to_OF_node(bus);
397 /* Find nearest ibm,dma-window, walking up the device tree */
398 for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
399 dma_window = get_property(pdn, "ibm,dma-window", NULL);
400 if (dma_window != NULL)
404 if (dma_window == NULL) {
405 DBG("iommu_bus_setup_pSeriesLP: bus %s seems to have no ibm,dma-window property\n", dn->full_name);
410 if (!ppci->iommu_table) {
411 /* Bussubno hasn't been copied yet.
412 * Do it now because iommu_table_setparms_lpar needs it.
415 ppci->bussubno = bus->number;
417 tbl = (struct iommu_table *)kmalloc(sizeof(struct iommu_table),
420 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
422 ppci->iommu_table = iommu_init_table(tbl);
426 PCI_DN(dn)->iommu_table = ppci->iommu_table;
430 static void iommu_dev_setup_pSeries(struct pci_dev *dev)
432 struct device_node *dn, *mydn;
433 struct iommu_table *tbl;
435 DBG("iommu_dev_setup_pSeries, dev %p (%s)\n", dev, pci_name(dev));
437 mydn = dn = pci_device_to_OF_node(dev);
439 /* If we're the direct child of a root bus, then we need to allocate
440 * an iommu table ourselves. The bus setup code should have setup
441 * the window sizes already.
443 if (!dev->bus->self) {
444 DBG(" --> first child, no bridge. Allocating iommu table.\n");
445 tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL);
446 iommu_table_setparms(PCI_DN(dn)->phb, dn, tbl);
447 PCI_DN(mydn)->iommu_table = iommu_init_table(tbl);
452 /* If this device is further down the bus tree, search upwards until
453 * an already allocated iommu table is found and use that.
456 while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL)
459 if (dn && PCI_DN(dn)) {
460 PCI_DN(mydn)->iommu_table = PCI_DN(dn)->iommu_table;
462 DBG("iommu_dev_setup_pSeries, dev %p (%s) has no iommu table\n", dev, pci_name(dev));
466 static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node)
469 struct device_node *np = node;
470 struct pci_dn *pci = PCI_DN(np);
473 case PSERIES_RECONFIG_REMOVE:
474 if (pci && pci->iommu_table &&
475 get_property(np, "ibm,dma-window", NULL))
476 iommu_free_table(np);
485 static struct notifier_block iommu_reconfig_nb = {
486 .notifier_call = iommu_reconfig_notifier,
489 static void iommu_dev_setup_pSeriesLP(struct pci_dev *dev)
491 struct device_node *pdn, *dn;
492 struct iommu_table *tbl;
493 unsigned char *dma_window = NULL;
496 DBG("iommu_dev_setup_pSeriesLP, dev %p (%s)\n", dev, pci_name(dev));
498 /* dev setup for LPAR is a little tricky, since the device tree might
499 * contain the dma-window properties per-device and not neccesarily
500 * for the bus. So we need to search upwards in the tree until we
501 * either hit a dma-window property, OR find a parent with a table
504 dn = pci_device_to_OF_node(dev);
506 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table;
508 dma_window = get_property(pdn, "ibm,dma-window", NULL);
513 /* Check for parent == NULL so we don't try to setup the empty EADS
514 * slots on POWER4 machines.
516 if (dma_window == NULL || pdn->parent == NULL) {
517 DBG("No dma window for device, linking to parent\n");
518 PCI_DN(dn)->iommu_table = PCI_DN(pdn)->iommu_table;
521 DBG("Found DMA window, allocating table\n");
525 if (!pci->iommu_table) {
526 /* iommu_table_setparms_lpar needs bussubno. */
527 pci->bussubno = pci->phb->bus->number;
529 tbl = (struct iommu_table *)kmalloc(sizeof(struct iommu_table),
532 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
534 pci->iommu_table = iommu_init_table(tbl);
538 PCI_DN(dn)->iommu_table = pci->iommu_table;
541 static void iommu_bus_setup_null(struct pci_bus *b) { }
542 static void iommu_dev_setup_null(struct pci_dev *d) { }
544 /* These are called very early. */
545 void iommu_init_early_pSeries(void)
547 if (of_chosen && get_property(of_chosen, "linux,iommu-off", NULL)) {
548 /* Direct I/O, IOMMU off */
549 ppc_md.iommu_dev_setup = iommu_dev_setup_null;
550 ppc_md.iommu_bus_setup = iommu_bus_setup_null;
551 pci_direct_iommu_init();
556 if (firmware_has_feature(FW_FEATURE_LPAR)) {
557 if (firmware_has_feature(FW_FEATURE_MULTITCE)) {
558 ppc_md.tce_build = tce_buildmulti_pSeriesLP;
559 ppc_md.tce_free = tce_freemulti_pSeriesLP;
561 ppc_md.tce_build = tce_build_pSeriesLP;
562 ppc_md.tce_free = tce_free_pSeriesLP;
564 ppc_md.iommu_bus_setup = iommu_bus_setup_pSeriesLP;
565 ppc_md.iommu_dev_setup = iommu_dev_setup_pSeriesLP;
567 ppc_md.tce_build = tce_build_pSeries;
568 ppc_md.tce_free = tce_free_pSeries;
569 ppc_md.iommu_bus_setup = iommu_bus_setup_pSeries;
570 ppc_md.iommu_dev_setup = iommu_dev_setup_pSeries;
574 pSeries_reconfig_notifier_register(&iommu_reconfig_nb);