arch/powerpc/platforms/pseries/iommu.c

   1 /*
   2  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
   3  *
   4  * Rewrite, cleanup:
   5  *
   6  * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
   7  * Copyright (C) 2006 Olof Johansson <olof@lixom.net>
   8  *
   9  * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
  10  *
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25  */
  26
  27 #include <linux/init.h>
  28 #include <linux/types.h>
  29 #include <linux/slab.h>
  30 #include <linux/mm.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/sched.h>        /* for show_stack */
  33 #include <linux/string.h>
  34 #include <linux/pci.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/crash_dump.h>
  37 #include <linux/memory.h>
  38 #include <asm/io.h>
  39 #include <asm/prom.h>
  40 #include <asm/rtas.h>
  41 #include <asm/iommu.h>
  42 #include <asm/pci-bridge.h>
  43 #include <asm/machdep.h>
  44 #include <asm/abs_addr.h>
  45 #include <asm/pSeries_reconfig.h>
  46 #include <asm/firmware.h>
  47 #include <asm/tce.h>
  48 #include <asm/ppc-pci.h>
  49 #include <asm/udbg.h>
  50 #include <asm/mmzone.h>
  51
  52 #include "plpar_wrappers.h"
  53
  54
  55 static int tce_build_pSeries(struct iommu_table *tbl, long index,
  56                               long npages, unsigned long uaddr,
  57                               enum dma_data_direction direction,
  58                               struct dma_attrs *attrs)
  59 {
  60         u64 proto_tce;
  61         u64 *tcep;
  62         u64 rpn;
  63
  64         proto_tce = TCE_PCI_READ; // Read allowed
  65
  66         if (direction != DMA_TO_DEVICE)
  67                 proto_tce |= TCE_PCI_WRITE;
  68
  69         tcep = ((u64 *)tbl->it_base) + index;
  70
  71         while (npages--) {
  72                 /* can't move this out since we might cross MEMBLOCK boundary */
  73                 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
  74                 *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
  75
  76                 uaddr += TCE_PAGE_SIZE;
  77                 tcep++;
  78         }
  79         return 0;
  80 }
  81
  82
  83 static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
  84 {
  85         u64 *tcep;
  86
  87         tcep = ((u64 *)tbl->it_base) + index;
  88
  89         while (npages--)
  90                 *(tcep++) = 0;
  91 }
  92
  93 static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
  94 {
  95         u64 *tcep;
  96
  97         tcep = ((u64 *)tbl->it_base) + index;
  98
  99         return *tcep;
 100 }
 101
 102 static void tce_free_pSeriesLP(struct iommu_table*, long, long);
 103 static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long);
 104
 105 static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
 106                                 long npages, unsigned long uaddr,
 107                                 enum dma_data_direction direction,
 108                                 struct dma_attrs *attrs)
 109 {
 110         u64 rc = 0;
 111         u64 proto_tce, tce;
 112         u64 rpn;
 113         int ret = 0;
 114         long tcenum_start = tcenum, npages_start = npages;
 115
 116         rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
 117         proto_tce = TCE_PCI_READ;
 118         if (direction != DMA_TO_DEVICE)
 119                 proto_tce |= TCE_PCI_WRITE;
 120
 121         while (npages--) {
 122                 tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
 123                 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce);
 124
 125                 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
 126                         ret = (int)rc;
 127                         tce_free_pSeriesLP(tbl, tcenum_start,
 128                                            (npages_start - (npages + 1)));
 129                         break;
 130                 }
 131
 132                 if (rc && printk_ratelimit()) {
 133                         printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 134                         printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 135                         printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 136                         printk("\ttce val = 0x%llx\n", tce );
 137                         show_stack(current, (unsigned long *)__get_SP());
 138                 }
 139
 140                 tcenum++;
 141                 rpn++;
 142         }
 143         return ret;
 144 }
 145
 146 static DEFINE_PER_CPU(u64 *, tce_page);
 147
 148 static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
 149                                      long npages, unsigned long uaddr,
 150                                      enum dma_data_direction direction,
 151                                      struct dma_attrs *attrs)
 152 {
 153         u64 rc = 0;
 154         u64 proto_tce;
 155         u64 *tcep;
 156         u64 rpn;
 157         long l, limit;
 158         long tcenum_start = tcenum, npages_start = npages;
 159         int ret = 0;
 160
 161         if (npages == 1) {
 162                 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
 163                                            direction, attrs);
 164         }
 165
 166         tcep = __get_cpu_var(tce_page);
 167
 168         /* This is safe to do since interrupts are off when we're called
 169          * from iommu_alloc{,_sg}()
 170          */
 171         if (!tcep) {
 172                 tcep = (u64 *)__get_free_page(GFP_ATOMIC);
 173                 /* If allocation fails, fall back to the loop implementation */
 174                 if (!tcep) {
 175                         return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
 176                                             direction, attrs);
 177                 }
 178                 __get_cpu_var(tce_page) = tcep;
 179         }
 180
 181         rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
 182         proto_tce = TCE_PCI_READ;
 183         if (direction != DMA_TO_DEVICE)
 184                 proto_tce |= TCE_PCI_WRITE;
 185
 186         /* We can map max one pageful of TCEs at a time */
 187         do {
 188                 /*
 189                  * Set up the page with TCE data, looping through and setting
 190                  * the values.
 191                  */
 192                 limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE);
 193
 194                 for (l = 0; l < limit; l++) {
 195                         tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
 196                         rpn++;
 197                 }
 198
 199                 rc = plpar_tce_put_indirect((u64)tbl->it_index,
 200                                             (u64)tcenum << 12,
 201                                             (u64)virt_to_abs(tcep),
 202                                             limit);
 203
 204                 npages -= limit;
 205                 tcenum += limit;
 206         } while (npages > 0 && !rc);
 207
 208         if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
 209                 ret = (int)rc;
 210                 tce_freemulti_pSeriesLP(tbl, tcenum_start,
 211                                         (npages_start - (npages + limit)));
 212                 return ret;
 213         }
 214
 215         if (rc && printk_ratelimit()) {
 216                 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 217                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 218                 printk("\tnpages  = 0x%llx\n", (u64)npages);
 219                 printk("\ttce[0] val = 0x%llx\n", tcep[0]);
 220                 show_stack(current, (unsigned long *)__get_SP());
 221         }
 222         return ret;
 223 }
 224
 225 static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
 226 {
 227         u64 rc;
 228
 229         while (npages--) {
 230                 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0);
 231
 232                 if (rc && printk_ratelimit()) {
 233                         printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 234                         printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 235                         printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 236                         show_stack(current, (unsigned long *)__get_SP());
 237                 }
 238
 239                 tcenum++;
 240         }
 241 }
 242
 243
 244 static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
 245 {
 246         u64 rc;
 247
 248         rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages);
 249
 250         if (rc && printk_ratelimit()) {
 251                 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
 252                 printk("\trc      = %lld\n", rc);
 253                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 254                 printk("\tnpages  = 0x%llx\n", (u64)npages);
 255                 show_stack(current, (unsigned long *)__get_SP());
 256         }
 257 }
 258
 259 static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum)
 260 {
 261         u64 rc;
 262         unsigned long tce_ret;
 263
 264         rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret);
 265
 266         if (rc && printk_ratelimit()) {
 267                 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc);
 268                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 269                 printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 270                 show_stack(current, (unsigned long *)__get_SP());
 271         }
 272
 273         return tce_ret;
 274 }
 275
 276 /* this is compatible with cells for the device tree property */
 277 struct dynamic_dma_window_prop {
 278         __be32  liobn;          /* tce table number */
 279         __be64  dma_base;       /* address hi,lo */
 280         __be32  tce_shift;      /* ilog2(tce_page_size) */
 281         __be32  window_shift;   /* ilog2(tce_window_size) */
 282 };
 283
 284 struct direct_window {
 285         struct device_node *device;
 286         const struct dynamic_dma_window_prop *prop;
 287         struct list_head list;
 288 };
 289
 290 /* Dynamic DMA Window support */
 291 struct ddw_query_response {
 292         u32 windows_available;
 293         u32 largest_available_block;
 294         u32 page_size;
 295         u32 migration_capable;
 296 };
 297
 298 struct ddw_create_response {
 299         u32 liobn;
 300         u32 addr_hi;
 301         u32 addr_lo;
 302 };
 303
 304 static LIST_HEAD(direct_window_list);
 305 /* prevents races between memory on/offline and window creation */
 306 static DEFINE_SPINLOCK(direct_window_list_lock);
 307 /* protects initializing window twice for same device */
 308 static DEFINE_MUTEX(direct_window_init_mutex);
 309 #define DIRECT64_PROPNAME "linux,direct64-ddr-window-info"
 310
 311 static int tce_clearrange_multi_pSeriesLP(unsigned long start_pfn,
 312                                         unsigned long num_pfn, const void *arg)
 313 {
 314         const struct dynamic_dma_window_prop *maprange = arg;
 315         int rc;
 316         u64 tce_size, num_tce, dma_offset, next;
 317         u32 tce_shift;
 318         long limit;
 319
 320         tce_shift = be32_to_cpu(maprange->tce_shift);
 321         tce_size = 1ULL << tce_shift;
 322         next = start_pfn << PAGE_SHIFT;
 323         num_tce = num_pfn << PAGE_SHIFT;
 324
 325         /* round back to the beginning of the tce page size */
 326         num_tce += next & (tce_size - 1);
 327         next &= ~(tce_size - 1);
 328
 329         /* covert to number of tces */
 330         num_tce |= tce_size - 1;
 331         num_tce >>= tce_shift;
 332
 333         do {
 334                 /*
 335                  * Set up the page with TCE data, looping through and setting
 336                  * the values.
 337                  */
 338                 limit = min_t(long, num_tce, 512);
 339                 dma_offset = next + be64_to_cpu(maprange->dma_base);
 340
 341                 rc = plpar_tce_stuff((u64)be32_to_cpu(maprange->liobn),
 342                                              dma_offset,
 343                                              0, limit);
 344                 num_tce -= limit;
 345         } while (num_tce > 0 && !rc);
 346
 347         return rc;
 348 }
 349
 350 static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn,
 351                                         unsigned long num_pfn, const void *arg)
 352 {
 353         const struct dynamic_dma_window_prop *maprange = arg;
 354         u64 *tcep, tce_size, num_tce, dma_offset, next, proto_tce, liobn;
 355         u32 tce_shift;
 356         u64 rc = 0;
 357         long l, limit;
 358
 359         local_irq_disable();    /* to protect tcep and the page behind it */
 360         tcep = __get_cpu_var(tce_page);
 361
 362         if (!tcep) {
 363                 tcep = (u64 *)__get_free_page(GFP_ATOMIC);
 364                 if (!tcep) {
 365                         local_irq_enable();
 366                         return -ENOMEM;
 367                 }
 368                 __get_cpu_var(tce_page) = tcep;
 369         }
 370
 371         proto_tce = TCE_PCI_READ | TCE_PCI_WRITE;
 372
 373         liobn = (u64)be32_to_cpu(maprange->liobn);
 374         tce_shift = be32_to_cpu(maprange->tce_shift);
 375         tce_size = 1ULL << tce_shift;
 376         next = start_pfn << PAGE_SHIFT;
 377         num_tce = num_pfn << PAGE_SHIFT;
 378
 379         /* round back to the beginning of the tce page size */
 380         num_tce += next & (tce_size - 1);
 381         next &= ~(tce_size - 1);
 382
 383         /* covert to number of tces */
 384         num_tce |= tce_size - 1;
 385         num_tce >>= tce_shift;
 386
 387         /* We can map max one pageful of TCEs at a time */
 388         do {
 389                 /*
 390                  * Set up the page with TCE data, looping through and setting
 391                  * the values.
 392                  */
 393                 limit = min_t(long, num_tce, 4096/TCE_ENTRY_SIZE);
 394                 dma_offset = next + be64_to_cpu(maprange->dma_base);
 395
 396                 for (l = 0; l < limit; l++) {
 397                         tcep[l] = proto_tce | next;
 398                         next += tce_size;
 399                 }
 400
 401                 rc = plpar_tce_put_indirect(liobn,
 402                                             dma_offset,
 403                                             (u64)virt_to_abs(tcep),
 404                                             limit);
 405
 406                 num_tce -= limit;
 407         } while (num_tce > 0 && !rc);
 408
 409         /* error cleanup: caller will clear whole range */
 410
 411         local_irq_enable();
 412         return rc;
 413 }
 414
 415 static int tce_setrange_multi_pSeriesLP_walk(unsigned long start_pfn,
 416                 unsigned long num_pfn, void *arg)
 417 {
 418         return tce_setrange_multi_pSeriesLP(start_pfn, num_pfn, arg);
 419 }
 420
 421
 422 #ifdef CONFIG_PCI
 423 static void iommu_table_setparms(struct pci_controller *phb,
 424                                  struct device_node *dn,
 425                                  struct iommu_table *tbl)
 426 {
 427         struct device_node *node;
 428         const unsigned long *basep;
 429         const u32 *sizep;
 430
 431         node = phb->dn;
 432
 433         basep = of_get_property(node, "linux,tce-base", NULL);
 434         sizep = of_get_property(node, "linux,tce-size", NULL);
 435         if (basep == NULL || sizep == NULL) {
 436                 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
 437                                 "missing tce entries !\n", dn->full_name);
 438                 return;
 439         }
 440
 441         tbl->it_base = (unsigned long)__va(*basep);
 442
 443         if (!is_kdump_kernel())
 444                 memset((void *)tbl->it_base, 0, *sizep);
 445
 446         tbl->it_busno = phb->bus->number;
 447
 448         /* Units of tce entries */
 449         tbl->it_offset = phb->dma_window_base_cur >> IOMMU_PAGE_SHIFT;
 450
 451         /* Test if we are going over 2GB of DMA space */
 452         if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
 453                 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
 454                 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
 455         }
 456
 457         phb->dma_window_base_cur += phb->dma_window_size;
 458
 459         /* Set the tce table size - measured in entries */
 460         tbl->it_size = phb->dma_window_size >> IOMMU_PAGE_SHIFT;
 461
 462         tbl->it_index = 0;
 463         tbl->it_blocksize = 16;
 464         tbl->it_type = TCE_PCI;
 465 }
 466
 467 /*
 468  * iommu_table_setparms_lpar
 469  *
 470  * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
 471  */
 472 static void iommu_table_setparms_lpar(struct pci_controller *phb,
 473                                       struct device_node *dn,
 474                                       struct iommu_table *tbl,
 475                                       const void *dma_window)
 476 {
 477         unsigned long offset, size;
 478
 479         of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
 480
 481         tbl->it_busno = phb->bus->number;
 482         tbl->it_base   = 0;
 483         tbl->it_blocksize  = 16;
 484         tbl->it_type = TCE_PCI;
 485         tbl->it_offset = offset >> IOMMU_PAGE_SHIFT;
 486         tbl->it_size = size >> IOMMU_PAGE_SHIFT;
 487 }
 488
 489 static void pci_dma_bus_setup_pSeries(struct pci_bus *bus)
 490 {
 491         struct device_node *dn;
 492         struct iommu_table *tbl;
 493         struct device_node *isa_dn, *isa_dn_orig;
 494         struct device_node *tmp;
 495         struct pci_dn *pci;
 496         int children;
 497
 498         dn = pci_bus_to_OF_node(bus);
 499
 500         pr_debug("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name);
 501
 502         if (bus->self) {
 503                 /* This is not a root bus, any setup will be done for the
 504                  * device-side of the bridge in iommu_dev_setup_pSeries().
 505                  */
 506                 return;
 507         }
 508         pci = PCI_DN(dn);
 509
 510         /* Check if the ISA bus on the system is under
 511          * this PHB.
 512          */
 513         isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa");
 514
 515         while (isa_dn && isa_dn != dn)
 516                 isa_dn = isa_dn->parent;
 517
 518         if (isa_dn_orig)
 519                 of_node_put(isa_dn_orig);
 520
 521         /* Count number of direct PCI children of the PHB. */
 522         for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling)
 523                 children++;
 524
 525         pr_debug("Children: %d\n", children);
 526
 527         /* Calculate amount of DMA window per slot. Each window must be
 528          * a power of two (due to pci_alloc_consistent requirements).
 529          *
 530          * Keep 256MB aside for PHBs with ISA.
 531          */
 532
 533         if (!isa_dn) {
 534                 /* No ISA/IDE - just set window size and return */
 535                 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */
 536
 537                 while (pci->phb->dma_window_size * children > 0x80000000ul)
 538                         pci->phb->dma_window_size >>= 1;
 539                 pr_debug("No ISA/IDE, window size is 0x%llx\n",
 540                          pci->phb->dma_window_size);
 541                 pci->phb->dma_window_base_cur = 0;
 542
 543                 return;
 544         }
 545
 546         /* If we have ISA, then we probably have an IDE
 547          * controller too. Allocate a 128MB table but
 548          * skip the first 128MB to avoid stepping on ISA
 549          * space.
 550          */
 551         pci->phb->dma_window_size = 0x8000000ul;
 552         pci->phb->dma_window_base_cur = 0x8000000ul;
 553
 554         tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
 555                            pci->phb->node);
 556
 557         iommu_table_setparms(pci->phb, dn, tbl);
 558         pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
 559
 560         /* Divide the rest (1.75GB) among the children */
 561         pci->phb->dma_window_size = 0x80000000ul;
 562         while (pci->phb->dma_window_size * children > 0x70000000ul)
 563                 pci->phb->dma_window_size >>= 1;
 564
 565         pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size);
 566 }
 567
 568
 569 static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus)
 570 {
 571         struct iommu_table *tbl;
 572         struct device_node *dn, *pdn;
 573         struct pci_dn *ppci;
 574         const void *dma_window = NULL;
 575
 576         dn = pci_bus_to_OF_node(bus);
 577
 578         pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n",
 579                  dn->full_name);
 580
 581         /* Find nearest ibm,dma-window, walking up the device tree */
 582         for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
 583                 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
 584                 if (dma_window != NULL)
 585                         break;
 586         }
 587
 588         if (dma_window == NULL) {
 589                 pr_debug("  no ibm,dma-window property !\n");
 590                 return;
 591         }
 592
 593         ppci = PCI_DN(pdn);
 594
 595         pr_debug("  parent is %s, iommu_table: 0x%p\n",
 596                  pdn->full_name, ppci->iommu_table);
 597
 598         if (!ppci->iommu_table) {
 599                 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
 600                                    ppci->phb->node);
 601                 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
 602                 ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node);
 603                 pr_debug("  created table: %p\n", ppci->iommu_table);
 604         }
 605 }
 606
 607
 608 static void pci_dma_dev_setup_pSeries(struct pci_dev *dev)
 609 {
 610         struct device_node *dn;
 611         struct iommu_table *tbl;
 612
 613         pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev));
 614
 615         dn = dev->dev.of_node;
 616
 617         /* If we're the direct child of a root bus, then we need to allocate
 618          * an iommu table ourselves. The bus setup code should have setup
 619          * the window sizes already.
 620          */
 621         if (!dev->bus->self) {
 622                 struct pci_controller *phb = PCI_DN(dn)->phb;
 623
 624                 pr_debug(" --> first child, no bridge. Allocating iommu table.\n");
 625                 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
 626                                    phb->node);
 627                 iommu_table_setparms(phb, dn, tbl);
 628                 PCI_DN(dn)->iommu_table = iommu_init_table(tbl, phb->node);
 629                 set_iommu_table_base(&dev->dev, PCI_DN(dn)->iommu_table);
 630                 return;
 631         }
 632
 633         /* If this device is further down the bus tree, search upwards until
 634          * an already allocated iommu table is found and use that.
 635          */
 636
 637         while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL)
 638                 dn = dn->parent;
 639
 640         if (dn && PCI_DN(dn))
 641                 set_iommu_table_base(&dev->dev, PCI_DN(dn)->iommu_table);
 642         else
 643                 printk(KERN_WARNING "iommu: Device %s has no iommu table\n",
 644                        pci_name(dev));
 645 }
 646
 647 static int __read_mostly disable_ddw;
 648
 649 static int __init disable_ddw_setup(char *str)
 650 {
 651         disable_ddw = 1;
 652         printk(KERN_INFO "ppc iommu: disabling ddw.\n");
 653
 654         return 0;
 655 }
 656
 657 early_param("disable_ddw", disable_ddw_setup);
 658
 659 static void remove_ddw(struct device_node *np)
 660 {
 661         struct dynamic_dma_window_prop *dwp;
 662         struct property *win64;
 663         const u32 *ddw_avail;
 664         u64 liobn;
 665         int len, ret;
 666
 667         ddw_avail = of_get_property(np, "ibm,ddw-applicable", &len);
 668         win64 = of_find_property(np, DIRECT64_PROPNAME, NULL);
 669         if (!win64)
 670                 return;
 671
 672         if (!ddw_avail || len < 3 * sizeof(u32) || win64->length < sizeof(*dwp))
 673                 goto delprop;
 674
 675         dwp = win64->value;
 676         liobn = (u64)be32_to_cpu(dwp->liobn);
 677
 678         /* clear the whole window, note the arg is in kernel pages */
 679         ret = tce_clearrange_multi_pSeriesLP(0,
 680                 1ULL << (be32_to_cpu(dwp->window_shift) - PAGE_SHIFT), dwp);
 681         if (ret)
 682                 pr_warning("%s failed to clear tces in window.\n",
 683                          np->full_name);
 684         else
 685                 pr_debug("%s successfully cleared tces in window.\n",
 686                          np->full_name);
 687
 688         ret = rtas_call(ddw_avail[2], 1, 1, NULL, liobn);
 689         if (ret)
 690                 pr_warning("%s: failed to remove direct window: rtas returned "
 691                         "%d to ibm,remove-pe-dma-window(%x) %llx\n",
 692                         np->full_name, ret, ddw_avail[2], liobn);
 693         else
 694                 pr_debug("%s: successfully removed direct window: rtas returned "
 695                         "%d to ibm,remove-pe-dma-window(%x) %llx\n",
 696                         np->full_name, ret, ddw_avail[2], liobn);
 697
 698 delprop:
 699         ret = prom_remove_property(np, win64);
 700         if (ret)
 701                 pr_warning("%s: failed to remove direct window property: %d\n",
 702                         np->full_name, ret);
 703 }
 704
 705 static u64 find_existing_ddw(struct device_node *pdn)
 706 {
 707         struct direct_window *window;
 708         const struct dynamic_dma_window_prop *direct64;
 709         u64 dma_addr = 0;
 710
 711         spin_lock(&direct_window_list_lock);
 712         /* check if we already created a window and dupe that config if so */
 713         list_for_each_entry(window, &direct_window_list, list) {
 714                 if (window->device == pdn) {
 715                         direct64 = window->prop;
 716                         dma_addr = direct64->dma_base;
 717                         break;
 718                 }
 719         }
 720         spin_unlock(&direct_window_list_lock);
 721
 722         return dma_addr;
 723 }
 724
 725 static int find_existing_ddw_windows(void)
 726 {
 727         int len;
 728         struct device_node *pdn;
 729         struct direct_window *window;
 730         const struct dynamic_dma_window_prop *direct64;
 731
 732         if (!firmware_has_feature(FW_FEATURE_LPAR))
 733                 return 0;
 734
 735         for_each_node_with_property(pdn, DIRECT64_PROPNAME) {
 736                 direct64 = of_get_property(pdn, DIRECT64_PROPNAME, &len);
 737                 if (!direct64)
 738                         continue;
 739
 740                 window = kzalloc(sizeof(*window), GFP_KERNEL);
 741                 if (!window || len < sizeof(struct dynamic_dma_window_prop)) {
 742                         kfree(window);
 743                         remove_ddw(pdn);
 744                         continue;
 745                 }
 746
 747                 window->device = pdn;
 748                 window->prop = direct64;
 749                 spin_lock(&direct_window_list_lock);
 750                 list_add(&window->list, &direct_window_list);
 751                 spin_unlock(&direct_window_list_lock);
 752         }
 753
 754         return 0;
 755 }
 756 machine_arch_initcall(pseries, find_existing_ddw_windows);
 757
 758 static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail,
 759                         struct ddw_query_response *query)
 760 {
 761         struct device_node *dn;
 762         struct pci_dn *pcidn;
 763         u32 cfg_addr;
 764         u64 buid;
 765         int ret;
 766
 767         /*
 768          * Get the config address and phb buid of the PE window.
 769          * Rely on eeh to retrieve this for us.
 770          * Retrieve them from the pci device, not the node with the
 771          * dma-window property
 772          */
 773         dn = pci_device_to_OF_node(dev);
 774         pcidn = PCI_DN(dn);
 775         cfg_addr = pcidn->eeh_config_addr;
 776         if (pcidn->eeh_pe_config_addr)
 777                 cfg_addr = pcidn->eeh_pe_config_addr;
 778         buid = pcidn->phb->buid;
 779         ret = rtas_call(ddw_avail[0], 3, 5, (u32 *)query,
 780                   cfg_addr, BUID_HI(buid), BUID_LO(buid));
 781         dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x"
 782                 " returned %d\n", ddw_avail[0], cfg_addr, BUID_HI(buid),
 783                 BUID_LO(buid), ret);
 784         return ret;
 785 }
 786
 787 static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail,
 788                         struct ddw_create_response *create, int page_shift,
 789                         int window_shift)
 790 {
 791         struct device_node *dn;
 792         struct pci_dn *pcidn;
 793         u32 cfg_addr;
 794         u64 buid;
 795         int ret;
 796
 797         /*
 798          * Get the config address and phb buid of the PE window.
 799          * Rely on eeh to retrieve this for us.
 800          * Retrieve them from the pci device, not the node with the
 801          * dma-window property
 802          */
 803         dn = pci_device_to_OF_node(dev);
 804         pcidn = PCI_DN(dn);
 805         cfg_addr = pcidn->eeh_config_addr;
 806         if (pcidn->eeh_pe_config_addr)
 807                 cfg_addr = pcidn->eeh_pe_config_addr;
 808         buid = pcidn->phb->buid;
 809
 810         do {
 811                 /* extra outputs are LIOBN and dma-addr (hi, lo) */
 812                 ret = rtas_call(ddw_avail[1], 5, 4, (u32 *)create, cfg_addr,
 813                                 BUID_HI(buid), BUID_LO(buid), page_shift, window_shift);
 814         } while (rtas_busy_delay(ret));
 815         dev_info(&dev->dev,
 816                 "ibm,create-pe-dma-window(%x) %x %x %x %x %x returned %d "
 817                 "(liobn = 0x%x starting addr = %x %x)\n", ddw_avail[1],
 818                  cfg_addr, BUID_HI(buid), BUID_LO(buid), page_shift,
 819                  window_shift, ret, create->liobn, create->addr_hi, create->addr_lo);
 820
 821         return ret;
 822 }
 823
 824 /*
 825  * If the PE supports dynamic dma windows, and there is space for a table
 826  * that can map all pages in a linear offset, then setup such a table,
 827  * and record the dma-offset in the struct device.
 828  *
 829  * dev: the pci device we are checking
 830  * pdn: the parent pe node with the ibm,dma_window property
 831  * Future: also check if we can remap the base window for our base page size
 832  *
 833  * returns the dma offset for use by dma_set_mask
 834  */
 835 static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
 836 {
 837         int len, ret;
 838         struct ddw_query_response query;
 839         struct ddw_create_response create;
 840         int page_shift;
 841         u64 dma_addr, max_addr;
 842         struct device_node *dn;
 843         const u32 *uninitialized_var(ddw_avail);
 844         struct direct_window *window;
 845         struct property *win64;
 846         struct dynamic_dma_window_prop *ddwprop;
 847
 848         mutex_lock(&direct_window_init_mutex);
 849
 850         dma_addr = find_existing_ddw(pdn);
 851         if (dma_addr != 0)
 852                 goto out_unlock;
 853
 854         /*
 855          * the ibm,ddw-applicable property holds the tokens for:
 856          * ibm,query-pe-dma-window
 857          * ibm,create-pe-dma-window
 858          * ibm,remove-pe-dma-window
 859          * for the given node in that order.
 860          * the property is actually in the parent, not the PE
 861          */
 862         ddw_avail = of_get_property(pdn, "ibm,ddw-applicable", &len);
 863         if (!ddw_avail || len < 3 * sizeof(u32))
 864                 goto out_unlock;
 865
 866        /*
 867          * Query if there is a second window of size to map the
 868          * whole partition.  Query returns number of windows, largest
 869          * block assigned to PE (partition endpoint), and two bitmasks
 870          * of page sizes: supported and supported for migrate-dma.
 871          */
 872         dn = pci_device_to_OF_node(dev);
 873         ret = query_ddw(dev, ddw_avail, &query);
 874         if (ret != 0)
 875                 goto out_unlock;
 876
 877         if (query.windows_available == 0) {
 878                 /*
 879                  * no additional windows are available for this device.
 880                  * We might be able to reallocate the existing window,
 881                  * trading in for a larger page size.
 882                  */
 883                 dev_dbg(&dev->dev, "no free dynamic windows");
 884                 goto out_unlock;
 885         }
 886         if (query.page_size & 4) {
 887                 page_shift = 24; /* 16MB */
 888         } else if (query.page_size & 2) {
 889                 page_shift = 16; /* 64kB */
 890         } else if (query.page_size & 1) {
 891                 page_shift = 12; /* 4kB */
 892         } else {
 893                 dev_dbg(&dev->dev, "no supported direct page size in mask %x",
 894                           query.page_size);
 895                 goto out_unlock;
 896         }
 897         /* verify the window * number of ptes will map the partition */
 898         /* check largest block * page size > max memory hotplug addr */
 899         max_addr = memory_hotplug_max();
 900         if (query.largest_available_block < (max_addr >> page_shift)) {
 901                 dev_dbg(&dev->dev, "can't map partiton max 0x%llx with %u "
 902                           "%llu-sized pages\n", max_addr,  query.largest_available_block,
 903                           1ULL << page_shift);
 904                 goto out_unlock;
 905         }
 906         len = order_base_2(max_addr);
 907         win64 = kzalloc(sizeof(struct property), GFP_KERNEL);
 908         if (!win64) {
 909                 dev_info(&dev->dev,
 910                         "couldn't allocate property for 64bit dma window\n");
 911                 goto out_unlock;
 912         }
 913         win64->name = kstrdup(DIRECT64_PROPNAME, GFP_KERNEL);
 914         win64->value = ddwprop = kmalloc(sizeof(*ddwprop), GFP_KERNEL);
 915         win64->length = sizeof(*ddwprop);
 916         if (!win64->name || !win64->value) {
 917                 dev_info(&dev->dev,
 918                         "couldn't allocate property name and value\n");
 919                 goto out_free_prop;
 920         }
 921
 922         ret = create_ddw(dev, ddw_avail, &create, page_shift, len);
 923         if (ret != 0)
 924                 goto out_free_prop;
 925
 926         ddwprop->liobn = cpu_to_be32(create.liobn);
 927         ddwprop->dma_base = cpu_to_be64(of_read_number(&create.addr_hi, 2));
 928         ddwprop->tce_shift = cpu_to_be32(page_shift);
 929         ddwprop->window_shift = cpu_to_be32(len);
 930
 931         dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %s\n",
 932                   create.liobn, dn->full_name);
 933
 934         window = kzalloc(sizeof(*window), GFP_KERNEL);
 935         if (!window)
 936                 goto out_clear_window;
 937
 938         ret = walk_system_ram_range(0, memblock_end_of_DRAM() >> PAGE_SHIFT,
 939                         win64->value, tce_setrange_multi_pSeriesLP_walk);
 940         if (ret) {
 941                 dev_info(&dev->dev, "failed to map direct window for %s: %d\n",
 942                          dn->full_name, ret);
 943                 goto out_free_window;
 944         }
 945
 946         ret = prom_add_property(pdn, win64);
 947         if (ret) {
 948                 dev_err(&dev->dev, "unable to add dma window property for %s: %d",
 949                          pdn->full_name, ret);
 950                 goto out_free_window;
 951         }
 952
 953         window->device = pdn;
 954         window->prop = ddwprop;
 955         spin_lock(&direct_window_list_lock);
 956         list_add(&window->list, &direct_window_list);
 957         spin_unlock(&direct_window_list_lock);
 958
 959         dma_addr = of_read_number(&create.addr_hi, 2);
 960         goto out_unlock;
 961
 962 out_free_window:
 963         kfree(window);
 964
 965 out_clear_window:
 966         remove_ddw(pdn);
 967
 968 out_free_prop:
 969         kfree(win64->name);
 970         kfree(win64->value);
 971         kfree(win64);
 972
 973 out_unlock:
 974         mutex_unlock(&direct_window_init_mutex);
 975         return dma_addr;
 976 }
 977
 978 static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
 979 {
 980         struct device_node *pdn, *dn;
 981         struct iommu_table *tbl;
 982         const void *dma_window = NULL;
 983         struct pci_dn *pci;
 984
 985         pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev));
 986
 987         /* dev setup for LPAR is a little tricky, since the device tree might
 988          * contain the dma-window properties per-device and not necessarily
 989          * for the bus. So we need to search upwards in the tree until we
 990          * either hit a dma-window property, OR find a parent with a table
 991          * already allocated.
 992          */
 993         dn = pci_device_to_OF_node(dev);
 994         pr_debug("  node is %s\n", dn->full_name);
 995
 996         for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table;
 997              pdn = pdn->parent) {
 998                 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
 999                 if (dma_window)
1000                         break;
1001         }
1002
1003         if (!pdn || !PCI_DN(pdn)) {
1004                 printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: "
1005                        "no DMA window found for pci dev=%s dn=%s\n",
1006                                  pci_name(dev), dn? dn->full_name : "<null>");
1007                 return;
1008         }
1009         pr_debug("  parent is %s\n", pdn->full_name);
1010
1011         pci = PCI_DN(pdn);
1012         if (!pci->iommu_table) {
1013                 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
1014                                    pci->phb->node);
1015                 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
1016                 pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
1017                 pr_debug("  created table: %p\n", pci->iommu_table);
1018         } else {
1019                 pr_debug("  found DMA window, table: %p\n", pci->iommu_table);
1020         }
1021
1022         set_iommu_table_base(&dev->dev, pci->iommu_table);
1023 }
1024
1025 static int dma_set_mask_pSeriesLP(struct device *dev, u64 dma_mask)
1026 {
1027         bool ddw_enabled = false;
1028         struct device_node *pdn, *dn;
1029         struct pci_dev *pdev;
1030         const void *dma_window = NULL;
1031         u64 dma_offset;
1032
1033         if (!dev->dma_mask)
1034                 return -EIO;
1035
1036         if (!dev_is_pci(dev))
1037                 goto check_mask;
1038
1039         pdev = to_pci_dev(dev);
1040
1041         /* only attempt to use a new window if 64-bit DMA is requested */
1042         if (!disable_ddw && dma_mask == DMA_BIT_MASK(64)) {
1043                 dn = pci_device_to_OF_node(pdev);
1044                 dev_dbg(dev, "node is %s\n", dn->full_name);
1045
1046                 /*
1047                  * the device tree might contain the dma-window properties
1048                  * per-device and not necessarily for the bus. So we need to
1049                  * search upwards in the tree until we either hit a dma-window
1050                  * property, OR find a parent with a table already allocated.
1051                  */
1052                 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table;
1053                                 pdn = pdn->parent) {
1054                         dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1055                         if (dma_window)
1056                                 break;
1057                 }
1058                 if (pdn && PCI_DN(pdn)) {
1059                         dma_offset = enable_ddw(pdev, pdn);
1060                         if (dma_offset != 0) {
1061                                 dev_info(dev, "Using 64-bit direct DMA at offset %llx\n", dma_offset);
1062                                 set_dma_offset(dev, dma_offset);
1063                                 set_dma_ops(dev, &dma_direct_ops);
1064                                 ddw_enabled = true;
1065                         }
1066                 }
1067         }
1068
1069         /* fall back on iommu ops, restore table pointer with ops */
1070         if (!ddw_enabled && get_dma_ops(dev) != &dma_iommu_ops) {
1071                 dev_info(dev, "Restoring 32-bit DMA via iommu\n");
1072                 set_dma_ops(dev, &dma_iommu_ops);
1073                 pci_dma_dev_setup_pSeriesLP(pdev);
1074         }
1075
1076 check_mask:
1077         if (!dma_supported(dev, dma_mask))
1078                 return -EIO;
1079
1080         *dev->dma_mask = dma_mask;
1081         return 0;
1082 }
1083
1084 static u64 dma_get_required_mask_pSeriesLP(struct device *dev)
1085 {
1086         if (!dev->dma_mask)
1087                 return 0;
1088
1089         if (!disable_ddw && dev_is_pci(dev)) {
1090                 struct pci_dev *pdev = to_pci_dev(dev);
1091                 struct device_node *dn;
1092
1093                 dn = pci_device_to_OF_node(pdev);
1094
1095                 /* search upwards for ibm,dma-window */
1096                 for (; dn && PCI_DN(dn) && !PCI_DN(dn)->iommu_table;
1097                                 dn = dn->parent)
1098                         if (of_get_property(dn, "ibm,dma-window", NULL))
1099                                 break;
1100                 /* if there is a ibm,ddw-applicable property require 64 bits */
1101                 if (dn && PCI_DN(dn) &&
1102                                 of_get_property(dn, "ibm,ddw-applicable", NULL))
1103                         return DMA_BIT_MASK(64);
1104         }
1105
1106         return dma_iommu_ops.get_required_mask(dev);
1107 }
1108
1109 #else  /* CONFIG_PCI */
1110 #define pci_dma_bus_setup_pSeries       NULL
1111 #define pci_dma_dev_setup_pSeries       NULL
1112 #define pci_dma_bus_setup_pSeriesLP     NULL
1113 #define pci_dma_dev_setup_pSeriesLP     NULL
1114 #define dma_set_mask_pSeriesLP          NULL
1115 #define dma_get_required_mask_pSeriesLP NULL
1116 #endif /* !CONFIG_PCI */
1117
1118 static int iommu_mem_notifier(struct notifier_block *nb, unsigned long action,
1119                 void *data)
1120 {
1121         struct direct_window *window;
1122         struct memory_notify *arg = data;
1123         int ret = 0;
1124
1125         switch (action) {
1126         case MEM_GOING_ONLINE:
1127                 spin_lock(&direct_window_list_lock);
1128                 list_for_each_entry(window, &direct_window_list, list) {
1129                         ret |= tce_setrange_multi_pSeriesLP(arg->start_pfn,
1130                                         arg->nr_pages, window->prop);
1131                         /* XXX log error */
1132                 }
1133                 spin_unlock(&direct_window_list_lock);
1134                 break;
1135         case MEM_CANCEL_ONLINE:
1136         case MEM_OFFLINE:
1137                 spin_lock(&direct_window_list_lock);
1138                 list_for_each_entry(window, &direct_window_list, list) {
1139                         ret |= tce_clearrange_multi_pSeriesLP(arg->start_pfn,
1140                                         arg->nr_pages, window->prop);
1141                         /* XXX log error */
1142                 }
1143                 spin_unlock(&direct_window_list_lock);
1144                 break;
1145         default:
1146                 break;
1147         }
1148         if (ret && action != MEM_CANCEL_ONLINE)
1149                 return NOTIFY_BAD;
1150
1151         return NOTIFY_OK;
1152 }
1153
1154 static struct notifier_block iommu_mem_nb = {
1155         .notifier_call = iommu_mem_notifier,
1156 };
1157
1158 static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node)
1159 {
1160         int err = NOTIFY_OK;
1161         struct device_node *np = node;
1162         struct pci_dn *pci = PCI_DN(np);
1163         struct direct_window *window;
1164
1165         switch (action) {
1166         case PSERIES_RECONFIG_REMOVE:
1167                 if (pci && pci->iommu_table)
1168                         iommu_free_table(pci->iommu_table, np->full_name);
1169
1170                 spin_lock(&direct_window_list_lock);
1171                 list_for_each_entry(window, &direct_window_list, list) {
1172                         if (window->device == np) {
1173                                 list_del(&window->list);
1174                                 kfree(window);
1175                                 break;
1176                         }
1177                 }
1178                 spin_unlock(&direct_window_list_lock);
1179
1180                 /*
1181                  * Because the notifier runs after isolation of the
1182                  * slot, we are guaranteed any DMA window has already
1183                  * been revoked and the TCEs have been marked invalid,
1184                  * so we don't need a call to remove_ddw(np). However,
1185                  * if an additional notifier action is added before the
1186                  * isolate call, we should update this code for
1187                  * completeness with such a call.
1188                  */
1189                 break;
1190         default:
1191                 err = NOTIFY_DONE;
1192                 break;
1193         }
1194         return err;
1195 }
1196
1197 static struct notifier_block iommu_reconfig_nb = {
1198         .notifier_call = iommu_reconfig_notifier,
1199 };
1200
1201 /* These are called very early. */
1202 void iommu_init_early_pSeries(void)
1203 {
1204         if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL))
1205                 return;
1206
1207         if (firmware_has_feature(FW_FEATURE_LPAR)) {
1208                 if (firmware_has_feature(FW_FEATURE_MULTITCE)) {
1209                         ppc_md.tce_build = tce_buildmulti_pSeriesLP;
1210                         ppc_md.tce_free  = tce_freemulti_pSeriesLP;
1211                 } else {
1212                         ppc_md.tce_build = tce_build_pSeriesLP;
1213                         ppc_md.tce_free  = tce_free_pSeriesLP;
1214                 }
1215                 ppc_md.tce_get   = tce_get_pSeriesLP;
1216                 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeriesLP;
1217                 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeriesLP;
1218                 ppc_md.dma_set_mask = dma_set_mask_pSeriesLP;
1219                 ppc_md.dma_get_required_mask = dma_get_required_mask_pSeriesLP;
1220         } else {
1221                 ppc_md.tce_build = tce_build_pSeries;
1222                 ppc_md.tce_free  = tce_free_pSeries;
1223                 ppc_md.tce_get   = tce_get_pseries;
1224                 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeries;
1225                 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeries;
1226         }
1227
1228
1229         pSeries_reconfig_notifier_register(&iommu_reconfig_nb);
1230         register_memory_notifier(&iommu_mem_nb);
1231
1232         set_pci_dma_ops(&dma_iommu_ops);
1233 }
1234
1235 static int __init disable_multitce(char *str)
1236 {
1237         if (strcmp(str, "off") == 0 &&
1238             firmware_has_feature(FW_FEATURE_LPAR) &&
1239             firmware_has_feature(FW_FEATURE_MULTITCE)) {
1240                 printk(KERN_INFO "Disabling MULTITCE firmware feature\n");
1241                 ppc_md.tce_build = tce_build_pSeriesLP;
1242                 ppc_md.tce_free  = tce_free_pSeriesLP;
1243                 powerpc_firmware_features &= ~FW_FEATURE_MULTITCE;
1244         }
1245         return 1;
1246 }
1247
1248 __setup("multitce=", disable_multitce);