2 * Support for PCI bridges found on Power Macintoshes.
4 * Copyright (C) 2003-2005 Benjamin Herrenschmuidt (benh@kernel.crashing.org)
5 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include <linux/string.h>
17 #include <linux/init.h>
18 #include <linux/bootmem.h>
19 #include <linux/irq.h>
20 #include <linux/of_pci.h>
22 #include <asm/sections.h>
25 #include <asm/pci-bridge.h>
26 #include <asm/machdep.h>
27 #include <asm/pmac_feature.h>
28 #include <asm/grackle.h>
29 #include <asm/ppc-pci.h>
34 #define DBG(x...) printk(x)
39 /* XXX Could be per-controller, but I don't think we risk anything by
40 * assuming we won't have both UniNorth and Bandit */
41 static int has_uninorth;
43 static struct pci_controller *u3_agp;
45 static int has_second_ohare;
46 #endif /* CONFIG_PPC64 */
48 extern int pcibios_assign_bus_offset;
50 struct device_node *k2_skiplist[2];
53 * Magic constants for enabling cache coherency in the bandit/PSX bridge.
55 #define BANDIT_DEVID_2 8
56 #define BANDIT_REVID 3
58 #define BANDIT_DEVNUM 11
59 #define BANDIT_MAGIC 0x50
60 #define BANDIT_COHERENT 0x40
62 static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
64 for (; node != 0;node = node->sibling) {
65 const int * bus_range;
66 const unsigned int *class_code;
69 /* For PCI<->PCI bridges or CardBus bridges, we go down */
70 class_code = of_get_property(node, "class-code", NULL);
71 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
72 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
74 bus_range = of_get_property(node, "bus-range", &len);
75 if (bus_range != NULL && len > 2 * sizeof(int)) {
76 if (bus_range[1] > higher)
77 higher = bus_range[1];
79 higher = fixup_one_level_bus_range(node->child, higher);
84 /* This routine fixes the "bus-range" property of all bridges in the
85 * system since they tend to have their "last" member wrong on macs
87 * Note that the bus numbers manipulated here are OF bus numbers, they
88 * are not Linux bus numbers.
90 static void __init fixup_bus_range(struct device_node *bridge)
93 struct property *prop;
95 /* Lookup the "bus-range" property for the hose */
96 prop = of_find_property(bridge, "bus-range", &len);
97 if (prop == NULL || prop->length < 2 * sizeof(int))
100 bus_range = prop->value;
101 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
105 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
107 * The "Bandit" version is present in all early PCI PowerMacs,
108 * and up to the first ones using Grackle. Some machines may
109 * have 2 bandit controllers (2 PCI busses).
111 * "Chaos" is used in some "Bandit"-type machines as a bridge
112 * for the separate display bus. It is accessed the same
113 * way as bandit, but cannot be probed for devices. It therefore
114 * has its own config access functions.
116 * The "UniNorth" version is present in all Core99 machines
117 * (iBook, G4, new IMacs, and all the recent Apple machines).
118 * It contains 3 controllers in one ASIC.
120 * The U3 is the bridge used on G5 machines. It contains an
121 * AGP bus which is dealt with the old UniNorth access routines
122 * and a HyperTransport bus which uses its own set of access
126 #define MACRISC_CFA0(devfn, off) \
127 ((1 << (unsigned int)PCI_SLOT(dev_fn)) \
128 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \
129 | (((unsigned int)(off)) & 0xFCUL))
131 #define MACRISC_CFA1(bus, devfn, off) \
132 ((((unsigned int)(bus)) << 16) \
133 |(((unsigned int)(devfn)) << 8) \
134 |(((unsigned int)(off)) & 0xFCUL) \
137 static volatile void __iomem *macrisc_cfg_access(struct pci_controller* hose,
138 u8 bus, u8 dev_fn, u8 offset)
142 if (bus == hose->first_busno) {
143 if (dev_fn < (11 << 3))
145 caddr = MACRISC_CFA0(dev_fn, offset);
147 caddr = MACRISC_CFA1(bus, dev_fn, offset);
149 /* Uninorth will return garbage if we don't read back the value ! */
151 out_le32(hose->cfg_addr, caddr);
152 } while (in_le32(hose->cfg_addr) != caddr);
154 offset &= has_uninorth ? 0x07 : 0x03;
155 return hose->cfg_data + offset;
158 static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn,
159 int offset, int len, u32 *val)
161 struct pci_controller *hose;
162 volatile void __iomem *addr;
164 hose = pci_bus_to_host(bus);
166 return PCIBIOS_DEVICE_NOT_FOUND;
168 return PCIBIOS_BAD_REGISTER_NUMBER;
169 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
171 return PCIBIOS_DEVICE_NOT_FOUND;
173 * Note: the caller has already checked that offset is
174 * suitably aligned and that len is 1, 2 or 4.
181 *val = in_le16(addr);
184 *val = in_le32(addr);
187 return PCIBIOS_SUCCESSFUL;
190 static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn,
191 int offset, int len, u32 val)
193 struct pci_controller *hose;
194 volatile void __iomem *addr;
196 hose = pci_bus_to_host(bus);
198 return PCIBIOS_DEVICE_NOT_FOUND;
200 return PCIBIOS_BAD_REGISTER_NUMBER;
201 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
203 return PCIBIOS_DEVICE_NOT_FOUND;
205 * Note: the caller has already checked that offset is
206 * suitably aligned and that len is 1, 2 or 4.
219 return PCIBIOS_SUCCESSFUL;
222 static struct pci_ops macrisc_pci_ops =
224 .read = macrisc_read_config,
225 .write = macrisc_write_config,
230 * Verify that a specific (bus, dev_fn) exists on chaos
232 static int chaos_validate_dev(struct pci_bus *bus, int devfn, int offset)
234 struct device_node *np;
235 const u32 *vendor, *device;
238 return PCIBIOS_BAD_REGISTER_NUMBER;
239 np = of_pci_find_child_device(bus->dev.of_node, devfn);
241 return PCIBIOS_DEVICE_NOT_FOUND;
243 vendor = of_get_property(np, "vendor-id", NULL);
244 device = of_get_property(np, "device-id", NULL);
245 if (vendor == NULL || device == NULL)
246 return PCIBIOS_DEVICE_NOT_FOUND;
248 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10)
249 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24))
250 return PCIBIOS_BAD_REGISTER_NUMBER;
252 return PCIBIOS_SUCCESSFUL;
256 chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
259 int result = chaos_validate_dev(bus, devfn, offset);
260 if (result == PCIBIOS_BAD_REGISTER_NUMBER)
262 if (result != PCIBIOS_SUCCESSFUL)
264 return macrisc_read_config(bus, devfn, offset, len, val);
268 chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
271 int result = chaos_validate_dev(bus, devfn, offset);
272 if (result != PCIBIOS_SUCCESSFUL)
274 return macrisc_write_config(bus, devfn, offset, len, val);
277 static struct pci_ops chaos_pci_ops =
279 .read = chaos_read_config,
280 .write = chaos_write_config,
283 static void __init setup_chaos(struct pci_controller *hose,
284 struct resource *addr)
286 /* assume a `chaos' bridge */
287 hose->ops = &chaos_pci_ops;
288 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
289 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
291 #endif /* CONFIG_PPC32 */
295 * These versions of U3 HyperTransport config space access ops do not
296 * implement self-view of the HT host yet
300 * This function deals with some "special cases" devices.
302 * 0 -> No special case
303 * 1 -> Skip the device but act as if the access was successful
304 * (return 0xff's on reads, eventually, cache config space
305 * accesses in a later version)
306 * -1 -> Hide the device (unsuccessful access)
308 static int u3_ht_skip_device(struct pci_controller *hose,
309 struct pci_bus *bus, unsigned int devfn)
311 struct device_node *busdn, *dn;
314 /* We only allow config cycles to devices that are in OF device-tree
315 * as we are apparently having some weird things going on with some
316 * revs of K2 on recent G5s, except for the host bridge itself, which
317 * is missing from the tree but we know we can probe.
320 busdn = pci_device_to_OF_node(bus->self);
325 for (dn = busdn->child; dn; dn = dn->sibling)
326 if (PCI_DN(dn) && PCI_DN(dn)->devfn == devfn)
332 * When a device in K2 is powered down, we die on config
333 * cycle accesses. Fix that here.
336 if (k2_skiplist[i] == dn)
342 #define U3_HT_CFA0(devfn, off) \
343 ((((unsigned int)devfn) << 8) | offset)
344 #define U3_HT_CFA1(bus, devfn, off) \
345 (U3_HT_CFA0(devfn, off) \
346 + (((unsigned int)bus) << 16) \
349 static void __iomem *u3_ht_cfg_access(struct pci_controller *hose, u8 bus,
350 u8 devfn, u8 offset, int *swap)
353 if (bus == hose->first_busno) {
355 return hose->cfg_data + U3_HT_CFA0(devfn, offset);
357 return ((void __iomem *)hose->cfg_addr) + (offset << 2);
359 return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset);
362 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
363 int offset, int len, u32 *val)
365 struct pci_controller *hose;
369 hose = pci_bus_to_host(bus);
371 return PCIBIOS_DEVICE_NOT_FOUND;
373 return PCIBIOS_BAD_REGISTER_NUMBER;
374 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap);
376 return PCIBIOS_DEVICE_NOT_FOUND;
378 switch (u3_ht_skip_device(hose, bus, devfn)) {
386 *val = 0xffff; break;
388 *val = 0xfffffffful; break;
390 return PCIBIOS_SUCCESSFUL;
392 return PCIBIOS_DEVICE_NOT_FOUND;
396 * Note: the caller has already checked that offset is
397 * suitably aligned and that len is 1, 2 or 4.
404 *val = swap ? in_le16(addr) : in_be16(addr);
407 *val = swap ? in_le32(addr) : in_be32(addr);
410 return PCIBIOS_SUCCESSFUL;
413 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
414 int offset, int len, u32 val)
416 struct pci_controller *hose;
420 hose = pci_bus_to_host(bus);
422 return PCIBIOS_DEVICE_NOT_FOUND;
424 return PCIBIOS_BAD_REGISTER_NUMBER;
425 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap);
427 return PCIBIOS_DEVICE_NOT_FOUND;
429 switch (u3_ht_skip_device(hose, bus, devfn)) {
433 return PCIBIOS_SUCCESSFUL;
435 return PCIBIOS_DEVICE_NOT_FOUND;
439 * Note: the caller has already checked that offset is
440 * suitably aligned and that len is 1, 2 or 4.
447 swap ? out_le16(addr, val) : out_be16(addr, val);
450 swap ? out_le32(addr, val) : out_be32(addr, val);
453 return PCIBIOS_SUCCESSFUL;
456 static struct pci_ops u3_ht_pci_ops =
458 .read = u3_ht_read_config,
459 .write = u3_ht_write_config,
462 #define U4_PCIE_CFA0(devfn, off) \
463 ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \
464 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \
465 | ((((unsigned int)(off)) >> 8) << 28) \
466 | (((unsigned int)(off)) & 0xfcU))
468 #define U4_PCIE_CFA1(bus, devfn, off) \
469 ((((unsigned int)(bus)) << 16) \
470 |(((unsigned int)(devfn)) << 8) \
471 | ((((unsigned int)(off)) >> 8) << 28) \
472 |(((unsigned int)(off)) & 0xfcU) \
475 static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose,
476 u8 bus, u8 dev_fn, int offset)
480 if (bus == hose->first_busno) {
481 caddr = U4_PCIE_CFA0(dev_fn, offset);
483 caddr = U4_PCIE_CFA1(bus, dev_fn, offset);
485 /* Uninorth will return garbage if we don't read back the value ! */
487 out_le32(hose->cfg_addr, caddr);
488 } while (in_le32(hose->cfg_addr) != caddr);
491 return hose->cfg_data + offset;
494 static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
495 int offset, int len, u32 *val)
497 struct pci_controller *hose;
498 volatile void __iomem *addr;
500 hose = pci_bus_to_host(bus);
502 return PCIBIOS_DEVICE_NOT_FOUND;
503 if (offset >= 0x1000)
504 return PCIBIOS_BAD_REGISTER_NUMBER;
505 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
507 return PCIBIOS_DEVICE_NOT_FOUND;
509 * Note: the caller has already checked that offset is
510 * suitably aligned and that len is 1, 2 or 4.
517 *val = in_le16(addr);
520 *val = in_le32(addr);
523 return PCIBIOS_SUCCESSFUL;
526 static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
527 int offset, int len, u32 val)
529 struct pci_controller *hose;
530 volatile void __iomem *addr;
532 hose = pci_bus_to_host(bus);
534 return PCIBIOS_DEVICE_NOT_FOUND;
535 if (offset >= 0x1000)
536 return PCIBIOS_BAD_REGISTER_NUMBER;
537 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
539 return PCIBIOS_DEVICE_NOT_FOUND;
541 * Note: the caller has already checked that offset is
542 * suitably aligned and that len is 1, 2 or 4.
555 return PCIBIOS_SUCCESSFUL;
558 static struct pci_ops u4_pcie_pci_ops =
560 .read = u4_pcie_read_config,
561 .write = u4_pcie_write_config,
564 #endif /* CONFIG_PPC64 */
568 * For a bandit bridge, turn on cache coherency if necessary.
569 * N.B. we could clean this up using the hose ops directly.
571 static void __init init_bandit(struct pci_controller *bp)
573 unsigned int vendev, magic;
576 /* read the word at offset 0 in config space for device 11 */
577 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID);
579 vendev = in_le32(bp->cfg_data);
580 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) +
581 PCI_VENDOR_ID_APPLE) {
582 /* read the revision id */
583 out_le32(bp->cfg_addr,
584 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID);
586 rev = in_8(bp->cfg_data);
587 if (rev != BANDIT_REVID)
589 "Unknown revision %d for bandit\n", rev);
590 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) {
591 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev);
595 /* read the word at offset 0x50 */
596 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC);
598 magic = in_le32(bp->cfg_data);
599 if ((magic & BANDIT_COHERENT) != 0)
601 magic |= BANDIT_COHERENT;
603 out_le32(bp->cfg_data, magic);
604 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n");
608 * Tweak the PCI-PCI bridge chip on the blue & white G3s.
610 static void __init init_p2pbridge(void)
612 struct device_node *p2pbridge;
613 struct pci_controller* hose;
617 /* XXX it would be better here to identify the specific
618 PCI-PCI bridge chip we have. */
619 p2pbridge = of_find_node_by_name(NULL, "pci-bridge");
620 if (p2pbridge == NULL
621 || p2pbridge->parent == NULL
622 || strcmp(p2pbridge->parent->name, "pci") != 0)
624 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) {
625 DBG("Can't find PCI infos for PCI<->PCI bridge\n");
628 /* Warning: At this point, we have not yet renumbered all busses.
629 * So we must use OF walking to find out hose
631 hose = pci_find_hose_for_OF_device(p2pbridge);
633 DBG("Can't find hose for PCI<->PCI bridge\n");
636 if (early_read_config_word(hose, bus, devfn,
637 PCI_BRIDGE_CONTROL, &val) < 0) {
638 printk(KERN_ERR "init_p2pbridge: couldn't read bridge"
642 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT;
643 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val);
645 of_node_put(p2pbridge);
648 static void __init init_second_ohare(void)
650 struct device_node *np = of_find_node_by_name(NULL, "pci106b,7");
651 unsigned char bus, devfn;
657 /* This must run before we initialize the PICs since the second
658 * ohare hosts a PIC that will be accessed there.
660 if (pci_device_from_OF_node(np, &bus, &devfn) == 0) {
661 struct pci_controller* hose =
662 pci_find_hose_for_OF_device(np);
664 printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
668 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
669 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
670 cmd &= ~PCI_COMMAND_IO;
671 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
673 has_second_ohare = 1;
678 * Some Apple desktop machines have a NEC PD720100A USB2 controller
679 * on the motherboard. Open Firmware, on these, will disable the
680 * EHCI part of it so it behaves like a pair of OHCI's. This fixup
681 * code re-enables it ;)
683 static void __init fixup_nec_usb2(void)
685 struct device_node *nec;
687 for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) {
688 struct pci_controller *hose;
693 prop = of_get_property(nec, "vendor-id", NULL);
698 prop = of_get_property(nec, "device-id", NULL);
703 prop = of_get_property(nec, "reg", NULL);
706 devfn = (prop[0] >> 8) & 0xff;
707 bus = (prop[0] >> 16) & 0xff;
708 if (PCI_FUNC(devfn) != 0)
710 hose = pci_find_hose_for_OF_device(nec);
713 early_read_config_dword(hose, bus, devfn, 0xe4, &data);
715 printk("Found NEC PD720100A USB2 chip with disabled"
716 " EHCI, fixing up...\n");
718 early_write_config_dword(hose, bus, devfn, 0xe4, data);
723 static void __init setup_bandit(struct pci_controller *hose,
724 struct resource *addr)
726 hose->ops = ¯isc_pci_ops;
727 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
728 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
732 static int __init setup_uninorth(struct pci_controller *hose,
733 struct resource *addr)
735 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
737 hose->ops = ¯isc_pci_ops;
738 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
739 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
740 /* We "know" that the bridge at f2000000 has the PCI slots. */
741 return addr->start == 0xf2000000;
743 #endif /* CONFIG_PPC32 */
746 static void __init setup_u3_agp(struct pci_controller* hose)
748 /* On G5, we move AGP up to high bus number so we don't need
749 * to reassign bus numbers for HT. If we ever have P2P bridges
750 * on AGP, we'll have to move pci_assign_all_busses to the
751 * pci_controller structure so we enable it for AGP and not for
753 * We hard code the address because of the different size of
754 * the reg address cell, we shall fix that by killing struct
755 * reg_property and using some accessor functions instead
757 hose->first_busno = 0xf0;
758 hose->last_busno = 0xff;
760 hose->ops = ¯isc_pci_ops;
761 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
762 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
766 static void __init setup_u4_pcie(struct pci_controller* hose)
768 /* We currently only implement the "non-atomic" config space, to
769 * be optimised later.
771 hose->ops = &u4_pcie_pci_ops;
772 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
773 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
775 /* The bus contains a bridge from root -> device, we need to
776 * make it visible on bus 0 so that we pick the right type
777 * of config cycles. If we didn't, we would have to force all
778 * config cycles to be type 1. So we override the "bus-range"
781 hose->first_busno = 0x00;
782 hose->last_busno = 0xff;
785 static void __init parse_region_decode(struct pci_controller *hose,
788 unsigned long base, end, next = -1;
791 /* Iterate through all bits. We ignore the last bit as this region is
792 * reserved for the ROM among other niceties
794 for (i = 0; i < 31; i++) {
795 if ((decode & (0x80000000 >> i)) == 0)
798 base = 0xf0000000 | (((u32)i) << 24);
799 end = base + 0x00ffffff;
801 base = ((u32)i-16) << 28;
802 end = base + 0x0fffffff;
806 printk(KERN_WARNING "PCI: Too many ranges !\n");
809 hose->mem_resources[cur].flags = IORESOURCE_MEM;
810 hose->mem_resources[cur].name = hose->dn->full_name;
811 hose->mem_resources[cur].start = base;
812 hose->mem_resources[cur].end = end;
813 DBG(" %d: 0x%08lx-0x%08lx\n", cur, base, end);
815 DBG(" : -0x%08lx\n", end);
816 hose->mem_resources[cur].end = end;
822 static void __init setup_u3_ht(struct pci_controller* hose)
824 struct device_node *np = hose->dn;
825 struct resource cfg_res, self_res;
828 hose->ops = &u3_ht_pci_ops;
830 /* Get base addresses from OF tree
832 if (of_address_to_resource(np, 0, &cfg_res) ||
833 of_address_to_resource(np, 1, &self_res)) {
834 printk(KERN_ERR "PCI: Failed to get U3/U4 HT resources !\n");
838 /* Map external cfg space access into cfg_data and self registers
841 hose->cfg_data = ioremap(cfg_res.start, 0x02000000);
842 hose->cfg_addr = ioremap(self_res.start,
843 self_res.end - self_res.start + 1);
846 * /ht node doesn't expose a "ranges" property, we read the register
847 * that controls the decoding logic and use that for memory regions.
848 * The IO region is hard coded since it is fixed in HW as well.
850 hose->io_base_phys = 0xf4000000;
851 hose->pci_io_size = 0x00400000;
852 hose->io_resource.name = np->full_name;
853 hose->io_resource.start = 0;
854 hose->io_resource.end = 0x003fffff;
855 hose->io_resource.flags = IORESOURCE_IO;
856 hose->pci_mem_offset = 0;
857 hose->first_busno = 0;
858 hose->last_busno = 0xef;
860 /* Note: fix offset when cfg_addr becomes a void * */
861 decode = in_be32(hose->cfg_addr + 0x80);
863 DBG("PCI: Apple HT bridge decode register: 0x%08x\n", decode);
865 /* NOTE: The decode register setup is a bit weird... region
866 * 0xf8000000 for example is marked as enabled in there while it's
867 & actually the memory controller registers.
868 * That means that we are incorrectly attributing it to HT.
870 * In a similar vein, region 0xf4000000 is actually the HT IO space but
871 * also marked as enabled in here and 0xf9000000 is used by some other
872 * internal bits of the northbridge.
874 * Unfortunately, we can't just mask out those bit as we would end
875 * up with more regions than we can cope (linux can only cope with
876 * 3 memory regions for a PHB at this stage).
878 * So for now, we just do a little hack. We happen to -know- that
879 * Apple firmware doesn't assign things below 0xfa000000 for that
880 * bridge anyway so we mask out all bits we don't want.
882 decode &= 0x003fffff;
884 /* Now parse the resulting bits and build resources */
885 parse_region_decode(hose, decode);
887 #endif /* CONFIG_PPC64 */
890 * We assume that if we have a G3 powermac, we have one bridge called
891 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
892 * if we have one or more bandit or chaos bridges, we don't have a MPC106.
894 static int __init pmac_add_bridge(struct device_node *dev)
897 struct pci_controller *hose;
898 struct resource rsrc;
900 const int *bus_range;
901 int primary = 1, has_address = 0;
903 DBG("Adding PCI host bridge %s\n", dev->full_name);
905 /* Fetch host bridge registers address */
906 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
908 /* Get bus range if any */
909 bus_range = of_get_property(dev, "bus-range", &len);
910 if (bus_range == NULL || len < 2 * sizeof(int)) {
911 printk(KERN_WARNING "Can't get bus-range for %s, assume"
912 " bus 0\n", dev->full_name);
915 hose = pcibios_alloc_controller(dev);
918 hose->first_busno = bus_range ? bus_range[0] : 0;
919 hose->last_busno = bus_range ? bus_range[1] : 0xff;
923 /* 64 bits only bridges */
925 if (of_device_is_compatible(dev, "u3-agp")) {
927 disp_name = "U3-AGP";
929 } else if (of_device_is_compatible(dev, "u3-ht")) {
933 } else if (of_device_is_compatible(dev, "u4-pcie")) {
935 disp_name = "U4-PCIE";
938 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number:"
939 " %d->%d\n", disp_name, hose->first_busno, hose->last_busno);
940 #endif /* CONFIG_PPC64 */
942 /* 32 bits only bridges */
944 if (of_device_is_compatible(dev, "uni-north")) {
945 primary = setup_uninorth(hose, &rsrc);
946 disp_name = "UniNorth";
947 } else if (strcmp(dev->name, "pci") == 0) {
948 /* XXX assume this is a mpc106 (grackle) */
950 disp_name = "Grackle (MPC106)";
951 } else if (strcmp(dev->name, "bandit") == 0) {
952 setup_bandit(hose, &rsrc);
953 disp_name = "Bandit";
954 } else if (strcmp(dev->name, "chaos") == 0) {
955 setup_chaos(hose, &rsrc);
959 printk(KERN_INFO "Found %s PCI host bridge at 0x%016llx. "
960 "Firmware bus number: %d->%d\n",
961 disp_name, (unsigned long long)rsrc.start, hose->first_busno,
963 #endif /* CONFIG_PPC32 */
965 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
966 hose, hose->cfg_addr, hose->cfg_data);
968 /* Interpret the "ranges" property */
969 /* This also maps the I/O region and sets isa_io/mem_base */
970 pci_process_bridge_OF_ranges(hose, dev, primary);
972 /* Fixup "bus-range" OF property */
973 fixup_bus_range(dev);
978 void __devinit pmac_pci_irq_fixup(struct pci_dev *dev)
981 /* Fixup interrupt for the modem/ethernet combo controller.
982 * on machines with a second ohare chip.
983 * The number in the device tree (27) is bogus (correct for
984 * the ethernet-only board but not the combo ethernet/modem
985 * board). The real interrupt is 28 on the second controller
988 if (has_second_ohare &&
989 dev->vendor == PCI_VENDOR_ID_DEC &&
990 dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) {
991 dev->irq = irq_create_mapping(NULL, 60);
992 irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
994 #endif /* CONFIG_PPC32 */
997 void __init pmac_pci_init(void)
999 struct device_node *np, *root;
1000 struct device_node *ht = NULL;
1002 ppc_pci_set_flags(PPC_PCI_CAN_SKIP_ISA_ALIGN);
1004 root = of_find_node_by_path("/");
1006 printk(KERN_CRIT "pmac_pci_init: can't find root "
1007 "of device tree\n");
1010 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
1011 if (np->name == NULL)
1013 if (strcmp(np->name, "bandit") == 0
1014 || strcmp(np->name, "chaos") == 0
1015 || strcmp(np->name, "pci") == 0) {
1016 if (pmac_add_bridge(np) == 0)
1019 if (strcmp(np->name, "ht") == 0) {
1027 /* Probe HT last as it relies on the agp resources to be already
1030 if (ht && pmac_add_bridge(ht) != 0)
1033 /* Setup the linkage between OF nodes and PHBs */
1034 pci_devs_phb_init();
1036 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
1037 * assume there is no P2P bridge on the AGP bus, which should be a
1038 * safe assumptions for now. We should do something better in the
1042 struct device_node *np = u3_agp->dn;
1043 PCI_DN(np)->busno = 0xf0;
1044 for (np = np->child; np; np = np->sibling)
1045 PCI_DN(np)->busno = 0xf0;
1047 /* pmac_check_ht_link(); */
1049 /* We can allocate missing resources if any */
1052 #else /* CONFIG_PPC64 */
1054 init_second_ohare();
1057 /* We are still having some issues with the Xserve G4, enabling
1058 * some offset between bus number and domains for now when we
1059 * assign all busses should help for now
1061 if (ppc_pci_has_flag(PPC_PCI_REASSIGN_ALL_BUS))
1062 pcibios_assign_bus_offset = 0x10;
1067 int pmac_pci_enable_device_hook(struct pci_dev *dev)
1069 struct device_node* node;
1073 node = pci_device_to_OF_node(dev);
1075 /* We don't want to enable USB controllers absent from the OF tree
1076 * (iBook second controller)
1078 if (dev->vendor == PCI_VENDOR_ID_APPLE
1079 && dev->class == PCI_CLASS_SERIAL_USB_OHCI
1081 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n",
1089 uninorth_child = node->parent &&
1090 of_device_is_compatible(node->parent, "uni-north");
1092 /* Firewire & GMAC were disabled after PCI probe, the driver is
1093 * claiming them, we must re-enable them now.
1095 if (uninorth_child && !strcmp(node->name, "firewire") &&
1096 (of_device_is_compatible(node, "pci106b,18") ||
1097 of_device_is_compatible(node, "pci106b,30") ||
1098 of_device_is_compatible(node, "pci11c1,5811"))) {
1099 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1);
1100 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1);
1103 if (uninorth_child && !strcmp(node->name, "ethernet") &&
1104 of_device_is_compatible(node, "gmac")) {
1105 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1);
1110 * Fixup various header fields on 32 bits. We don't do that on
1111 * 64 bits as some of these have strange values behind the HT
1112 * bridge and we must not, for example, enable MWI or set the
1113 * cache line size on them.
1118 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1119 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
1120 | PCI_COMMAND_INVALIDATE;
1121 pci_write_config_word(dev, PCI_COMMAND, cmd);
1122 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16);
1124 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
1125 L1_CACHE_BYTES >> 2);
1131 void __devinit pmac_pci_fixup_ohci(struct pci_dev *dev)
1133 struct device_node *node = pci_device_to_OF_node(dev);
1135 /* We don't want to assign resources to USB controllers
1136 * absent from the OF tree (iBook second controller)
1138 if (dev->class == PCI_CLASS_SERIAL_USB_OHCI && !node)
1139 dev->resource[0].flags = 0;
1141 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_ANY_ID, pmac_pci_fixup_ohci);
1143 /* We power down some devices after they have been probed. They'll
1144 * be powered back on later on
1146 void __init pmac_pcibios_after_init(void)
1148 struct device_node* nd;
1150 for_each_node_by_name(nd, "firewire") {
1151 if (nd->parent && (of_device_is_compatible(nd, "pci106b,18") ||
1152 of_device_is_compatible(nd, "pci106b,30") ||
1153 of_device_is_compatible(nd, "pci11c1,5811"))
1154 && of_device_is_compatible(nd->parent, "uni-north")) {
1155 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0);
1156 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0);
1159 for_each_node_by_name(nd, "ethernet") {
1160 if (nd->parent && of_device_is_compatible(nd, "gmac")
1161 && of_device_is_compatible(nd->parent, "uni-north"))
1162 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0);
1166 void pmac_pci_fixup_cardbus(struct pci_dev* dev)
1168 if (!machine_is(powermac))
1171 * Fix the interrupt routing on the various cardbus bridges
1172 * used on powerbooks
1174 if (dev->vendor != PCI_VENDOR_ID_TI)
1176 if (dev->device == PCI_DEVICE_ID_TI_1130 ||
1177 dev->device == PCI_DEVICE_ID_TI_1131) {
1179 /* Enable PCI interrupt */
1180 if (pci_read_config_byte(dev, 0x91, &val) == 0)
1181 pci_write_config_byte(dev, 0x91, val | 0x30);
1182 /* Disable ISA interrupt mode */
1183 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1184 pci_write_config_byte(dev, 0x92, val & ~0x06);
1186 if (dev->device == PCI_DEVICE_ID_TI_1210 ||
1187 dev->device == PCI_DEVICE_ID_TI_1211 ||
1188 dev->device == PCI_DEVICE_ID_TI_1410 ||
1189 dev->device == PCI_DEVICE_ID_TI_1510) {
1191 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
1192 signal out the MFUNC0 pin */
1193 if (pci_read_config_byte(dev, 0x8c, &val) == 0)
1194 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2);
1195 /* Disable ISA interrupt mode */
1196 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1197 pci_write_config_byte(dev, 0x92, val & ~0x06);
1201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus);
1203 void pmac_pci_fixup_pciata(struct pci_dev* dev)
1208 * On PowerMacs, we try to switch any PCI ATA controller to
1211 if (!machine_is(powermac))
1214 /* Some controllers don't have the class IDE */
1215 if (dev->vendor == PCI_VENDOR_ID_PROMISE)
1216 switch(dev->device) {
1217 case PCI_DEVICE_ID_PROMISE_20246:
1218 case PCI_DEVICE_ID_PROMISE_20262:
1219 case PCI_DEVICE_ID_PROMISE_20263:
1220 case PCI_DEVICE_ID_PROMISE_20265:
1221 case PCI_DEVICE_ID_PROMISE_20267:
1222 case PCI_DEVICE_ID_PROMISE_20268:
1223 case PCI_DEVICE_ID_PROMISE_20269:
1224 case PCI_DEVICE_ID_PROMISE_20270:
1225 case PCI_DEVICE_ID_PROMISE_20271:
1226 case PCI_DEVICE_ID_PROMISE_20275:
1227 case PCI_DEVICE_ID_PROMISE_20276:
1228 case PCI_DEVICE_ID_PROMISE_20277:
1231 /* Others, check PCI class */
1232 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
1235 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1236 if ((progif & 5) != 5) {
1237 printk(KERN_INFO "PCI: %s Forcing PCI IDE into native mode\n",
1239 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
1240 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
1242 printk(KERN_ERR "Rewrite of PROGIF failed !\n");
1244 /* Clear IO BARs, they will be reassigned */
1245 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
1246 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
1247 pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0);
1248 pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, 0);
1252 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata);
1253 #endif /* CONFIG_PPC32 */
1256 * Disable second function on K2-SATA, it's broken
1257 * and disable IO BARs on first one
1259 static void fixup_k2_sata(struct pci_dev* dev)
1264 if (PCI_FUNC(dev->devfn) > 0) {
1265 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1266 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1267 pci_write_config_word(dev, PCI_COMMAND, cmd);
1268 for (i = 0; i < 6; i++) {
1269 dev->resource[i].start = dev->resource[i].end = 0;
1270 dev->resource[i].flags = 0;
1271 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i,
1275 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1276 cmd &= ~PCI_COMMAND_IO;
1277 pci_write_config_word(dev, PCI_COMMAND, cmd);
1278 for (i = 0; i < 5; i++) {
1279 dev->resource[i].start = dev->resource[i].end = 0;
1280 dev->resource[i].flags = 0;
1281 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i,
1286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata);
1289 * On U4 (aka CPC945) the PCIe root complex "P2P" bridge resource ranges aren't
1290 * configured by the firmware. The bridge itself seems to ignore them but it
1291 * causes problems with Linux which then re-assigns devices below the bridge,
1292 * thus changing addresses of those devices from what was in the device-tree,
1293 * which sucks when those are video cards using offb
1295 * We could just mark it transparent but I prefer fixing up the resources to
1296 * properly show what's going on here, as I have some doubts about having them
1297 * badly configured potentially being an issue for DMA.
1299 * We leave PIO alone, it seems to be fine
1301 * Oh and there's another funny bug. The OF properties advertize the region
1302 * 0xf1000000..0xf1ffffff as being forwarded as memory space. But that's
1303 * actually not true, this region is the memory mapped config space. So we
1304 * also need to filter it out or we'll map things in the wrong place.
1306 static void fixup_u4_pcie(struct pci_dev* dev)
1308 struct pci_controller *host = pci_bus_to_host(dev->bus);
1309 struct resource *region = NULL;
1313 /* Only do that on PowerMac */
1314 if (!machine_is(powermac))
1317 /* Find the largest MMIO region */
1318 for (i = 0; i < 3; i++) {
1319 struct resource *r = &host->mem_resources[i];
1320 if (!(r->flags & IORESOURCE_MEM))
1322 /* Skip the 0xf0xxxxxx..f2xxxxxx regions, we know they
1323 * are reserved by HW for other things
1325 if (r->start >= 0xf0000000 && r->start < 0xf3000000)
1327 if (!region || (r->end - r->start) >
1328 (region->end - region->start))
1331 /* Nothing found, bail */
1335 /* Print things out */
1336 printk(KERN_INFO "PCI: Fixup U4 PCIe bridge range: %pR\n", region);
1338 /* Fixup bridge config space. We know it's a Mac, resource aren't
1339 * offset so let's just blast them as-is. We also know that they
1342 reg = ((region->start >> 16) & 0xfff0) | (region->end & 0xfff00000);
1343 pci_write_config_dword(dev, PCI_MEMORY_BASE, reg);
1344 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0);
1345 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
1346 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0);
1348 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_U4_PCIE, fixup_u4_pcie);