2 * Copyright (C) 2006-2007 PA Semi, Inc
4 * Authors: Kip Walker, PA Semi
5 * Olof Johansson, PA Semi
7 * Maintained by: Olof Johansson <olof@lixom.net>
9 * Based on arch/powerpc/platforms/maple/setup.c
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/errno.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/console.h>
29 #include <linux/pci.h>
30 #include <linux/of_platform.h>
33 #include <asm/system.h>
34 #include <asm/iommu.h>
35 #include <asm/machdep.h>
41 #include <pcmcia/ss.h>
42 #include <pcmcia/cistpl.h>
43 #include <pcmcia/ds.h>
47 /* SDC reset register, must be pre-mapped at reset time */
48 static void __iomem *reset_reg;
50 /* Various error status registers, must be pre-mapped at MCE time */
52 #define MAX_MCE_REGS 32
58 static struct mce_regs mce_regs[MAX_MCE_REGS];
59 static int num_mce_regs;
60 static int nmi_virq = NO_IRQ;
63 static void pas_restart(char *cmd)
65 /* Need to put others cpu in hold loop so they're not sleeping */
68 printk("Restarting...\n");
70 out_le32(reset_reg, 0x6000000);
74 static raw_spinlock_t timebase_lock;
75 static unsigned long timebase;
77 static void __devinit pas_give_timebase(void)
81 local_irq_save(flags);
83 __raw_spin_lock(&timebase_lock);
84 mtspr(SPRN_TBCTL, TBCTL_FREEZE);
87 __raw_spin_unlock(&timebase_lock);
91 mtspr(SPRN_TBCTL, TBCTL_RESTART);
92 local_irq_restore(flags);
95 static void __devinit pas_take_timebase(void)
100 __raw_spin_lock(&timebase_lock);
101 set_tb(timebase >> 32, timebase & 0xffffffff);
103 __raw_spin_unlock(&timebase_lock);
106 struct smp_ops_t pas_smp_ops = {
107 .probe = smp_mpic_probe,
108 .message_pass = smp_mpic_message_pass,
109 .kick_cpu = smp_generic_kick_cpu,
110 .setup_cpu = smp_mpic_setup_cpu,
111 .give_timebase = pas_give_timebase,
112 .take_timebase = pas_take_timebase,
114 #endif /* CONFIG_SMP */
116 void __init pas_setup_arch(void)
119 /* Setup SMP callback */
120 smp_ops = &pas_smp_ops;
122 /* Lookup PCI hosts */
125 #ifdef CONFIG_DUMMY_CONSOLE
126 conswitchp = &dummy_con;
129 /* Remap SDC register for doing reset */
130 /* XXXOJN This should maybe come out of the device tree */
131 reset_reg = ioremap(0xfc101100, 4);
134 static int __init pas_setup_mce_regs(void)
139 /* Remap various SoC status registers for use by the MCE handler */
143 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL);
144 while (dev && reg < MAX_MCE_REGS) {
145 mce_regs[reg].name = kasprintf(GFP_KERNEL,
146 "mc%d_mcdebug_errsta", reg);
147 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730);
148 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev);
152 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
153 if (dev && reg+4 < MAX_MCE_REGS) {
154 mce_regs[reg].name = "iobdbg_IntStatus1";
155 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438);
157 mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg";
158 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454);
160 mce_regs[reg].name = "iobiom_IntStatus";
161 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10);
163 mce_regs[reg].name = "iobiom_IntDbgReg";
164 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c);
168 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL);
169 if (dev && reg+2 < MAX_MCE_REGS) {
170 mce_regs[reg].name = "l2csts_IntStatus";
171 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200);
173 mce_regs[reg].name = "l2csts_Cnt";
174 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214);
182 machine_device_initcall(pasemi, pas_setup_mce_regs);
184 static __init void pas_init_IRQ(void)
186 struct device_node *np;
187 struct device_node *root, *mpic_node;
188 unsigned long openpic_addr;
189 const unsigned int *opprop;
192 const unsigned int *nmiprop;
197 for_each_node_by_type(np, "interrupt-controller")
198 if (of_device_is_compatible(np, "open-pic")) {
203 for_each_node_by_type(np, "open-pic") {
209 "Failed to locate the MPIC interrupt controller\n");
213 /* Find address list in /platform-open-pic */
214 root = of_find_node_by_path("/");
215 naddr = of_n_addr_cells(root);
216 opprop = of_get_property(root, "platform-open-pic", &opplen);
218 printk(KERN_ERR "No platform-open-pic property.\n");
222 openpic_addr = of_read_number(opprop, naddr);
223 printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr);
225 mpic_flags = MPIC_PRIMARY | MPIC_LARGE_VECTORS | MPIC_NO_BIAS;
227 nmiprop = of_get_property(mpic_node, "nmi-source", NULL);
229 mpic_flags |= MPIC_ENABLE_MCK;
231 mpic = mpic_alloc(mpic_node, openpic_addr,
232 mpic_flags, 0, 0, "PASEMI-OPIC");
235 mpic_assign_isu(mpic, 0, openpic_addr + 0x10000);
237 /* The NMI/MCK source needs to be prio 15 */
239 nmi_virq = irq_create_mapping(NULL, *nmiprop);
240 mpic_irq_set_priority(nmi_virq, 15);
241 set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING);
242 mpic_unmask_irq(nmi_virq);
245 of_node_put(mpic_node);
249 static void __init pas_progress(char *s, unsigned short hex)
251 printk("[%04x] : %s\n", hex, s ? s : "");
255 static int pas_machine_check_handler(struct pt_regs *regs)
257 int cpu = smp_processor_id();
258 unsigned long srr0, srr1, dsisr;
265 if (nmi_virq != NO_IRQ && mpic_get_mcirq() == nmi_virq) {
266 printk(KERN_ERR "NMI delivered\n");
268 mpic_end_irq(nmi_virq);
272 dsisr = mfspr(SPRN_DSISR);
273 printk(KERN_ERR "Machine Check on CPU %d\n", cpu);
274 printk(KERN_ERR "SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1);
275 printk(KERN_ERR "DSISR 0x%016lx DAR 0x%016lx\n", dsisr, regs->dar);
276 printk(KERN_ERR "BER 0x%016lx MER 0x%016lx\n", mfspr(SPRN_PA6T_BER),
277 mfspr(SPRN_PA6T_MER));
278 printk(KERN_ERR "IER 0x%016lx DER 0x%016lx\n", mfspr(SPRN_PA6T_IER),
279 mfspr(SPRN_PA6T_DER));
280 printk(KERN_ERR "Cause:\n");
283 printk(KERN_ERR "Signalled by SDC\n");
285 if (srr1 & 0x100000) {
286 printk(KERN_ERR "Load/Store detected error:\n");
288 printk(KERN_ERR "D-cache ECC double-bit error or bus error\n");
290 printk(KERN_ERR "LSU snoop response error\n");
291 if (dsisr & 0x2000) {
292 printk(KERN_ERR "MMU SLB multi-hit or invalid B field\n");
296 printk(KERN_ERR "Recoverable Duptags\n");
298 printk(KERN_ERR "Recoverable D-cache parity error count overflow\n");
300 printk(KERN_ERR "TLB parity error count overflow\n");
304 printk(KERN_ERR "Bus Error\n");
306 if (srr1 & 0x40000) {
307 printk(KERN_ERR "I-side SLB multiple hit\n");
312 printk(KERN_ERR "I-cache parity error hit\n");
314 if (num_mce_regs == 0)
315 printk(KERN_ERR "No MCE registers mapped yet, can't dump\n");
317 printk(KERN_ERR "SoC debug registers:\n");
319 for (i = 0; i < num_mce_regs; i++)
320 printk(KERN_ERR "%s: 0x%08x\n", mce_regs[i].name,
321 in_le32(mce_regs[i].addr));
327 printk(KERN_ERR "slb contents:\n");
328 for (i = 0; i < mmu_slb_size; i++) {
329 asm volatile("slbmfee %0,%1" : "=r" (e) : "r" (i));
330 asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i));
331 printk(KERN_ERR "%02d %016lx %016lx\n", i, e, v);
336 /* SRR1[62] is from MSR[62] if recoverable, so pass that back */
337 return !!(srr1 & 0x2);
340 static void __init pas_init_early(void)
342 iommu_init_early_pasemi();
346 static int pcmcia_notify(struct notifier_block *nb, unsigned long action,
349 struct device *dev = data;
350 struct device *parent;
351 struct pcmcia_device *pdev = to_pcmcia_dev(dev);
353 /* We are only intereted in device addition */
354 if (action != BUS_NOTIFY_ADD_DEVICE)
357 parent = pdev->socket->dev.parent;
359 /* We know electra_cf devices will always have of_node set, since
360 * electra_cf is an of_platform driver.
362 if (!parent->archdata.of_node)
365 if (!of_device_is_compatible(parent->archdata.of_node, "electra-cf"))
368 /* We use the direct ops for localbus */
369 dev->archdata.dma_ops = &dma_direct_ops;
374 static struct notifier_block pcmcia_notifier = {
375 .notifier_call = pcmcia_notify,
378 static inline void pasemi_pcmcia_init(void)
380 extern struct bus_type pcmcia_bus_type;
382 bus_register_notifier(&pcmcia_bus_type, &pcmcia_notifier);
387 static inline void pasemi_pcmcia_init(void)
394 static struct of_device_id pasemi_bus_ids[] = {
395 /* Unfortunately needed for legacy firmwares */
396 { .type = "localbus", },
398 /* These are the proper entries, which newer firmware uses */
399 { .compatible = "pasemi,localbus", },
400 { .compatible = "pasemi,sdc", },
404 static int __init pasemi_publish_devices(void)
406 pasemi_pcmcia_init();
408 /* Publish OF platform devices for SDC and other non-PCI devices */
409 of_platform_bus_probe(NULL, pasemi_bus_ids, NULL);
413 machine_device_initcall(pasemi, pasemi_publish_devices);
417 * Called very early, MMU is off, device-tree isn't unflattened
419 static int __init pas_probe(void)
421 unsigned long root = of_get_flat_dt_root();
423 if (!of_flat_dt_is_compatible(root, "PA6T-1682M") &&
424 !of_flat_dt_is_compatible(root, "pasemi,pwrficient"))
434 define_machine(pasemi) {
435 .name = "PA Semi PWRficient",
437 .setup_arch = pas_setup_arch,
438 .init_early = pas_init_early,
439 .init_IRQ = pas_init_IRQ,
440 .get_irq = mpic_get_irq,
441 .restart = pas_restart,
442 .get_boot_time = pas_get_boot_time,
443 .calibrate_decr = generic_calibrate_decr,
444 .progress = pas_progress,
445 .machine_check_exception = pas_machine_check_handler,