2 * Copyright (C) 2006-2007 PA Semi, Inc
4 * Common functions for DMA access on PA Semi PWRficient
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
26 #include <asm/pasemi_dma.h>
31 static struct pasdma_status *dma_status;
33 static void __iomem *iob_regs;
34 static void __iomem *mac_regs[6];
35 static void __iomem *dma_regs;
37 static int base_hw_irq;
39 static int num_txch, num_rxch;
41 static struct pci_dev *dma_pdev;
43 /* Bitmaps to handle allocation of channels */
45 static DECLARE_BITMAP(txch_free, MAX_TXCH);
46 static DECLARE_BITMAP(rxch_free, MAX_RXCH);
48 /* pasemi_read_iob_reg - read IOB register
49 * @reg: Register to read (offset into PCI CFG space)
51 unsigned int pasemi_read_iob_reg(unsigned int reg)
53 return in_le32(iob_regs+reg);
55 EXPORT_SYMBOL(pasemi_read_iob_reg);
57 /* pasemi_write_iob_reg - write IOB register
58 * @reg: Register to write to (offset into PCI CFG space)
59 * @val: Value to write
61 void pasemi_write_iob_reg(unsigned int reg, unsigned int val)
63 out_le32(iob_regs+reg, val);
65 EXPORT_SYMBOL(pasemi_write_iob_reg);
67 /* pasemi_read_mac_reg - read MAC register
68 * @intf: MAC interface
69 * @reg: Register to read (offset into PCI CFG space)
71 unsigned int pasemi_read_mac_reg(int intf, unsigned int reg)
73 return in_le32(mac_regs[intf]+reg);
75 EXPORT_SYMBOL(pasemi_read_mac_reg);
77 /* pasemi_write_mac_reg - write MAC register
78 * @intf: MAC interface
79 * @reg: Register to write to (offset into PCI CFG space)
80 * @val: Value to write
82 void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val)
84 out_le32(mac_regs[intf]+reg, val);
86 EXPORT_SYMBOL(pasemi_write_mac_reg);
88 /* pasemi_read_dma_reg - read DMA register
89 * @reg: Register to read (offset into PCI CFG space)
91 unsigned int pasemi_read_dma_reg(unsigned int reg)
93 return in_le32(dma_regs+reg);
95 EXPORT_SYMBOL(pasemi_read_dma_reg);
97 /* pasemi_write_dma_reg - write DMA register
98 * @reg: Register to write to (offset into PCI CFG space)
99 * @val: Value to write
101 void pasemi_write_dma_reg(unsigned int reg, unsigned int val)
103 out_le32(dma_regs+reg, val);
105 EXPORT_SYMBOL(pasemi_write_dma_reg);
107 static int pasemi_alloc_tx_chan(enum pasemi_dmachan_type type)
112 switch (type & (TXCHAN_EVT0|TXCHAN_EVT1)) {
127 bit = find_next_bit(txch_free, MAX_TXCH, start);
130 if (!test_and_clear_bit(bit, txch_free))
136 static void pasemi_free_tx_chan(int chan)
138 BUG_ON(test_bit(chan, txch_free));
139 set_bit(chan, txch_free);
142 static int pasemi_alloc_rx_chan(void)
146 bit = find_first_bit(rxch_free, MAX_RXCH);
149 if (!test_and_clear_bit(bit, rxch_free))
155 static void pasemi_free_rx_chan(int chan)
157 BUG_ON(test_bit(chan, rxch_free));
158 set_bit(chan, rxch_free);
161 /* pasemi_dma_alloc_chan - Allocate a DMA channel
162 * @type: Type of channel to allocate
163 * @total_size: Total size of structure to allocate (to allow for more
164 * room behind the structure to be used by the client)
165 * @offset: Offset in bytes from start of the total structure to the beginning
166 * of struct pasemi_dmachan. Needed when struct pasemi_dmachan is
167 * not the first member of the client structure.
169 * pasemi_dma_alloc_chan allocates a DMA channel for use by a client. The
170 * type argument specifies whether it's a RX or TX channel, and in the case
171 * of TX channels which group it needs to belong to (if any).
173 * Returns a pointer to the total structure allocated on success, NULL
176 void *pasemi_dma_alloc_chan(enum pasemi_dmachan_type type,
177 int total_size, int offset)
180 struct pasemi_dmachan *chan;
183 BUG_ON(total_size < sizeof(struct pasemi_dmachan));
185 buf = kzalloc(total_size, GFP_KERNEL);
193 switch (type & (TXCHAN|RXCHAN)) {
195 chno = pasemi_alloc_rx_chan();
197 chan->irq = irq_create_mapping(NULL,
198 base_hw_irq + num_txch + chno);
199 chan->status = &dma_status->rx_sta[chno];
202 chno = pasemi_alloc_tx_chan(type);
204 chan->irq = irq_create_mapping(NULL, base_hw_irq + chno);
205 chan->status = &dma_status->tx_sta[chno];
209 chan->chan_type = type;
213 EXPORT_SYMBOL(pasemi_dma_alloc_chan);
215 /* pasemi_dma_free_chan - Free a previously allocated channel
216 * @chan: Channel to free
218 * Frees a previously allocated channel. It will also deallocate any
219 * descriptor ring associated with the channel, if allocated.
221 void pasemi_dma_free_chan(struct pasemi_dmachan *chan)
224 pasemi_dma_free_ring(chan);
226 switch (chan->chan_type & (RXCHAN|TXCHAN)) {
228 pasemi_free_rx_chan(chan->chno);
231 pasemi_free_tx_chan(chan->chno);
237 EXPORT_SYMBOL(pasemi_dma_free_chan);
239 /* pasemi_dma_alloc_ring - Allocate descriptor ring for a channel
240 * @chan: Channel for which to allocate
241 * @ring_size: Ring size in 64-bit (8-byte) words
243 * Allocate a descriptor ring for a channel. Returns 0 on success, errno
244 * on failure. The passed in struct pasemi_dmachan is updated with the
245 * virtual and DMA addresses of the ring.
247 int pasemi_dma_alloc_ring(struct pasemi_dmachan *chan, int ring_size)
249 BUG_ON(chan->ring_virt);
251 chan->ring_size = ring_size;
253 chan->ring_virt = dma_alloc_coherent(&dma_pdev->dev,
254 ring_size * sizeof(u64),
255 &chan->ring_dma, GFP_KERNEL);
257 if (!chan->ring_virt)
260 memset(chan->ring_virt, 0, ring_size * sizeof(u64));
264 EXPORT_SYMBOL(pasemi_dma_alloc_ring);
266 /* pasemi_dma_free_ring - Free an allocated descriptor ring for a channel
267 * @chan: Channel for which to free the descriptor ring
269 * Frees a previously allocated descriptor ring for a channel.
271 void pasemi_dma_free_ring(struct pasemi_dmachan *chan)
273 BUG_ON(!chan->ring_virt);
275 dma_free_coherent(&dma_pdev->dev, chan->ring_size * sizeof(u64),
276 chan->ring_virt, chan->ring_dma);
277 chan->ring_virt = NULL;
281 EXPORT_SYMBOL(pasemi_dma_free_ring);
283 /* pasemi_dma_start_chan - Start a DMA channel
284 * @chan: Channel to start
285 * @cmdsta: Additional CCMDSTA/TCMDSTA bits to write
287 * Enables (starts) a DMA channel with optional additional arguments.
289 void pasemi_dma_start_chan(const struct pasemi_dmachan *chan, const u32 cmdsta)
291 if (chan->chan_type == RXCHAN)
292 pasemi_write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno),
293 cmdsta | PAS_DMA_RXCHAN_CCMDSTA_EN);
295 pasemi_write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno),
296 cmdsta | PAS_DMA_TXCHAN_TCMDSTA_EN);
298 EXPORT_SYMBOL(pasemi_dma_start_chan);
300 /* pasemi_dma_stop_chan - Stop a DMA channel
301 * @chan: Channel to stop
303 * Stops (disables) a DMA channel. This is done by setting the ST bit in the
304 * CMDSTA register and waiting on the ACT (active) bit to clear, then
305 * finally disabling the whole channel.
307 * This function will only try for a short while for the channel to stop, if
308 * it doesn't it will return failure.
310 * Returns 1 on success, 0 on failure.
312 #define MAX_RETRIES 5000
313 int pasemi_dma_stop_chan(const struct pasemi_dmachan *chan)
318 if (chan->chan_type == RXCHAN) {
319 reg = PAS_DMA_RXCHAN_CCMDSTA(chan->chno);
320 pasemi_write_dma_reg(reg, PAS_DMA_RXCHAN_CCMDSTA_ST);
321 for (retries = 0; retries < MAX_RETRIES; retries++) {
322 sta = pasemi_read_dma_reg(reg);
323 if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)) {
324 pasemi_write_dma_reg(reg, 0);
330 reg = PAS_DMA_TXCHAN_TCMDSTA(chan->chno);
331 pasemi_write_dma_reg(reg, PAS_DMA_TXCHAN_TCMDSTA_ST);
332 for (retries = 0; retries < MAX_RETRIES; retries++) {
333 sta = pasemi_read_dma_reg(reg);
334 if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)) {
335 pasemi_write_dma_reg(reg, 0);
344 EXPORT_SYMBOL(pasemi_dma_stop_chan);
346 /* pasemi_dma_alloc_buf - Allocate a buffer to use for DMA
347 * @chan: Channel to allocate for
348 * @size: Size of buffer in bytes
349 * @handle: DMA handle
351 * Allocate a buffer to be used by the DMA engine for read/write,
352 * similar to dma_alloc_coherent().
354 * Returns the virtual address of the buffer, or NULL in case of failure.
356 void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size,
359 return dma_alloc_coherent(&dma_pdev->dev, size, handle, GFP_KERNEL);
361 EXPORT_SYMBOL(pasemi_dma_alloc_buf);
363 /* pasemi_dma_free_buf - Free a buffer used for DMA
364 * @chan: Channel the buffer was allocated for
365 * @size: Size of buffer in bytes
366 * @handle: DMA handle
368 * Frees a previously allocated buffer.
370 void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size,
373 dma_free_coherent(&dma_pdev->dev, size, handle, GFP_KERNEL);
375 EXPORT_SYMBOL(pasemi_dma_free_buf);
377 static void *map_onedev(struct pci_dev *p, int index)
379 struct device_node *dn;
382 dn = pci_device_to_OF_node(p);
386 ret = of_iomap(dn, index);
392 /* This is hardcoded and ugly, but we have some firmware versions
393 * that don't provide the register space in the device tree. Luckily
394 * they are at well-known locations so we can just do the math here.
396 return ioremap(0xe0000000 + (p->devfn << 12), 0x2000);
399 /* pasemi_dma_init - Initialize the PA Semi DMA library
401 * This function initializes the DMA library. It must be called before
402 * any other function in the library.
404 * Returns 0 on success, errno on failure.
406 int pasemi_dma_init(void)
408 static spinlock_t init_lock = SPIN_LOCK_UNLOCKED;
409 struct pci_dev *iob_pdev;
410 struct pci_dev *pdev;
412 struct device_node *dn;
413 int i, intf, err = 0;
414 unsigned long timeout;
417 if (!machine_is(pasemi))
420 spin_lock(&init_lock);
422 /* Make sure we haven't already initialized */
426 iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
429 printk(KERN_WARNING "Can't find I/O Bridge\n");
433 iob_regs = map_onedev(iob_pdev, 0);
435 dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
438 printk(KERN_WARNING "Can't find DMA controller\n");
442 dma_regs = map_onedev(dma_pdev, 0);
443 base_hw_irq = virq_to_hw(dma_pdev->irq);
445 pci_read_config_dword(dma_pdev, PAS_DMA_CAP_TXCH, &tmp);
446 num_txch = (tmp & PAS_DMA_CAP_TXCH_TCHN_M) >> PAS_DMA_CAP_TXCH_TCHN_S;
448 pci_read_config_dword(dma_pdev, PAS_DMA_CAP_RXCH, &tmp);
449 num_rxch = (tmp & PAS_DMA_CAP_RXCH_RCHN_M) >> PAS_DMA_CAP_RXCH_RCHN_S;
452 for (pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa006, NULL);
454 pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa006, pdev))
455 mac_regs[intf++] = map_onedev(pdev, 0);
459 for (pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa005, NULL);
461 pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa005, pdev))
462 mac_regs[intf++] = map_onedev(pdev, 0);
466 dn = pci_device_to_OF_node(iob_pdev);
468 err = of_address_to_resource(dn, 1, &res);
470 /* Fallback for old firmware */
471 res.start = 0xfd800000;
472 res.end = res.start + 0x1000;
474 dma_status = __ioremap(res.start, res.end-res.start, 0);
475 pci_dev_put(iob_pdev);
477 for (i = 0; i < MAX_TXCH; i++)
478 __set_bit(i, txch_free);
480 for (i = 0; i < MAX_RXCH; i++)
481 __set_bit(i, rxch_free);
483 timeout = jiffies + HZ;
484 pasemi_write_dma_reg(PAS_DMA_COM_RXCMD, 0);
485 while (pasemi_read_dma_reg(PAS_DMA_COM_RXSTA) & 1) {
486 if (time_after(jiffies, timeout)) {
487 pr_warning("Warning: Could not disable RX section\n");
492 timeout = jiffies + HZ;
493 pasemi_write_dma_reg(PAS_DMA_COM_TXCMD, 0);
494 while (pasemi_read_dma_reg(PAS_DMA_COM_TXSTA) & 1) {
495 if (time_after(jiffies, timeout)) {
496 pr_warning("Warning: Could not disable TX section\n");
501 /* setup resource allocations for the different DMA sections */
502 tmp = pasemi_read_dma_reg(PAS_DMA_COM_CFG);
503 pasemi_write_dma_reg(PAS_DMA_COM_CFG, tmp | 0x18000000);
505 /* enable tx section */
506 pasemi_write_dma_reg(PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN);
508 /* enable rx section */
509 pasemi_write_dma_reg(PAS_DMA_COM_RXCMD, PAS_DMA_COM_RXCMD_EN);
511 printk(KERN_INFO "PA Semi PWRficient DMA library initialized "
512 "(%d tx, %d rx channels)\n", num_txch, num_rxch);
515 spin_unlock(&init_lock);
518 EXPORT_SYMBOL(pasemi_dma_init);